NEC 78K/0 Series - Manuals - manualsarea.com

Page 3 - IEBus is a trademark of NEC Corporation.; NOTES FOR CMOS DEVICES; PRECAUTION AGAINST ESD FOR SEMICONDUCTORS; to be taken for PW boards with semiconductor devices on it.; HANDLING OF UNUSED INPUT PINS FOR CMOS; pin should be connected to V; or GND with a resistor, if it is considered to have a possibility of; STATUS BEFORE INITIALIZATION OF MOS DEVICES; having reset function.

3 User's Manual U12326EJ4V0UM Caution: Purchase of NEC I 2 C components conveys a license under the Philips I 2 C Patent Rights to use these components in an I 2 C system, provided that the system conforms to the I 2 C Standard Specification as defined by Philips. IEBus is a trademark of NEC Corpora...

Page 4 - s u p p o r t s y s t e m s a n d m e d i c a l e q u i p m e n t f o r l i f e s u p p o r t , e t c .

4 User's Manual U12326EJ4V0UM The export of these products from Japan is regulated by the Japanese government. The export of some or all of theseproducts may be prohibited without governmental license. To export or re-export some or all of these products from ac o u n t r y o t h e r t h a n J a p a...

Page 5 - Regional Information; Device availability

5 User's Manual U12326EJ4V0UM Regional Information Some information contained in this document may vary from country to country. Before using any NECproduct in your application, pIease contact the NEC office in your country to obtain a list of authorizedrepresentatives and distributors. They will ve...

Page 6 - Major Revisions in This Edition; Page; The mark shows major revised points.

6 User's Manual U12326EJ4V0UM Major Revisions in This Edition Page Description Throughout Deletion of all information except for information common to the 78K/0 Series (for individual product information, refer to the user’s manual of each product). The mark shows major revised points.

Page 7 - INTRODUCTION

7 User's Manual U12326EJ4V0UM INTRODUCTION Target Readers This manual is intended for users who wish to understand the functions of 78K/0 Series products and to design and develop its application systems and programs. Purpose This manual is intended to give users an understanding of the various kind...

Page 8 - Related Documents; versions are not marked as such.; • Documents Common to 78K/0 Series; Note; Some subseries may not be covered.; latest version of each document for designing.

8 User's Manual U12326EJ4V0UM Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. • Documents Common to 78K/0 Series Document Name Document No. User’s Manual Instructions This manual Application...

Page 11 - LIST OF FIGURES; LIST OF TABLES; Title

11 User's Manual U12326EJ4V0UM LIST OF FIGURES Figure No. Title Page 2-1 Program Counter Configuration .............................................................................................................. 14 2-2 Program Status Word Configuration ................................................

Page 12 - CHAPTER 1 MEMORY SPACE; ROM space, refer to the user’s manual of each product.; Vector Table Area; area, refer to the user’s manual of each product.; CALLT Instruction Table Area; The internal high-speed RAM can also be used as a stack memory.

12 User's Manual U12326EJ4V0UM CHAPTER 1 MEMORY SPACE 1.1 Memory Spaces The 78K/0 Series product program memory map varies depending on the internal memory capacity. For details of memory-mapped address area, refer to the user’s manual of each product. 1.2 Internal Program Memory (Internal ROM) Spac...

Page 13 - CHAPTER 1 MEMORY SPACE; also be used as an ordinary RAM area.; External Memory Space; Register Area

13 CHAPTER 1 MEMORY SPACE User's Manual U12326EJ4V0UM (3) RAM for VFD display There are some products in the 78K/0 Series to which RAM for VFD display is allocated. This RAM can also be used as an ordinary RAM area. (4) Internal expansion RAM There are some products in the 78K/0 Series to which inte...

Page 14 - status word and a stack pointer are the control registers.; Figure 2-1. Program Counter Configuration; RESET input sets the PSW to 02H.; Figure 2-2. Program Status Word Configuration

14 User's Manual U12326EJ4V0UM CHAPTER 2 REGISTERS 2.1 Control Registers The control registers control the program sequence, statuses and stack memory. A program counter, a program status word and a stack pointer are the control registers. 2.1.1 Program counter (PC) The program counter is a 16-bit r...

Page 15 - CHAPTER 2 REGISTERS; execution of the EI instruction.

15 CHAPTER 2 REGISTERS User's Manual U12326EJ4V0UM (1) Interrupt enable flag (IE) This flag controls the interrupt request acknowledgement operations of the CPU. When IE = 0, the IE flag is set to interrupt disable (DI), and interrupts other than non-maskable interrupts are all disabled. When IE = 1...

Page 16 - RAM area can be set as the stack area.; Figure 2-4. Data to Be Saved to Stack Memory

16 CHAPTER 2 REGISTERS User's Manual U12326EJ4V0UM Interrupt andBRK instructions PSW PC15-PC8 PC15-PC8 PC7-PC0 Lower halfregister pairs SP SP _ 2 SP _ 2 CALL, CALLF andCALLT instructions PUSH rpinstruction SP _ 1 SP SP SP _ 2 SP _ 2 SP _ 1 SP PC7-PC0 SP _ 3 SP _ 2 SP _ 1 SP SP SP _ 3 Upper halfregis...

Page 19 - Each manipulation bit unit can be specified as follows.

19 CHAPTER 2 REGISTERS User's Manual U12326EJ4V0UM 2.3 Special Function Registers (SFRs) Unlike a general-purpose register, each special-function register has a special function. Special function registers are allocated in the 256-byte area FF00H to FFFFH. Special function registers can be manipulat...

Page 20 - CHAPTER 5; +127 from the start address of the following instruction.

20 User's Manual U12326EJ4V0UM CHAPTER 3 ADDRESSING 3.1 Instruction Address Addressing An instruction address is determined by program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched eac...

Page 21 - CHAPTER 3 ADDRESSING; CALLF !addr11 instruction is branched to the area of 0800H to 0FFFH.

21 CHAPTER 3 ADDRESSING User's Manual U12326EJ4V0UM 15 0 PC 8 7 7 0 fa 10 to fa 8 11 10 0 0 0 0 1 6 4 3 CALLF fa 7 to fa 0 3.1.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the “CALL...

Page 22 - memory table of 40H to 7FH.

22 CHAPTER 3 ADDRESSING User's Manual U12326EJ4V0UM 15 1 15 0 PC 7 0 Low addr. High addr. Memory (Table) Effective address+1 Effective address 0 1 0 0 0 0 0 0 0 0 8 7 8 7 6 5 0 0 1 1 1 7 6 5 1 0 ta 4–0 Instruction code 3.1.3 Table indirect addressing [Function] Table contents (branch destination add...

Page 24 - Operand Address Addressing; during instruction execution.

24 CHAPTER 3 ADDRESSING User's Manual U12326EJ4V0UM 3.2 Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.2.1 Implied addressing [Function] This addressing automatically specifies the...

Page 25 - MOV A, C When selecting the C register for r

25 CHAPTER 3 ADDRESSING User's Manual U12326EJ4V0UM 3.2.2 Register addressing [Function] Register addressing accesses a general-purpose register as an operand. The general-purpose register to be accessed is specified by the register bank selection flags (RBS0 and RBS1) and the register specification...

Page 27 - manipulated with a small number of bytes and clocks.

27 CHAPTER 3 ADDRESSING User's Manual U12326EJ4V0UM 15 0 Short direct memory Effectiveaddress 1 1 1 1 1 1 1 8 7 0 7 OP code saddr-offset α When 8-bit immediate data is 20H to FFH, α = 0. When 8-bit immediate data is 00H to 1FH, α = 1. 3.2.4 Short direct addressing [Function] The memory to be manipul...

Page 29 - register pair specification in instruction codes.

29 CHAPTER 3 ADDRESSING User's Manual U12326EJ4V0UM 15 0 8 D 7 E 0 7 7 0 A DE Memory Memory address specified by register pair DE Contents of memory to be addressed are transferred 3.2.6 Register indirect addressing [Function] Register indirect addressing addresses memory with register pair contents...

Page 31 - In the case of PUSH DE

31 CHAPTER 3 ADDRESSING User's Manual U12326EJ4V0UM 3.2.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and RETURN instructions are executed or the register...

Page 32 - CHAPTER 4 INSTRUCTION SET; Operand identifiers and description methods; Absolute address specification; Table 4-1. Operand Identifiers and Description Methods; FFD0H to FFDFH are not addressable.; Remark

32 User's Manual U12326EJ4V0UM CHAPTER 4 INSTRUCTION SET This chapter lists the instructions in the 78K/0 Series instruction set. The instructions are common to all 78K/0 Series products. 4.1 Operation For the operation list for each product, refer to the user’s manual of each product. 4.1.1 Operand...

Page 33 - CHAPTER 4 INSTRUCTION SET; Description of “flag operation” column

33 CHAPTER 4 INSTRUCTION SET User's Manual U12326EJ4V0UM 4.1.2 Description of “operation” column A: A register; 8-bit accumulator X: X register B: B register C: C register D: D register E: E register H: H register L: L register AX: AX register pair; 16-bit accumulator BC: BC register pair DE: DE reg...

Page 34 - instruction clock cycle is 1 CPU clock cycle (f; Instructions listed by addressing type

34 CHAPTER 4 INSTRUCTION SET User's Manual U12326EJ4V0UM 4.1.4 Description of number of clocks 1 instruction clock cycle is 1 CPU clock cycle (f CPU ) selected by the processor clock control register (PCC). 4.1.5 Instructions listed by addressing type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB,...

Page 38 - Instruction Codes; Description of instruction code table

38 CHAPTER 4 INSTRUCTION SET User's Manual U12326EJ4V0UM 4.2 Instruction Codes 4.2.1 Description of instruction code table r rp RB R 2 R 1 R 0 reg P 1 P 0 reg-pair RB 1 RB 0 reg-bank 0 0 0 R0 X 0 0 RP0 AX 0 0 RB0 0 0 1 R1 A 0 1 RP1 BC 0 1 RB1 0 1 0 R2 C 1 0 RP2 DE 1 0 RB2 0 1 1 R3 B 1 1 RP3 HL 1 1 R...

Page 39 - XCH

39 CHAPTER 4 INSTRUCTION SET User's Manual U12326EJ4V0UM 4.2.2 Instruction code list Instruction Mnemonic Operands Operation Code Group B1 B2 B3 B4 8-Bit Data MOV r,#byte 1 0 1 0 0 R 2 R 1 R 0 Data Transfer saddr,#byte 0 0 0 1 0 0 0 1 Saddr-offset Data sfr,#byte 0 0 0 1 0 0 1 1 Sfr-offset Data A,r N...

Page 41 - SUBC; AND

41 CHAPTER 4 INSTRUCTION SET User's Manual U12326EJ4V0UM 8-Bit SUB A,#byte 0 0 0 1 1 1 0 1 Data Operation saddr,#byte 1 0 0 1 1 0 0 0 Saddr-offset Data A,r Note 0 1 1 0 0 0 0 1 0 0 0 1 1 R 2 R 1 R 0 r,A 0 1 1 0 0 0 0 1 0 0 0 1 0 R 2 R 1 R 0 A,saddr 0 0 0 1 1 1 1 0 Saddr-offset A,!addr16 0 0 0 1 1 0 ...

Page 42 - XOR; CMP

42 CHAPTER 4 INSTRUCTION SET User's Manual U12326EJ4V0UM 8-Bit OR A,#byte 0 1 1 0 1 1 0 1 Data Operation saddr,#byte 1 1 1 0 1 0 0 0 Saddr-offset Data A,r Note 0 1 1 0 0 0 0 1 0 1 1 0 1 R 2 R 1 R 0 r,A 0 1 1 0 0 0 0 1 0 1 1 0 0 R 2 R 1 R 0 A,saddr 0 1 1 0 1 1 1 0 Saddr-offset A,!addr16 0 1 1 0 1 0 0...

Page 46 - CHAPTER 5 EXPLANATION OF INSTRUCTIONS; including description of multiple operands.; CHAPTER 4 INSTRUCTION SET, respectively.

46 User's Manual U12326EJ4V0UM CHAPTER 5 EXPLANATION OF INSTRUCTIONS This chapter explains the instructions of 78K/0 Series products. Each instruction is described with a mnemonic, including description of multiple operands. The basic configuration of instruction description is shown on the next pag...

Page 47 - CHAPTER 5 EXPLANATION OF INSTRUCTIONS; DESCRIPTION EXAMPLE; Move; Byte Data Transfer; MOV; Conventions

47 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM DESCRIPTION EXAMPLE Mnemonic Full name Move MOV Byte Data Transfer Meaning of instruction [Instruction format] MOV dst, src: Indicates the basic description format of the instruction. [Operation] dst ← src: Indicates instruction op...

Page 48 - The following instructions are 8-bit data transfer instructions.

48 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM 5.1 8-Bit Data Transfer Instructions The following instructions are 8-bit data transfer instructions. MOV ... 49 XCH ... 50

Page 49 - All other operand

49 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Move MOV Byte Data Transfer [Instruction format] MOV dst, src [Operation] dst ← src [Operand] Mnemonic Operand(dst,src) Mnemonic Operand(dst,src) MOV r, #byte MOV A, PSW saddr, #byte PSW, A sfr, #byte A, [DE] A, r Note [DE], A r, A...

Page 50 - Exchange; Byte Data Exchange; The 1st and 2nd operand contents are exchanged.

50 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Exchange XCH Byte Data Exchange [Instruction format] XCH dst, src [Operation] dst ↔ src [Operand] Mnemonic Operand(dst,src) Mnemonic Operand(dst,src) XCH A, r Note XCH A, [HL] A, saddr A, [HL+byte] A, sfr A, [HL+B] A, !addr16 A, [H...

Page 52 - Move Word; Word Data Transfer; MOVW; The HL register contents are transferred to the AX register.

52 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Move Word MOVW Word Data Transfer [Instruction format] MOVW dst, src [Operation] dst ← src [Operand] Mnemonic Operand(dst,src) Mnemonic Operand(dst,src) MOVW rp, #word MOVW sfrp, AX saddrp, #word AX, rp Note sfrp, #word rp, AX Note...

Page 53 - Exchange Word; Word Data Exchange; XCHW

53 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Exchange Word XCHW Word Data Exchange [Instruction format] XCHW dst, src [Operation] dst ↔ src [Operand] Mnemonic Operand(dst,src) XCHW AX, rp Note Note Only when rp = BC, DE or HL [Flag] Z AC CY [Description] • The 1st and 2nd ope...

Page 54 - The following are 8-bit operation instructions.

54 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM 5.3 8-Bit Operation Instructions The following are 8-bit operation instructions. ADD ... 55 ADDC ... 56 SUB ... 57 SUBC ... 58 AND ... 59 OR ... 60 XOR ... 61 CMP ... 62

Page 55 - Add; Byte Data Addition; ADD

55 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Add ADD Byte Data Addition [Instruction format] ADD dst, src [Operation] dst, CY ← dst + src [Operand] Mnemonic Operand(dst,src) Mnemonic Operand(dst,src) ADD A, #byte ADD A, !addr16 saddr, #byte A, [HL] A, r Note A, [HL+byte] r, A...

Page 56 - Add with Carry; Addition of Byte Data with Carry; ADDC; CY flag are added and the result is stored in the A register.

56 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Add with Carry ADDC Addition of Byte Data with Carry [Instruction format] ADDC dst, src [Operation] dst, CY ← dst + src + CY [Operand] Mnemonic Operand(dst,src) Mnemonic Operand(dst,src) ADDC A, #byte ADDC A, !addr16 saddr, #byte A...

Page 57 - Subtract; Byte Data Subtraction; SUB

57 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Subtract SUB Byte Data Subtraction [Instruction format] SUB dst, src [Operation] dst, CY ← dst – src [Operand] Mnemonic Operand(dst,src) Mnemonic Operand(dst,src) SUB A, #byte SUB A, !addr16 saddr, #byte A, [HL] A, r Note A, [HL+by...

Page 58 - Subtract with Carry; Subtraction of Byte Data with Carry; the result is stored in the A register.

58 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Subtract with Carry SUBC Subtraction of Byte Data with Carry [Instruction format] SUBC dst, src [Operation] dst, CY ← dst – src – CY [Operand] Mnemonic Operand(dst,src) Mnemonic Operand(dst,src) SUBC A, #byte SUBC A, !addr16 saddr,...

Page 59 - And; Logical Product of Byte Data; result is stored at FEBAH.

59 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM And AND Logical Product of Byte Data [Instruction format] AND dst, src [Operation] dst ← dst ∧ src [Operand] Mnemonic Operand(dst,src) Mnemonic Operand(dst,src) AND A, #byte AND A, !addr16 saddr, #byte A, [HL] A, r Note A, [HL+byte...

Page 60 - Or; Logical Sum of Byte Data; OR

60 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Or OR Logical Sum of Byte Data [Instruction format] OR dst, src [Operation] dst ← dst ∨ src [Operand] Mnemonic Operand(dst,src) Mnemonic Operand(dst,src) OR A, #byte OR A, !addr16 saddr, #byte A, [HL] A, r Note A, [HL+byte] r, A A,...

Page 61 - Exclusive Or; Exclusive Logical Sum of Byte Data

61 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Exclusive Or XOR Exclusive Logical Sum of Byte Data [Instruction format] XOR dst, src [Operation] dst ← dst ∨ src [Operand] Mnemonic Operand(dst,src) Mnemonic Operand(dst,src) XOR A, #byte XOR A, !addr16 saddr, #byte A, [HL] A, r N...

Page 62 - Compare; Byte Data Comparison; specified by the 1st operand.

62 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Compare CMP Byte Data Comparison [Instruction format] CMP dst, src [Operation] dst – src [Operand] Mnemonic Operand(dst,src) Mnemonic Operand(dst,src) CMP A, #byte CMP A, !addr16 saddr, #byte A, [HL] A, r Note A, [HL+byte] r, A A, ...

Page 63 - The following are 16-bit operation instructions.

63 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM 5.4 16-Bit Operation Instructions The following are 16-bit operation instructions. ADDW ... 64 SUBW ... 65 CMPW ... 66

Page 64 - Add Word; Word Data Addition; ADDW; As a result of addition, the AC flag becomes undefined.

64 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Add Word ADDW Word Data Addition [Instruction format] ADDW dst, src [Operation] dst, CY ← dst + src [Operand] Mnemonic Operand(dst,src) ADDW AX, #word [Flag] Z AC CY × × × [Description] • The destination operand (dst) specified by ...

Page 65 - Subtract Word; Word Data Subtraction; SUBW; As a result of subtraction, the AC flag becomes undefined.

65 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Subtract Word SUBW Word Data Subtraction [Instruction format] SUBW dst, src [Operation] dst, CY ← dst – src [Operand] Mnemonic Operand(dst,src) SUBW AX, #word [Flag] Z AC CY × × × [Description] • The source operand (src) specified ...

Page 66 - Compare Word; Word Data Comparison; CMPW

66 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Compare Word CMPW Word Data Comparison [Instruction format] CMPW dst, src [Operation] dst – src [Operand] Mnemonic Operand(dst,src) CMPW AX, #word [Flag] Z AC CY × × × [Description] • The source operand (src) specified by the 2nd o...

Page 67 - The following are multiply/divide instructions.

67 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM 5.5 Multiply/Divide Instructions The following are multiply/divide instructions. MULU ... 68 DIVUW ... 69

Page 68 - Multiply Unsigned; Unsigned Multiplication of Data; MULU; is stored in the AX register.

68 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Multiply Unsigned MULU Unsigned Multiplication of Data [Instruction format] MULU src [Operation] AX ← A × src [Operand] Mnemonic Operand(src) MULU X [Flag] Z AC CY [Description] • The A register contents and the source operand (src...

Page 69 - Divide Unsigned Word; Unsigned Division of Word Data; DIVUW; are stored in the AX register and the C register, respectively.

69 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Divide Unsigned Word DIVUW Unsigned Division of Word Data [Instruction format] DIVUW dst [Operation] AX (quotient), dst (remainder) ← AX ÷ dst [Operand] Mnemonic Operand(dst) DIVUW C [Flag] Z AC CY [Description] • The AX register c...

Page 70 - The following are increment/decrement instructions.

70 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM 5.6 Increment/Decrement Instructions The following are increment/decrement instructions. INC ... 71 DEC ... 72 INCW ... 73 DECW ... 74

Page 71 - Increment; Byte Data Increment; INC; The destination operand (dst) contents are incremented by only one.

71 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Increment INC Byte Data Increment [Instruction format] INC dst [Operation] dst ← dst + 1 [Operand] Mnemonic Operand(dst) INC r saddr [Flag] Z AC CY × × [Description] • The destination operand (dst) contents are incremented by only ...

Page 72 - Decrement; Byte Data Decrement; DEC; The destination operand (dst) contents are decremented by only one.

72 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Decrement DEC Byte Data Decrement [Instruction format] DEC dst [Operation] dst ← dst – 1 [Operand] Mnemonic Operand(dst) DEC r saddr [Flag] Z AC CY × × [Description] • The destination operand (dst) contents are decremented by only ...

Page 73 - Increment Word; Word Data Increment; INCW

73 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Increment Word INCW Word Data Increment [Instruction format] INCW dst [Operation] dst ← dst + 1 [Operand] Mnemonic Operand(dst) INCW rp [Flag] Z AC CY [Description] • The destination operand (dst) contents are incremented by only o...

Page 74 - Decrement Word; Word Data Decrement; DECW

74 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Decrement Word DECW Word Data Decrement [Instruction format] DECW dst [Operation] dst ← dst – 1 [Operand] Mnemonic Operand (dst) DECW rp [Flag] Z AC CY [Description] • The destination operand (dst) contents are decremented by only ...

Page 75 - Rotate Instructions; The following are rotate instructions.

75 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM 5.7 Rotate Instructions The following are rotate instructions. ROR ... 76 ROL ... 77 RORC ... 78 ROLC ... 79 ROR4 ... 80 ROL4 ... 81

Page 76 - Rotate Right; Byte Data Rotation to the Right; ROR; The A register contents are rotated one bit to the right.

76 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Rotate Right ROR Byte Data Rotation to the Right [Instruction format] ROR dst, cnt [Operation] (CY, dst 7 ← dst 0 , dst m–1 ← dst m ) × one time [Operand] Mnemonic Operand(dst,cnt) ROR A, 1 [Flag] Z AC CY × [Description] • The dest...

Page 77 - Rotate Left; Byte Data Rotation to the Left; ROL; The A register contents are rotated to the left by one bit.

77 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Rotate Left ROL Byte Data Rotation to the Left [Instruction format] ROL dst, cnt [Operation] (CY, dst 0 ← dst 7 , dst m+1 ← dst m ) × one time [Operand] Mnemonic Operand(dst,cnt) ROL A, 1 [Flag] Z AC CY × [Description] • The destin...

Page 78 - Rotate Right with Carry; Byte Data Rotation to the Right with Carry; RORC

78 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Rotate Right with Carry RORC Byte Data Rotation to the Right with Carry [Instruction format] RORC dst, cnt [Operation] (CY ← dst 0 , dst 7 ← CY, dst m–1 ← dst m ) × one time [Operand] Mnemonic Operand(dst,cnt) RORC A, 1 [Flag] Z AC...

Page 79 - Rotate Left with Carry; Byte Data Rotation to the Left with Carry; ROLC

79 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Rotate Left with Carry ROLC Byte Data Rotation to the Left with Carry [Instruction format] ROLC dst, cnt [Operation] (CY ← dst 7 , dst 0 ← CY, dst m+1 ← dst m ) × one time [Operand] Mnemonic Operand(dst,cnt) ROLC A, 1 [Flag] Z AC C...

Page 80 - Rotate Right Digit; The higher 4 bits of the A register remain unchanged.

80 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Rotate Right Digit ROR4 Digit Rotation to the Right [Instruction format] ROR4 dst [Operation] A 3-0 ← (dst) 3-0 , (dst) 7-4 ← A 3-0 , (dst) 3-0 ← (dst) 7-4 [Operand] Mnemonic Operand(dst) ROR4 [HL] Note Note Specify an area other t...

Page 81 - Rotate Left Digit

81 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Rotate Left Digit ROL4 Digit Rotation to the Left [Instruction format] ROL4 dst [Operation] A 3-0 ← (dst) 7-4 , (dst) 3-0 ← A 3-0 , (dst) 7-4 ← (dst) 3-0 [Operand] Mnemonic Operand(dst) ROL4 [HL] Note Note Specify an area other tha...

Page 82 - BCD Adjust Instructions; The following are BCD adjust instructions.

82 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM 5.8 BCD Adjust Instructions The following are BCD adjust instructions. ADJBA ... 83 ADJBS ... 84

Page 83 - Decimal Adjust Register for Addition; ADJBA; Decimal Adjustment of Addition Result; None

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 83 User's Manual U12326EJ4V0UM Decimal Adjust Register for Addition ADJBA Decimal Adjustment of Addition Result [Instruction format] ADJBA [Operation] Decimal Adjust Accumulator for Addition [Operand] None [Flag] Z AC CY × × × [Description] • The A register, CY ...

Page 84 - Decimal Adjust Register for Subtraction; ADJBS; Decimal Adjustment of Subtraction Result; See the table below for the adjustment method.

84 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Decimal Adjust Register for Subtraction ADJBS Decimal Adjustment of Subtraction Result [Instruction format] ADJBS [Operation] Decimal Adjust Accumulator for Subtraction [Operand] None [Flag] Z AC CY × × × [Description] • The A regi...

Page 85 - Bit Manipulation Instructions; The following are bit manipulation instructions.

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 85 User's Manual U12326EJ4V0UM 5.9 Bit Manipulation Instructions The following are bit manipulation instructions. MOV1 ... 86 AND1 ... 87 OR1 ... 88 XOR1 ... 89 SET1 ... 90 CLR1 ... 91 NOT1 ... 92

Page 86 - Move Single Bit; In all other cases

86 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Move Single Bit MOV1 1 Bit Data Transfer [Instruction format] MOV1 dst, src [Operation] dst ← src [Operand] Mnemonic Operand(dst,src) Mnemonic Operand(dst,src) MOV1 CY, saddr.bit MOV1 saddr.bit, CY CY, sfr.bit sfr.bit, CY CY, A.bit...

Page 87 - And Single Bit

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 87 User's Manual U12326EJ4V0UM And Single Bit AND1 1 Bit Data Logical Product [Instruction format] AND1 dst, src [Operation] dst ← dst ∧ src [Operand] Mnemonic Operand(dst,src) AND1 CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit [Flag] Z AC CY × [D...

Page 88 - Or Single Bit

88 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Or Single Bit OR1 1 Bit Data Logical Sum [Instruction format] OR1 dst, src [Operation] dst ← dst ∨ src [Operand] Mnemonic Operand(dst,src) OR1 CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit [Flag] Z AC CY × [Descripti...

Page 89 - Exclusive Or Single Bit; is stored in the CY flag.

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 89 User's Manual U12326EJ4V0UM Exclusive Or Single Bit XOR1 1 Bit Data Exclusive Logical Sum [Instruction format] XOR1 dst, src [Operation] dst ← dst ∨ src [Operand] Mnemonic Operand(dst,src) XOR1 CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit [Fla...

Page 90 - Bit Data Set

90 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Set Single Bit (Carry Flag) SET1 1 Bit Data Set [Instruction format] SET1 dst [Operation] dst ← 1 [Operand] Mnemonic Operand(dst) SET1 saddr.bit sfr.bit A.bit PSW.bit [HL].bit CY [Flag] dst = PSW.bit dst = CY In all other cases Z A...

Page 91 - Bit Data Clear

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 91 User's Manual U12326EJ4V0UM Clear Single Bit (Carry Flag) CLR1 1 Bit Data Clear [Instruction format] CLR1 dst [Operation] dst ← 0 [Operand] Mnemonic Operand(dst) CLR1 saddr.bit sfr.bit A.bit PSW.bit [HL].bit CY [Flag] dst = PSW.bit dst = CY In all other cases...

Page 92 - Bit Data Logical Negation; The CY flag is inverted.

92 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Not Single Bit (Carry Flag) NOT1 1 Bit Data Logical Negation [Instruction format] NOT1 dst [Operation] dst ← dst [Operand] Mnemonic Operand(dst) NOT1 CY [Flag] Z AC CY × [Description] • The CY flag is inverted. [Description example...

Page 93 - Call Return Instructions; The following are call return instructions.

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 93 User's Manual U12326EJ4V0UM 5.10 Call Return Instructions The following are call return instructions. CALL ... 94 CALLF ... 95 CALLT ... 96 BRK ... 97 RET ... 98 RETI ... 99 RETB ... 100

Page 94 - Call; CALL target; CALL

94 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Call CALL Subroutine Call (16 Bit Direct) [Instruction format] CALL target [Operation] (SP–1) ← (PC+3) H , (SP–2) ← (PC+3) L , SP ← SP–2, PC ← target [Operand] Mnemonic Operand(target) CALL !addr16 [Flag] Z AC CY [Description] • Th...

Page 95 - CALLF; Subroutine call to 0C2AH

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 95 User's Manual U12326EJ4V0UM Call Flag CALLF Subroutine Call (11 Bit Direct Specification) [Instruction format] CALLF Target [Operation] (SP–1) ← (PC+2) H , (SP–2) ← (PC+2) L , SP ← SP–2, PC ← target [Operand] Mnemonic Operand(target) CALLF !addr11 [Flag] Z AC...

Page 96 - Call Table; Subroutine Call (Refer to the Call Table); CALLT; This is a subroutine call for call table reference.

96 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Call Table CALLT Subroutine Call (Refer to the Call Table) [Instruction format] CALLT [addr5] [Operation] (SP–1) ← (PC+1) H , (SP–2) ← (PC+1) L , SP ← SP–2, PC H ← (00000000, addr5+1) PC L ← (00000000, addr5) [Operand] Mnemonic Ope...

Page 97 - BRK; This is a software interrupt instruction.

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 97 User's Manual U12326EJ4V0UM Break BRK Software Vectored Interrupt [Instruction format] BRK [Operation] (SP–1) ← PSW, (SP–2) ← (PC+1) H , (SP–3) ← (PC+1) L , IE ← 0, SP ← SP–3, PC H ← (3FH), PC L ← (3EH) [Operand] None [Flag] Z AC CY [Description] • This is a ...

Page 98 - RET

98 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Return RET Return from Subroutine [Instruction format] RET [Operation] PC L ← (SP), PC H ← (SP+1), SP ← SP+2 [Operand] None [Flag] Z AC CY [Description] • This is a return instruction from the subroutine call made with the CALL, CA...

Page 99 - RETI; This is a return instruction from the vectored interrupt.

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 99 User's Manual U12326EJ4V0UM Return from Interrupt RETI Return from Hardware Vectored Interrupt [Instruction format] RETI [Operation] PC L ← (SP), PC H ← (SP+1), PSW ← (SP+2), SP ← SP+3, NMIS ← 0 [Operand] None [Flag] Z AC CY R R R [Description] • This is a re...

Page 100 - RETB

100 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Return from Break RETB Return from Software Vectored Interrupt [Instruction format] RETB [Operation] PC L ← (SP), PC H ← (SP+1), PSW ← (SP+2), SP ← SP+3 [Operand] None [Flag] Z AC CY R R R [Description] • This is a return instruct...

Page 101 - Stack Manipulation Instructions; The following are stack manipulation instructions.

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 101 User's Manual U12326EJ4V0UM 5.11 Stack Manipulation Instructions The following are stack manipulation instructions. PUSH ... 102 POP ... 103 MOVW SP, src ... 104 MOVW AX, SP ... 104

Page 102 - PUSH; AX register contents are saved to the stack.

102 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Push PUSH Push [Instruction format] PUSH src [Operation] When src = rp When src = PSW (SP–1) ← src H , (SP–1) ← src (SP–2) ← src L , SP ← SP–1 SP ← SP–2 [Operand] Mnemonic Operand(src) PUSH PSW rp [Flag] Z AC CY [Description] • Th...

Page 103 - POP

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 103 User's Manual U12326EJ4V0UM Pop POP Pop [Instruction format] POP dst [Operation] When dst = rp When dst = PSW dst L ← (SP), dst ← (SP) dst H ← (SP+1), SP ← SP+1 SP ← SP+2 [Operand] Mnemonic Operand(dst) POP PSW rp [Flag] dst =rp PSW Z AC CY Z AC CY R R R [De...

Page 104 - This is an instruction to manipulate the stack pointer contents.

104 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM MOVW SP, src Move Word MOVW AX, SP Word Data Transfer with Stack Pointer [Instruction format] MOVW dst, src [Operation] dst ← src [Operand] Mnemonic Operand(dst,src) MOVW SP, #word SP, AX AX, SP [Flag] Z AC CY [Description] • This...

Page 105 - Unconditional Branch Instruction; The unconditional branch instruction is shown below.

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 105 User's Manual U12326EJ4V0UM 5.12 Unconditional Branch Instruction The unconditional branch instruction is shown below. BR ... 106

Page 106 - Branch; Unconditional Branch; BR; This is an instruction to branch unconditionally.

106 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Branch BR Unconditional Branch [Instruction format] BR target [Operation] PC ← target [Operand] Mnemonic Operand(target) BR !addr16 AX $addr16 [Flag] Z AC CY [Description] • This is an instruction to branch unconditionally. • The ...

Page 107 - Conditional Branch Instructions; Conditional branch instructions are shown below.

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 107 User's Manual U12326EJ4V0UM 5.13 Conditional Branch Instructions Conditional branch instructions are shown below. BC ... 108 BNC ... 109 BZ ... 110 BNZ ... 111 BT ... 112 BF ... 113 BTCLR ... 114 DBNZ ... 115

Page 108 - Branch if Carry; BC; When CY = 1, data is branched to the address specified by the operand.

108 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Branch if Carry BC Conditional Branch with Carry Flag (CY = 1) [Instruction format] BC $addr16 [Operation] PC ← PC+2+jdisp8 if CY = 1 [Operand] Mnemonic Operand($addr16) BC $addr16 [Flag] Z AC CY [Description] • When CY = 1, data ...

Page 109 - Branch if Not Carry; BNC; When CY = 0, data is branched to the address specified by the operand.

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 109 User's Manual U12326EJ4V0UM Branch if Not Carry BNC Conditional Branch with Carry Flag (CY = 0) [Instruction format] BNC $addr16 [Operation] PC ← PC+2+jdisp8 if CY = 0 [Operand] Mnemonic Operand($addr16) BNC $addr16 [Flag] Z AC CY [Description] • When CY = 0...

Page 110 - Branch if Zero; BZ; When Z = 1, data is branched to the address specified by the operand.; DEC B

110 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Branch if Zero BZ Conditional Branch with Zero Flag (Z = 1) [Instruction format] BZ $addr16 [Operation] PC ← PC+2+jdisp8 if Z = 1 [Operand] Mnemonic Operand($addr16) BZ $addr16 [Flag] Z AC CY [Description] • When Z = 1, data is br...

Page 111 - Branch if Not Zero; BNZ; When Z = 0, data is branched to the address specified by the operand.

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 111 User's Manual U12326EJ4V0UM Branch if Not Zero BNZ Conditional Branch with Zero Flag (Z = 0) [Instruction format] BNZ $addr16 [Operation] PC ← PC+2+jdisp8 if Z = 0 [Operand] Mnemonic Operand($addr16) BNZ $addr16 [Flag] Z AC CY [Description] • When Z = 0, dat...

Page 112 - Branch if True; BT; instruction is executed.

112 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Branch if True BT Conditional Branch by Bit Test (Byte Data Bit = 1) [Instruction format] BT bit, $addr16 [Operation] PC ← PC+b+jdisp8 if bit = 1 [Operand] Mnemonic Operand(bit,$addr16) b(Number of bytes) BT saddr.bit, $addr16 3 s...

Page 113 - Branch if False; BF

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 113 User's Manual U12326EJ4V0UM Branch if False BF Conditional Branch by Bit Test (Byte Data Bit = 0) [Instruction format] BF bit, $addr16 [Operation] PC ← PC+b+jdisp8 if bit = 0 [Operand] Mnemonic Operand(bit,$addr16) b(Number of bytes) BF saddr.bit, $addr16 4 ...

Page 114 - Branch if True and Clear; Conditional Branch and Clear by Bit Test (Byte Data Bit = 1); BTCLR

114 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Branch if True and Clear BTCLR Conditional Branch and Clear by Bit Test (Byte Data Bit = 1) [Instruction format] BTCLR bit, $addr16 [Operation] PC ← PC+b+jdisp8 if bit = 1, then bit ← 0 [Operand] Mnemonic Operand(bit,$addr16) b(Nu...

Page 115 - Decrement and Branch if Not Zero; Conditional Loop (R1; DBNZ; subtraction result is stored in the destination operand (dst).

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 115 User's Manual U12326EJ4V0UM Decrement and Branch if Not Zero DBNZ Conditional Loop (R1 ≠ 0) [Instruction format] DBNZ dst, $addr16 [Operation] dst ← dst–1, then PC ← PC+b+jdisp16 if dst R1 ≠ 0 [Operand] Mnemonic Operand(dst,$addr16) b(Number of bytes) DBNZ B...

Page 116 - CPU Control Instructions; The following are CPU control instructions.

116 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM 5.14 CPU Control Instructions The following are CPU control instructions. SEL RBn ... 117 NOP ... 118 EI ... 119 DI ... 120 HALT ... 121 STOP ... 122

Page 117 - Select Register Bank; SEL RBn; Register Bank Selection; SEL; RBn ranges from RB0 to RB3.

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 117 User's Manual U12326EJ4V0UM Select Register Bank SEL RBn Register Bank Selection [Instruction format] SEL RBn [Operation] RBS0, RBS1 ← n; (n = 0-3) [Operand] Mnemonic Operand(RBn) SEL RBn [Flag] Z AC CY [Description] • The register bank specified by the oper...

Page 118 - NOP; No Operation; Only the time is consumed without processing.

118 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM No Operation NOP No Operation [Instruction format] NOP [Operation] no operation [Operand] None [Flag] Z AC CY [Description] • Only the time is consumed without processing.

Page 119 - Enable Interrupt; EI; Interrupt Enabled; “Interrupt Functions”; in the user’s manual of each product.

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 119 User's Manual U12326EJ4V0UM Enable Interrupt EI Interrupt Enabled [Instruction format] EI [Operation] IE ← 1 [Operand] None [Flag] Z AC CY [Description] • The maskable interrupt acknowledgeable status is set (by setting the interrupt enable flag (IE) to (1))...

Page 120 - Disable Interrupt; DI; Interrupt Disabled; For details of interrupt servicing, refer to

120 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Disable Interrupt DI Interrupt Disabled [Instruction format] DI [Operation] IE ← 0 [Operand] None [Flag] Z AC CY [Description] • Maskable interrupt acknowledgment by vectored interrupt is disabled (with the interrupt enable flag (...

Page 121 - Halt; HALT; HALT Mode Set

CHAPTER 5 EXPLANATION OF INSTRUCTIONS 121 User's Manual U12326EJ4V0UM Halt HALT HALT Mode Set [Instruction format] HALT [Operation] Set HALT Mode [Operand] None [Flag] Z AC CY [Description] • This instruction is used to set the HALT mode to stop the CPU operation clock. The total power consumption o...

Page 122 - Stop; STOP; Stop Mode Set

122 CHAPTER 5 EXPLANATION OF INSTRUCTIONS User's Manual U12326EJ4V0UM Stop STOP Stop Mode Set [Instruction format] STOP [Operation] Set STOP Mode [Operand] None [Flag] Z AC CY [Description] • This instruction is used to set the STOP mode to stop the main system clock oscillator and to stop the whole...

Page 123 - APPENDIX A REVISION HISTORY; chapters of each edition in which the revision was applied.

123 User's Manual U12326EJ4V0UM APPENDIX A REVISION HISTORY The following table shows the revision history of the previous editions. The “Applied to:” column indicates the chapters of each edition in which the revision was applied. Edition Major Revision from Previous Edition Applied to: 2nd Additio...

Page 126 - APPENDIX C INSTRUCTION INDEX (MNEMONIC: IN ALPHABETICAL ORDER)

126 User's Manual U12326EJ4V0UM APPENDIX C INSTRUCTION INDEX (MNEMONIC: IN ALPHABETICAL ORDER) [A] ADD ... 55 ADDC ... 56 ADDW ... 64 ADJBA ... 83 ADJBS ... 84 AND ... 59 AND1 ... 87 [B] BC ... 108 BF ... 113 BNC ... 109 BNZ ... 111 BR ... 106 BRK ... 97 BT ... 112 BTCLR ... 114 BZ ... 110 [C] CALL ...

Page 127 - APPENDIX C INSTRUCTION INDEX (MNEMONIC: IN ALPHABETICAL ORDER)

127 User's Manual U12326EJ4V0UM [S] SEL RBn ... 117 SET1 ... 90 STOP ... 122 SUB ... 57 SUBC ... 58 SUBW ... 65 [X] XCH ... 50 XCHW ... 53 XOR ... 61 XOR1 ... 89 APPENDIX C INSTRUCTION INDEX (MNEMONIC: IN ALPHABETICAL ORDER)

Page 129 - Thank you for your kind support.; Document Rating; Facsimile

Although NEC has taken all possible stepsto ensure that the documentation suppliedto our customers is complete, bug freeand up-to-date, we readily accept thaterrors may occur. Despite all the care andp r e c a u t i o n s w e ' v e t a k e n , y o u m a yencounter problems in the documentation.Pleas...