NEC 78K/0 Series - Manual

NEC 78K/0 Series

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Table of Contents:

  • Page 3 – IEBus is a trademark of NEC Corporation.; NOTES FOR CMOS DEVICES; PRECAUTION AGAINST ESD FOR SEMICONDUCTORS; to be taken for PW boards with semiconductor devices on it.; HANDLING OF UNUSED INPUT PINS FOR CMOS; pin should be connected to V; or GND with a resistor, if it is considered to have a possibility of; STATUS BEFORE INITIALIZATION OF MOS DEVICES; having reset function.
  • Page 4 – s u p p o r t s y s t e m s a n d m e d i c a l e q u i p m e n t f o r l i f e s u p p o r t , e t c .
  • Page 5 – Regional Information; Device availability
  • Page 6 – Major Revisions in This Edition; Page; The mark shows major revised points.
  • Page 7 – INTRODUCTION
  • Page 8 – Related Documents; versions are not marked as such.; • Documents Common to 78K/0 Series; Note; Some subseries may not be covered.; latest version of each document for designing.
  • Page 11 – LIST OF FIGURES; LIST OF TABLES; Title
  • Page 12 – CHAPTER 1 MEMORY SPACE; ROM space, refer to the user’s manual of each product.; Vector Table Area; area, refer to the user’s manual of each product.; CALLT Instruction Table Area; The internal high-speed RAM can also be used as a stack memory.
  • Page 13 – CHAPTER 1 MEMORY SPACE; also be used as an ordinary RAM area.; External Memory Space; Register Area
  • Page 14 – status word and a stack pointer are the control registers.; Figure 2-1. Program Counter Configuration; RESET input sets the PSW to 02H.; Figure 2-2. Program Status Word Configuration
  • Page 15 – CHAPTER 2 REGISTERS; execution of the EI instruction.
  • Page 16 – RAM area can be set as the stack area.; Figure 2-4. Data to Be Saved to Stack Memory
  • Page 19 – Each manipulation bit unit can be specified as follows.
  • Page 20 – CHAPTER 5; +127 from the start address of the following instruction.
  • Page 21 – CHAPTER 3 ADDRESSING; CALLF !addr11 instruction is branched to the area of 0800H to 0FFFH.
  • Page 22 – memory table of 40H to 7FH.
  • Page 24 – Operand Address Addressing; during instruction execution.
  • Page 25 – MOV A, C When selecting the C register for r
  • Page 27 – manipulated with a small number of bytes and clocks.
  • Page 29 – register pair specification in instruction codes.
  • Page 31 – In the case of PUSH DE
  • Page 32 – CHAPTER 4 INSTRUCTION SET; Operand identifiers and description methods; Absolute address specification; Table 4-1. Operand Identifiers and Description Methods; FFD0H to FFDFH are not addressable.; Remark
  • Page 33 – CHAPTER 4 INSTRUCTION SET; Description of “flag operation” column
  • Page 34 – instruction clock cycle is 1 CPU clock cycle (f; Instructions listed by addressing type
  • Page 38 – Instruction Codes; Description of instruction code table
  • Page 39 – XCH
  • Page 41 – SUBC; AND
  • Page 42 – XOR; CMP
  • Page 46 – CHAPTER 5 EXPLANATION OF INSTRUCTIONS; including description of multiple operands.; CHAPTER 4 INSTRUCTION SET, respectively.
  • Page 47 – CHAPTER 5 EXPLANATION OF INSTRUCTIONS; DESCRIPTION EXAMPLE; Move; Byte Data Transfer; MOV; Conventions
  • Page 48 – The following instructions are 8-bit data transfer instructions.
  • Page 49 – All other operand
  • Page 50 – Exchange; Byte Data Exchange; The 1st and 2nd operand contents are exchanged.
  • Page 52 – Move Word; Word Data Transfer; MOVW; The HL register contents are transferred to the AX register.
  • Page 53 – Exchange Word; Word Data Exchange; XCHW
  • Page 54 – The following are 8-bit operation instructions.
  • Page 55 – Add; Byte Data Addition; ADD
  • Page 56 – Add with Carry; Addition of Byte Data with Carry; ADDC; CY flag are added and the result is stored in the A register.
  • Page 57 – Subtract; Byte Data Subtraction; SUB
  • Page 58 – Subtract with Carry; Subtraction of Byte Data with Carry; the result is stored in the A register.
  • Page 59 – And; Logical Product of Byte Data; result is stored at FEBAH.
  • Page 60 – Or; Logical Sum of Byte Data; OR
  • Page 61 – Exclusive Or; Exclusive Logical Sum of Byte Data
  • Page 62 – Compare; Byte Data Comparison; specified by the 1st operand.
  • Page 63 – The following are 16-bit operation instructions.
  • Page 64 – Add Word; Word Data Addition; ADDW; As a result of addition, the AC flag becomes undefined.
  • Page 65 – Subtract Word; Word Data Subtraction; SUBW; As a result of subtraction, the AC flag becomes undefined.
  • Page 66 – Compare Word; Word Data Comparison; CMPW
  • Page 67 – The following are multiply/divide instructions.
  • Page 68 – Multiply Unsigned; Unsigned Multiplication of Data; MULU; is stored in the AX register.
  • Page 69 – Divide Unsigned Word; Unsigned Division of Word Data; DIVUW; are stored in the AX register and the C register, respectively.
  • Page 70 – The following are increment/decrement instructions.
  • Page 71 – Increment; Byte Data Increment; INC; The destination operand (dst) contents are incremented by only one.
  • Page 72 – Decrement; Byte Data Decrement; DEC; The destination operand (dst) contents are decremented by only one.
  • Page 73 – Increment Word; Word Data Increment; INCW
  • Page 74 – Decrement Word; Word Data Decrement; DECW
  • Page 75 – Rotate Instructions; The following are rotate instructions.
  • Page 76 – Rotate Right; Byte Data Rotation to the Right; ROR; The A register contents are rotated one bit to the right.
  • Page 77 – Rotate Left; Byte Data Rotation to the Left; ROL; The A register contents are rotated to the left by one bit.
  • Page 78 – Rotate Right with Carry; Byte Data Rotation to the Right with Carry; RORC
  • Page 79 – Rotate Left with Carry; Byte Data Rotation to the Left with Carry; ROLC
  • Page 80 – Rotate Right Digit; The higher 4 bits of the A register remain unchanged.
  • Page 81 – Rotate Left Digit
  • Page 82 – BCD Adjust Instructions; The following are BCD adjust instructions.
  • Page 83 – Decimal Adjust Register for Addition; ADJBA; Decimal Adjustment of Addition Result; None
  • Page 84 – Decimal Adjust Register for Subtraction; ADJBS; Decimal Adjustment of Subtraction Result; See the table below for the adjustment method.
  • Page 85 – Bit Manipulation Instructions; The following are bit manipulation instructions.
  • Page 86 – Move Single Bit; In all other cases
  • Page 87 – And Single Bit
  • Page 88 – Or Single Bit
  • Page 89 – Exclusive Or Single Bit; is stored in the CY flag.
  • Page 90 – Bit Data Set
  • Page 91 – Bit Data Clear
  • Page 92 – Bit Data Logical Negation; The CY flag is inverted.
  • Page 93 – Call Return Instructions; The following are call return instructions.
  • Page 94 – Call; CALL target; CALL
  • Page 95 – CALLF; Subroutine call to 0C2AH
  • Page 96 – Call Table; Subroutine Call (Refer to the Call Table); CALLT; This is a subroutine call for call table reference.
  • Page 97 – BRK; This is a software interrupt instruction.
  • Page 98 – RET
  • Page 99 – RETI; This is a return instruction from the vectored interrupt.
  • Page 100 – RETB
  • Page 101 – Stack Manipulation Instructions; The following are stack manipulation instructions.
  • Page 102 – PUSH; AX register contents are saved to the stack.
  • Page 103 – POP
  • Page 104 – This is an instruction to manipulate the stack pointer contents.
  • Page 105 – Unconditional Branch Instruction; The unconditional branch instruction is shown below.
  • Page 106 – Branch; Unconditional Branch; BR; This is an instruction to branch unconditionally.
  • Page 107 – Conditional Branch Instructions; Conditional branch instructions are shown below.
  • Page 108 – Branch if Carry; BC; When CY = 1, data is branched to the address specified by the operand.
  • Page 109 – Branch if Not Carry; BNC; When CY = 0, data is branched to the address specified by the operand.
  • Page 110 – Branch if Zero; BZ; When Z = 1, data is branched to the address specified by the operand.; DEC B
  • Page 111 – Branch if Not Zero; BNZ; When Z = 0, data is branched to the address specified by the operand.
  • Page 112 – Branch if True; BT; instruction is executed.
  • Page 113 – Branch if False; BF
  • Page 114 – Branch if True and Clear; Conditional Branch and Clear by Bit Test (Byte Data Bit = 1); BTCLR
  • Page 115 – Decrement and Branch if Not Zero; Conditional Loop (R1; DBNZ; subtraction result is stored in the destination operand (dst).
  • Page 116 – CPU Control Instructions; The following are CPU control instructions.
  • Page 117 – Select Register Bank; SEL RBn; Register Bank Selection; SEL; RBn ranges from RB0 to RB3.
  • Page 118 – NOP; No Operation; Only the time is consumed without processing.
  • Page 119 – Enable Interrupt; EI; Interrupt Enabled; “Interrupt Functions”; in the user’s manual of each product.
  • Page 120 – Disable Interrupt; DI; Interrupt Disabled; For details of interrupt servicing, refer to
  • Page 121 – Halt; HALT; HALT Mode Set
  • Page 122 – Stop; STOP; Stop Mode Set
  • Page 123 – APPENDIX A REVISION HISTORY; chapters of each edition in which the revision was applied.
  • Page 126 – APPENDIX C INSTRUCTION INDEX (MNEMONIC: IN ALPHABETICAL ORDER)
  • Page 127 – APPENDIX C INSTRUCTION INDEX (MNEMONIC: IN ALPHABETICAL ORDER)
  • Page 129 – Thank you for your kind support.; Document Rating; Facsimile
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User’s Manual

Printed in Japan

©

78K/0 Series

Instructions

Document No.

U12326EJ4V0UM00 (4th edition)

Date Published October 2001 N CP(K)

1995

Common to 78K/0 Series

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Summary

Page 3 - IEBus is a trademark of NEC Corporation.; NOTES FOR CMOS DEVICES; PRECAUTION AGAINST ESD FOR SEMICONDUCTORS; to be taken for PW boards with semiconductor devices on it.; HANDLING OF UNUSED INPUT PINS FOR CMOS; pin should be connected to V; or GND with a resistor, if it is considered to have a possibility of; STATUS BEFORE INITIALIZATION OF MOS DEVICES; having reset function.

3 User's Manual U12326EJ4V0UM Caution: Purchase of NEC I 2 C components conveys a license under the Philips I 2 C Patent Rights to use these components in an I 2 C system, provided that the system conforms to the I 2 C Standard Specification as defined by Philips. IEBus is a trademark of NEC Corpora...

Page 4 - s u p p o r t s y s t e m s a n d m e d i c a l e q u i p m e n t f o r l i f e s u p p o r t , e t c .

4 User's Manual U12326EJ4V0UM The export of these products from Japan is regulated by the Japanese government. The export of some or all of theseproducts may be prohibited without governmental license. To export or re-export some or all of these products from ac o u n t r y o t h e r t h a n J a p a...

Page 5 - Regional Information; Device availability

5 User's Manual U12326EJ4V0UM Regional Information Some information contained in this document may vary from country to country. Before using any NECproduct in your application, pIease contact the NEC office in your country to obtain a list of authorizedrepresentatives and distributors. They will ve...

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