Page 5 - FCC/DOC Radio Frequency Interference Compliance; Federal Communications Commission
FCC/DOC Radio Frequency Interference Compliance This equipment generates and uses radio frequency energy and, if not installed and used in strict accordance with theinstructions in this manual, may cause interference to radio and television reception. This equipment has been testedand found to compl...
Page 6 - Contents; About This Manual; xiii
© National Instruments Corporation vii GPIB-1014 User Manual Contents About This Manual ............................................................................................................ xiii Organization of This Manual .........................................................................
Page 10 - Glossary
Contents © National Instruments Corporation xi GPIB-1014 User Manual Data Lines .......................................................................................................... E-2 Handshake Lines ................................................................................................
Page 11 - Tables; Multiline GPIB Commands Recognized by the
Contents GPIB-1014 User Manual xii © National Instruments Corporation Figure 6-3. Array Format for Linked Chaining Modes ...................................................... 6-21 Figure E-1. The GPIB Connector and Signal Assignments ................................................ E-4 Figure E-2. ...
Page 12 - Organization of This Manual; The GPIB-1014 User Manual is organized as follows:
© National Instruments Corporation xiii GPIB-1014 User Manual About This Manual The GPIB-1014 User Manual describes the mechanical and electrical aspects of the GPIB-1014,the data transfer features, and contains information concerning its operation and programming. Organization of This Manual The GP...
Page 13 - Conventions Used in This Manual; italic; Related Documentation; How to Interface a Microcomputer System to a GPIB, (& The NEC
About This Manual GPIB-1014 User Manual xiv © National Instruments Corporation • Appendix F, Mnemonics Key, contains a mnemonics key that defines the mnemonics(abbreviations) used throughout this manual for functions, remote messages, local messages,states, bits, registers, integrated circuits, syst...
Page 14 - Customer Communication
About This Manual © National Instruments Corporation xv GPIB-1014 User Manual • Motorola Semiconductor Technical Data MC68450 Advance Information Direct MemoryAccess Controller (DMAC) • Hitachi Microcomputer System HD68450 DMAC (Direct Memory Access Controller) Customer Communication National Instru...
Page 16 - Art not available in PDF version of document.
Introduction Chapter 1 GPIB-1014 User Manual 1-2 © National Instruments Corporation Figure 1-1 shows the GPIB-1014 interface board. Figure 1-1. GPIB-1014 Interface Board Art not available in PDF version of document.
Page 17 - What Your Kit Should Contain; Kit Component; Optional Equipment; Equipment
Chapter 1 Introduction © National Instruments Corporation 1-3 GPIB-1014 User Manual The GPIB-1014 interface kit includes hardware and programming examples to implement theGPIB functions. Optional cables are supplied for interconnection with other devices on theGPIB. What Your Kit Should Contain Your...
Page 18 - Unpacking; Follow these steps when unpacking your GPIB-1014.
Introduction Chapter 1 GPIB-1014 User Manual 1-4 © National Instruments Corporation Unpacking Follow these steps when unpacking your GPIB-1014. 1. Verify that the pieces contained in the package you received match the kit parts list given earlier in this chapter. Do not remove the board from its pla...
Page 19 - Electrical Characteristics; Driver Device; SYSCLK
© National Instruments Corporation 2-1 GPIB-1014 User Manual Chapter 2General Description This chapter contains the electrical specifications for the GPIB-1014, the data transfer features,and describes the characteristics of key interface board components. Electrical Characteristics All integrated c...
Page 20 - Data Transceivers; VMEbus Characteristics; VMEbus Slave-Addressing
General Description Chapter 2 GPIB-1014 User Manual 2-2 © National Instruments Corporation Table 2-1. GPIB-1014 Signals (continued) Driver Device Receiver Device Bus Signals Part Number Part Number BR0*-BR3* AS756 LS241 BBSY* AS756 LS240 IACKIN* – LS240 IACKOUT* F1241 – IRQ1*-IRQ7* 74145 – BERR* – F...
Page 21 - Address
Chapter 2 General Description © National Instruments Corporation 2-3 GPIB-1014 User Manual to generate its board select signal. It then decodes the lowest eight lines, A8 through A1, toaddress the following items:• The 68450 DMA Controller (DMAC) • The µ PD7210 GPIB Talker/Listener/Controller (TLC) ...
Page 22 - Ad
General Description Chapter 2 GPIB-1014 User Manual 2-4 © National Instruments Corporation Table 2-3. 68450 Internal DMA Registers Ad dress (Base + Hex Offset) Mode Register Channel Size 0A R/W Memory Transfer Counter (MTCR0) 0 16 bits 0C R/W Memory Address Register (MAR0) 0 32 bits 29 R/W Memory Fu...
Page 23 - VMEbus Master-Direct Memory Access
Chapter 2 General Description © National Instruments Corporation 2-5 GPIB-1014 User Manual Table 2-3. 68450 Internal DMA Registers (continued) Address (Base + Hex Offset) Mode Register Channel Size 85 R/W Operation Control (OCR2) 2 8 bits 86 R/W Sequence Control (SCR2) 2 8 bits 87 R/W Channel Contro...
Page 24 - Interrupter
General Description Chapter 2 GPIB-1014 User Manual 2-6 © National Instruments Corporation Memory addresses generated by the GPIB-1014 are 24 bits wide and the VMEbus AddressModifier Lines (AM5 through AM0) are fully programmable using function code registerslocated in the 68450 and three hardware j...
Page 25 - VMEbus Modules Not Provided; Diagnostic Aids; Data Transfer Features
Chapter 2 General Description © National Instruments Corporation 2-7 GPIB-1014 User Manual Data Transfer Bus (DTB) Requester The GPIB-1014 arbitrates for the DTB before each DMA transfer. The board is designed for youto select, through software, one of four VMEbus request lines (BR0* through BR3*) u...
Page 26 - Programmed I/O Transfers; GPIB-1014 Functional Description
General Description Chapter 2 GPIB-1014 User Manual 2-8 © National Instruments Corporation • GPIB Listener response time (DAV* low to NDAC* high) • GPIB Talker response time (NRFD* high to DAV* low) • GPIB-1014 transfer mode: Cycle Steal with hold, programmable timeout • T1 timing: high-speed Transf...
Page 33 - Compliance Notation
Chapter 2 General Description © National Instruments Corporation 2-15 GPIB-1014 User Manual • Receive control • Pass control • Conduct a Parallel Poll • Take control synchronously or asynchronously Table 2-6 contains the GPIB-1014 IEEE 1014 compliance levels. Table 2-6. GPIB-1014 IEEE 1014 Interrupt...
Page 34 - Configuration
© National Instruments Corporation 3-1 GPIB-1014 User Manual Chapter 3Configuration and Installation This chapter describes the steps needed to configure and install the GPIB-1014 hardware. Configuration Before installing the GPIB-1014 in the VMEbus backplane, the following options must beconfigured...
Page 36 - Access Mode
Chapter 3 Configuration and Installation © National Instruments Corporation 3-3 GPIB-1014 User Manual Access Mode The GPIB-1014 can be configured to respond to Supervisor (privileged) or User (non-privileged)access. Hardware jumper W2 is used to select the access mode that is automatically in effect...
Page 37 - Set Base Address Using Jumper Block W1; Set Base Address Using Compare Address Lines
Configuration and Installation Chapter 3 GPIB-1014 User Manual 3-4 © National Instruments Corporation Set Base Address Using Jumper Block W1 Move the jumper to the side labeled 1 to select a logical one for the corresponding address bit, orto the side labeled 0 to select a logical zero. Figure 3-3 s...
Page 38 - DMA Address Modifier Code Output
Chapter 3 Configuration and Installation © National Instruments Corporation 3-5 GPIB-1014 User Manual DMA Address Modifier Code Output During a DMA cycle, the GPIB-1014 sends out a 6-bit Address Modifier (AM) code to theVMEbus lines AM5 through AM0. The correct code is obtained by both programming t...
Page 40 - Other Configuration Parameters; Enabling the Release On Request (ROR) feature; Installation; Verification of System Compatibility
Chapter 3 Configuration and Installation © National Instruments Corporation 3-7 GPIB-1014 User Manual For example, to produce an AM code of 17 hex (a binary value of 010111), complete thefollowing steps: 1. Set jumper W3 to 0. 2. Set jumper W4 to 0. 3. Set jumper W5 to AM(1). 4. Write the pattern 00...
Page 43 - Cabling; A Front Panel Plug-In Connector; Verification Testing
Configuration and Installation Chapter 3 GPIB-1014 User Manual 3-10 © National Instruments Corporation Cabling Two options are available for GPIB I/O from the GPIB-1014: • A Front Panel Plug-In Connector • A VMEbus P2 Connector The Model GPIB-1014-1 interface board has a standard 24-pin IEEE 488 con...
Page 44 - Register Map; Register Name
© National Instruments Corporation 4-1 GPIB-1014 User Manual Chapter 4Register Bit Descriptions This chapter contains a description of the register map, a list of interface registers, and adescription of the DMA registers. Register Map The register map for the GPIB-1014 is shown in Table 4-1. This t...
Page 45 - Register Sizes
Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-2 © National Instruments Corporation Table 4-1. GPIB-1014 Register Map (continued) Register Name Address (Hex) Type Size DMA Register Group: Address Registers Memory Address Register Base address + 0C Read/Write 32-bit Base Address Register...
Page 46 - Register Description Format
Chapter 4 Register Bit Descriptions © National Instruments Corporation 4-3 GPIB-1014 User Manual Register Description Format The remainder of this chapter discusses each of the GPIB-1014 registers in the order shown inTable 4-1. Each register group is introduced, followed by a detailed bit descripti...
Page 47 - Interface Registers
Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-4 © National Instruments Corporation Interface Registers Twenty-one GPIB Interface registers, eight of which are readable and 13 of which are writable,are located within the NEC µ PD7210 Talker/Listener/Controller (TLC) integrated circuit. ...
Page 49 - Figure 4-2. Writing to the Hidden Registers
Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-6 © National Instruments Corporation Control Code Command Code When CNT2-CNT0 is: ICR is loaded with: PPR is loaded with: AUXRA is loaded with: AUXRB is loaded with: AUXRE is loaded with: W AUXMR CNT2 CNT1 CNT0 COM4 COM3 COM2 COM1 COM0 0 CL...
Page 50 - Read Only, Internal to TLC; Bit; Data In Bits 7 through 0
Chapter 4 Register Bit Descriptions © National Instruments Corporation 4-7 GPIB-1014 User Manual Data In Register (DIR) VMEbus Address: Base Address + 111 (hex) Attributes: Read Only, Internal to TLC 7 6 5 4 3 2 1 0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 R The Data In Register (DIR) is used to move data fr...
Page 51 - Write Only, Internal to TLC; Command/Data Out Bits 7 through 0
Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-8 © National Instruments Corporation Command/Data Out Register (CDOR) VMEbus Address: Base Address + 111 (hex) Attributes: Write Only, Internal to TLC 7 6 5 4 3 2 1 0 CDO7 CDO6 CDO5 CDO4 CDO3 CDO2 CDO1 CDO0 The Command/Data Out Register (CD...
Page 62 - Power On Reset
Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-18 © National Instruments Corporation Bit Mnemonic Description Notes TA: Talker Active bit, ADSR[1]r LA: Listener Active bit, ADSR[2]r CIC: Controller-In-Charge bit, ADSR[7]r MJMN: Major/Minor bit, ADSR[0]r lon: Listen Only bit, ADMR[6]w to...
Page 65 - TPAS; Note: Only one Talker and Listener can be active at any one time
Bit Mnemonic Description 3r TPAS Talker Primary Addressed State BitTPAS is used when the TLC is configured for extended GPIBaddressing, and, when set, indicates that the TLC has received itsprimary GPIB talk address. In extended mode addressing (mode 3addressing), TPAS=1 indicates that the secondary...
Page 70 - Hex Number
Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-26 © National Instruments Corporation Table 4-3. Multiline GPIB Commands Recognized by the µ PD7210 (continued) Hex Number Message Description 15 PPU Parallel Poll Unconfigure 18 SPE Serial Poll Enable 19 SPD Serial Poll Disable 20-3E MLA M...
Page 71 - Table 4-4 shows the control and command codes used.; Control Code Bits 2 through 0
Auxiliary Mode Register (AUXMR) VMEbus Address: Base Address + 11B (hex) Attributes: Write Only, Internal to TLCPermits Access to Hidden Registers W 7 6 5 4 3 2 1 0 CNT1 CNT0 CNT2 COM4 COM3 COM2 COM1 COM0 The Auxiliary Mode Register (AUXMR) is used to issue auxiliary commands. It is also used toprog...
Page 72 - Hex
Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-28 © National Instruments Corporation Table 4-4. Auxiliary Command Summary Function Code*(COM4-COM0) Hex 4 3 2 1 0 Code** Auxiliary Command 0 0 0 0 0 00 Immediate Execute pon 0 0 0 1 0 02 Chip Reset 0 0 0 1 1 03 Finish Handshake 0 0 1 0 0 0...
Page 73 - Description
Table 4-5 shows the functions that are executed when the AUXMR Control Code (CNT2through CNT0) is loaded with 000 (binary) and the Command Code (COM4 through COM0) isloaded. Table 4-5. Auxiliary Commands: Detail Description Command Code(COM4-COM0) 4 3 2 1 0 Description 0 0 0 0 0 Immediate Execute Po...
Page 74 - Trigger
Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-30 © National Instruments Corporation Table 4-5. Auxiliary Commands: Detail Description (continued) Command Code(COM4-COM0) 4 3 2 1 0 Description 0 0 0 1 1 Finish Handshake (FH) The Finish Handshake command finishes a GPIB Handshake thatwas...
Page 76 - In continuous mode, the local message rdy is issued when the
Register Bit Descriptions Chapter 4 GPIB-1014 User Manual 4-32 © National Instruments Corporation Table 4-5. Auxiliary Commands: Detail Description (continued) Command Code(COM4-COM0) 4 3 2 1 0 Description 1 1 0 1 1 In continuous mode, the local message rdy is issued when the (continued) Acceptor No...
Page 77 - Hidden Registers
Chapter 4 Register Descriptions © National Instruments Corporation 4-33 GPIB-1014 User Manual Hidden Registers The hidden registers are loaded through the Auxiliary Mode Register (AUXMR). AUXMR[7-5]is loaded with the hidden register number, and AUXMR[4-0] is loaded with the data to betransferred to ...
Page 78 - Reserved Bit
Register Descriptions Chapter 4 GPIB-1014 User Manual 4-34 © National Instruments Corporation Internal Counter Register (ICR) VMEbus Address: Base Address + 11B (hex) AUXMR Control Code: 001 (Binary, Bits 7 - 5) Attributes: Write Only, Internal to TLCAccessed through AUXMR 4 3 2 1 0 W 0 CLK3 CLK2 CL...
Page 79 - Unconfigure Bit
Chapter 4 Register Descriptions © National Instruments Corporation 4-35 GPIB-1014 User Manual Parallel Poll Register (PPR) VMEbus Address: Base Address + 11B (hex) AUXMR Control Code: 011 (Binary, Bits 7 - 5) Attributes: Write Only, Internal to TLCAccessed through AUXMR 4 3 2 1 0 W U S P3 P2 P1 This...
Page 80 - Parallel Poll Response Bits 3 through 1; Result; Unconfigures PPR
Register Descriptions Chapter 4 GPIB-1014 User Manual 4-36 © National Instruments Corporation Bit Mnemonic Description 3w S Status Bit Polarity (Sense) Bit The S bit is used to indicate the polarity (or sense) of the TLC local istmessage. If S=1, the status is in phase, meaning that if, during aPara...
Page 83 - ISS
Chapter 4 Register Descriptions © National Instruments Corporation 4-39 GPIB-1014 User Manual Auxiliary Register B (AUXRB) VMEbus Address: Base Address + 11B (hex) AUXMR Control Code: 101 (Binary, Bits 7 - 5) Attributes: Write Only, Internal to TLCAccessed through AUXMR 4 3 2 1 0 W ISS INV TRI SPEOI...
Page 84 - TRI
Register Descriptions Chapter 4 GPIB-1014 User Manual 4-40 © National Instruments Corporation Bit Mnemonic Description 2w TRI Three-State Timing Bit The TRI bit determines the TLC GPIB Source Handshake Timing, T1.TRI can be set to enable high-speed data transfers (T1 ≥ 500 nsec) when tri-state GPIB ...
Page 86 - Reads as a zero or one.
Register Descriptions Chapter 4 GPIB-1014 User Manual 4-42 © National Instruments Corporation Address Register 0 (ADR0) VMEbus Address: Base Address + 11D (hex) Attributes: Read Only, Internal to TLC 7 6 5 4 3 2 1 0 X DT0 DL0 AD5-0 AD4-0 AD3-0 AD2-0 AD1-0 R Address Register 0 (ADR0) reflects the int...
Page 89 - Base Address + 11F hex; End of String Bits 7 through 0
Chapter 4 Register Descriptions © National Instruments Corporation 4-45 GPIB-1014 User Manual End of String Register (EOSR) VMEbus Address: Base Address + 11F hex Attributes: Write Only, Internal to TLC W 7 6 5 4 3 2 1 0 EOS7 EOS6 EOS5 EOS4 EOS3 EOS2 EOS1 EOS0 The End Of String Register (EOSR) holds...
Page 90 - DMA Registers
Register Descriptions Chapter 4 GPIB-1014 User Manual 4-46 © National Instruments Corporation DMA Registers The onboard DMA Controller is a 68450 DMAC. This chip is extremely flexible and uses fourindependent DMA channels. The DMAC can support single address (flyby) transfers or dualaddress (flowthr...
Page 92 - Address Registers
Register Descriptions Chapter 4 GPIB-1014 User Manual 4-48 © National Instruments Corporation The following paragraphs describe the channel configuration and status registers. Moreinformation on the 68450 can be found in the Motorola Semiconductor Technical DataMC68450 Advance Information Direct Mem...
Page 93 - Transfer Count Registers
Chapter 4 Register Descriptions © National Instruments Corporation 4-49 GPIB-1014 User Manual Transfer Count Registers The Memory Transfer Counter Register (MTCR) and the Base Transfer Counter Register(BTCR) are 16-bit registers. The MTCR is used to specify how many operands will betransferred. (An ...
Page 94 - Function Code Registers; Read as zeros or ones.
Register Descriptions Chapter 4 GPIB-1014 User Manual 4-50 © National Instruments Corporation Function Code Registers VMEbus Address: Base Address + 29 (hex) for Memory Function CodeBase Address + 31 (hex) for Device Function CodeBase Address + 39 (hex) for Base Function Code Attributes: Read/Write,...
Page 95 - Device Control Register
Chapter 4 Register Descriptions © National Instruments Corporation 4-51 GPIB-1014 User Manual Device Control Register VMEbus Address: Base Address + 04 (hex) Attributes: Read/Write, Internal to DMAC 7 6 5 4 3 2 1 0 XRM DTYP DPS 0 PCL R/W The Device Control Register (DCR) is a device-soriented contro...
Page 97 - Operation Control Register
Chapter 4 Register Descriptions © National Instruments Corporation 4-53 GPIB-1014 User Manual Operation Control Register VMEbus Address: Base Address + 05 (hex) Attributes: Read/Write, Internal to DMAC 7 6 5 4 3 2 1 0 DIR 0 SIZE CHN REQG R/W The Operation Control Register (OCR) is an operation-orien...
Page 99 - Sequence Control Register
Chapter 4 Register Descriptions © National Instruments Corporation 4-55 GPIB-1014 User Manual Sequence Control Register VMEbus Address: Base Address + 06 (hex) Attributes: Read/Write, Internal to DMAC 7 6 5 4 3 2 1 0 0 0 0 0 MAC DAC R/W The Sequence Control Register (SCR) is used to define the seque...
Page 100 - Channel Control Register
Register Descriptions Chapter 4 GPIB-1014 User Manual 4-56 © National Instruments Corporation Channel Control Register VMEbus Address: Base Address + 07 (hex) Attributes: Read/Write, Internal to DMAC 7 6 5 4 3 2 1 0 STR CNT HLT SAB EINT 0 0 0 R/W This register is used to control the operation of the...
Page 102 - Channel Status Register
Register Descriptions Chapter 4 GPIB-1014 User Manual 4-58 © National Instruments Corporation Channel Status Register VMEbus Address: Base Address + 00 (hex) Attributes: Read/Write, Internal to DMAC 7 6 5 4 3 2 1 0 COC BTC NDT ERR ACT 0 PCT PCS R/W The Channel Status Register (CSR) bits are set auto...
Page 104 - Channel Error Register
Register Descriptions Chapter 4 GPIB-1014 User Manual 4-60 © National Instruments Corporation Channel Error Register VMEbus Address: Base Address + 01 (hex) Attributes: Read Only, Internal to DMAC 7 6 5 4 3 2 1 0 ERROR CODE 0 0 0 R The Channel Error Register (CER) is an error condition register. The...
Page 105 - Channel Priority Register
Chapter 4 Register Descriptions © National Instruments Corporation 4-61 GPIB-1014 User Manual Channel Priority Register VMEbus Address: Base Address + 2D (hex) Attributes: Read/Write, Internal to DMAC 7 6 5 4 3 2 0 CP 0 0 0 0 0 0 R/W The Channel Priority Register (CPR) is used to define the priority...
Page 106 - Interrupt Vector Registers; The COC bit is set in the CSR.
Register Descriptions Chapter 4 GPIB-1014 User Manual 4-62 © National Instruments Corporation Interrupt Vector Registers Each channel has a Normal Interrupt Vector Register (NIVR) and an Error Interrupt VectorRegister (EIVR), each consisting of eight bits. The CPU responds to an interrupt request fr...
Page 107 - General Control Register
Chapter 4 Register Descriptions © National Instruments Corporation 4-63 GPIB-1014 User Manual General Control Register VMEbus Address: Base Address + FF (hex) Attributes: Read/Write, Internal to DMAC 7 6 5 4 3 2 1 0 0 0 0 0 BT BR R/W When the transfer mode is cycle steal with hold, the General Contr...
Page 108 - Configuration Registers
Register Descriptions Chapter 4 GPIB-1014 User Manual 4-64 © National Instruments Corporation Configuration Registers The GPIB-1014 contains two 8-bit write-only registers that are used to configure some of theboard operating parameters. Configuration Register 1 (CFG1) VMEbus Address: Base Address +...
Page 112 - PD7210 GPIB-IFC User Manual by NEC Electronics; Initialization
© National Instruments Corporation 5-1 GPIB-1014 User Manual Chapter 5Programming Considerations This chapter explains the initialization process, sending/receiving messages, and theserial/parallel poll process. Additional information on programming the µ PD7210 GPIB interface chip can be obtained f...
Page 113 - The 68450 DMAC is initialized as follows:
Programming Considerations Chapter 5 GPIB-1014 User Manual 5-2 © National Instruments Corporation • The Transit Receive Mode 0 (TRM0) and Transit Receive Mode 1 (TRM1) bits in theAddress Mode Register (ADMR) are cleared. All other TLC register contents should be considered as undefined while the LMR...
Page 114 - Execute the desired TLC auxiliary commands.; The GPIB-1014 as GPIB Controller; sec, and then issue the Clear IFC
Chapter 5 Programming Considerations © National Instruments Corporation 5-3 GPIB-1014 User Manual 9. Load the Parallel Poll response in the Parallel Poll Register (PPR) if local configuration isused. If using remote configuration, clear the PPR. 10. Clear power on (pon) by issuing the Immediate Exec...
Page 115 - Sending Remote Multiline Messages (Commands); There are three cases to consider when going to standby.; Going from Standby to Active Controller
Programming Considerations Chapter 5 GPIB-1014 User Manual 5-4 © National Instruments Corporation Sending Remote Multiline Messages (Commands) The GPIB-1014 sends commands as Active Controller simply by writing to the Command/DataOut Register (CDOR) in response to the CO status bit in ISR2. DMA tran...
Page 116 - Going from Active to Idle Controller; automatically unasserts ATN and the new Controller asserts ATN.
Chapter 5 Programming Considerations © National Instruments Corporation 5-5 GPIB-1014 User Manual Case 2: The TLC, as a Listener, takes control upon receipt of the Take Control Synchronouslyauxiliary command. If programmed I/O is used, the Take Control Synchronouslyauxiliary command should be issued...
Page 117 - The GPIB-1014 as GPIB Talker and Listener; LA; Programmed Implementation of Talker and Listener; Address Mode 1
Programming Considerations Chapter 5 GPIB-1014 User Manual 5-6 © National Instruments Corporation The GPIB-1014 as GPIB Talker and Listener The TLC may be either GPIB Talker or Listener, but not both simultaneously. Either function isdeactivated automatically if the other is activated. The TA, LA, a...
Page 118 - Address Mode 2; issue the Valid auxiliary command.
Chapter 5 Programming Considerations © National Instruments Corporation 5-7 GPIB-1014 User Manual Address Mode 2 Address Mode 2 is used when Talker Extended (TE) or Listener Extended (LE) functions are tobe used. TE and LE functions require receipt of two addresses (primary and secondary) beforesett...
Page 119 - Sending/Receiving Messages; Using Direct Memory Access
Programming Considerations Chapter 5 GPIB-1014 User Manual 5-8 © National Instruments Corporation 6. When the Valid auxiliary command is issued, the TLC assumes that the My Secondary Address (MSA) message has been received, which causes the following events to occur: • The LA bit to be set and the T...
Page 121 - DMA Transfers without the Carry Cycle; Figure 5-1. DMA Transfer without Carry Cycle
Programming Considerations Chapter 5 GPIB-1014 User Manual 5-10 © National Instruments Corporation DMA Transfers without the Carry Cycle Data Block A Total = N bytes NO CHAINING OR Total = N bytes Data Block A Data Block B Data Block C CHAINING DMAC VMEbus interrupt TLC interrupt Bus ErrorGPIB Sync....
Page 122 - If no chaining is required, complete the following events:
Chapter 5 Programming Considerations © National Instruments Corporation 5-11 GPIB-1014 User Manual b. A 0xFF (hex) must be written to the CSR of Channel 0 to clear any leftover error or status bits. c. The DCR of Channel 0 is loaded with the proper value to select the DMA transfer mode (cycle steal ...
Page 124 - DMA Transfers with the Carry Cycle; Figure 5-2. DMA Transfer with Carry Cycle
Chapter 5 Programming Considerations © National Instruments Corporation 5-13 GPIB-1014 User Manual DMA Transfers with the Carry Cycle Channel 0 Data Block A Total=N-1 bytes NO CHAINING OR Total=N-1 bytes Data Block A Data Bock B Data Block C CHAINING Channel 1 Block A Count=1 Block B Count=2 Carry C...
Page 125 - GPIB and the VME system memory. The sequence is as follows:
Programming Considerations Chapter 5 GPIB-1014 User Manual 5-14 © National Instruments Corporation 2. Channel 0 must be configured to provide a flyby transfer for the n-1 data bytes between the GPIB and the VME system memory. The sequence is as follows: a. Write the CCR of Channel 0 with the SAB bit...
Page 126 - DFCR, and EIVR of Channel 0 are generally not used.
Chapter 5 Programming Considerations © National Instruments Corporation 5-15 GPIB-1014 User Manual • For array or linked chaining, load the MFCR of Channel 0 with the proper data togenerate the required Address Modifier Code to access the data blocks. See Tables3-1 and 3-2 for recommended values. • ...
Page 127 - First four bytes = physical address of carry cycle byte
Programming Considerations Chapter 5 GPIB-1014 User Manual 5-16 © National Instruments Corporation i. For array or linked chaining, load the MFCR of Channel 1 with the proper value togenerate the desired address modifier code, which then accesses the data blocks. (SeeTables 3-1 and 3-2 for recommend...
Page 128 - if the TLC is a GPIB Talker.; Polling During DMAs
Chapter 5 Programming Considerations © National Instruments Corporation 5-17 GPIB-1014 User Manual 4. Once channels 0 and 1 have been configured properly, start the DMA channels. Start Channel 1 before starting Channel 0. The channels are started by writing to the CCRs withthe STR bits set. (Channel...
Page 130 - Read ISR2 to clear any interrupt bit set.; Terminating on END or EOS
Chapter 5 Programming Considerations © National Instruments Corporation 5-19 GPIB-1014 User Manual accepted by all Listeners on the GPIB (indicating a GPIB synchronization). For this reason,Channel 1 is programmed to transfer two bytes to avoid a premature COC interrupt. After thelast data byte (the...
Page 131 - Sending and Receiving Data
Programming Considerations Chapter 5 GPIB-1014 User Manual 5-20 © National Instruments Corporation Whether terminating on the END message or the EOS message (or whenever the DMA transferdoes not complete properly), the DMAC must be stopped by issuing a software abort to Channels0 and 1 by writing to...
Page 132 - Interrupts; An interrupt request is received from the GPIB TLC.
Chapter 5 Programming Considerations © National Instruments Corporation 5-21 GPIB-1014 User Manual Interrupts If the GPIB-1014 is enabled for interrupts, there are three events that can cause an interrupt onthe VMEbus. The first event is an interrupt from the TLC. The second event is a GPIBhandshake...
Page 134 - Serial Polls; Conducting a Serial Poll; Parallel Polls
Chapter 5 Programming Considerations © National Instruments Corporation 5-23 GPIB-1014 User Manual Serial Polls Conducting a Serial Poll The TLC, as CIC, can serial poll other devices as described in the IEEE 488 specification. Fromthe programming point of view, the TLC must first become Active Cont...
Page 135 - Conducting a Parallel Poll
Programming Considerations Chapter 5 GPIB-1014 User Manual 5-24 © National Instruments Corporation Although the Controller can obtain a Parallel Poll response quickly and at any time, there can beconsiderable front-end overhead during initialization to configure the devices to respondappropriately. ...
Page 136 - Send the GPIB UNL message to unaddress all GPIB Listeners.; Responding to a Parallel Poll; Enabling the TLC to participate in polls
Chapter 5 Programming Considerations © National Instruments Corporation 5-25 GPIB-1014 User Manual 2. Send the GPIB UNL message to unaddress all GPIB Listeners. 3. Send the listen address of the first device to be configured. 4. Send the GPIB PPC message to all devices followed by the PPE message fo...
Page 137 - VMEbus Interface; Data Lines; Slave Read and Write Transfers
© National Instruments Corporation 6-1 GPIB-1014 User Manual Chapter 6Theory of Operation This chapter contains a functional overview of the GPIB-1014 board and explains the operationof each functional block making up the GPIB-1014. A brief description of the GPIB-1014 interface is given in Chapter ...
Page 138 - Control Signals
Theory of Operation Chapter 6 GPIB-1014 User Manual 6-2 © National Instruments Corporation accomplished using an F245 8-bit data transceiver, which gates the upper data byte to the TLC.This data transceiver is automatically controlled by the DMAC signal HIBYTE*. When the datatransfer is on VMEbus da...
Page 139 - Control Equations of Transceivers; Table 6-1 lists the control equations for the address and data.; VMEbus Signals; HIBYTE transceiver; Address Decoding
Chapter 6 Theory of Operation © National Instruments Corporation 6-3 GPIB-1014 User Manual Control Equations of Transceivers Table 6-1 lists the control equations for the address and data. Table 6-1. Control Equations of Transceivers VMEbus Signals Transceivers Control Equations A23 through A16 AS57...
Page 140 - Clock and Reset Circuitry
Theory of Operation Chapter 6 GPIB-1014 User Manual 6-4 © National Instruments Corporation address. If DS* from the master is also asserted, local signal BRDEN* is asserted. Furtherdecoding is necessary to determine which register is being addressed. Eight data lines (A8through A1) are latched by an...
Page 141 - Configuration Register 1
Chapter 6 Theory of Operation © National Instruments Corporation 6-5 GPIB-1014 User Manual control the timing of local signal DTACK* when the board is a slave and signal to control RD*and WR* to the TLC (see Timing State Machine later in this chapter). The VMEbus signal SYSRESET* is monitored by the...
Page 143 - Configuration Register 2; Timing State Machine; Slave Cycles
Chapter 6 Theory of Operation © National Instruments Corporation 6-7 GPIB-1014 User Manual Configuration Register 2 Four discrete 74LS74A D-type flip-flops are used to implement Configuration Register 2(CFG2). Data is written into each bit of this register on the rising edge of the WR* signalgenerat...
Page 144 - DMA Cycles
Theory of Operation Chapter 6 GPIB-1014 User Manual 6-8 © National Instruments Corporation corresponds to the read access time of the TLC. Local signal SACK is asserted to drive VMEbussignal DTACK* active to indicate that the data is valid on the VMEbus data lines D07 throughD00. The data remains va...
Page 145 - DMA Gating and Control
Chapter 6 Theory of Operation © National Instruments Corporation 6-9 GPIB-1014 User Manual DMA Gating and Control The DMA Gating and Control circuitry is designed to control the DMA request/acknowledgeinterface between the DMAC and the TLC. The circuitry consists of an LS74 flip-flop andmiscellaneou...
Page 146 - A 74F85 4-bit magnitude comparator; DTB Requester and Controller
Theory of Operation Chapter 6 GPIB-1014 User Manual 6-10 © National Instruments Corporation If the carry cycle feature is not used in a DMA transfer, the CC bit in CFG1 is 0, and DMAGating and Control circuitry directs all DMA requests from the TLC to DMAC Channel 0.DMAC Channel 1 is not used and mu...
Page 147 - Figure 6-1. DTB Requester and Controller Flip-Flop Operations
Chapter 6 Theory of Operation © National Instruments Corporation 6-11 GPIB-1014 User Manual are some external requests for the bus. While the board is holding the bus and the DMACrequests the bus, the DMAC is immediately granted the bus, thus avoiding bus arbitration time. The circuitry consists of ...
Page 148 - A typical bus arbitration process is described as follows:
Theory of Operation Chapter 6 GPIB-1014 User Manual 6-12 © National Instruments Corporation received. OWN* is asserted by the DMAC to indicate that it now has ownership of the bus.BUS_REL* is asserted by the DTB Requester and Controller circuitry to indicate that it is goingto release the VMEbus. RE...
Page 149 - to become active, at which time BGIN becomes high.; GPIB Synchronization and Interrupt Control
Chapter 6 Theory of Operation © National Instruments Corporation 6-13 GPIB-1014 User Manual 4. The outputs of the 74S139 are connected to four 74LS02 gates, along with the LBROUT* signal, to assert one of the four VMEbus bus request lines (BR3* through BR0*). 5. The DTB Requester waits for the appro...
Page 152 - DMAC Channel Operation; Initialization and Transfer Phases
Theory of Operation Chapter 6 GPIB-1014 User Manual 6-16 © National Instruments Corporation 4. Clear IMR2. 5. Write a value to CFG1 to release PCL1 line (perhaps use the same value as the last write to CFG1). 6. Write a software abort to Channel 0. 7. Check, then clear the COC and ERR bits in CSR0. ...
Page 155 - Device Port Size
Chapter 6 Theory of Operation © National Instruments Corporation 6-19 GPIB-1014 User Manual Operands and Addressing. Three factors affect how the actual data is handled: device(destination) port size, operand (from source) size, and address sequencing. • Device Port Size The DCR is also used to prog...
Page 156 - Initiation and Control of Channel Operation
Theory of Operation Chapter 6 GPIB-1014 User Manual 6-20 © National Instruments Corporation address the device (VMEbus memory) in dual-address transfers. It is initiated before starting thechannel operation. The BAR is used only in chaining or continue operations. Transfer Count Register Operation. ...
Page 157 - Block Termination; The channel begins a new block transfer.
Chapter 6 Theory of Operation © National Instruments Corporation 6-21 GPIB-1014 User Manual to service the request for the halted channel. When this bit is reset, the channel resumesoperation and services any request that may have been received while the channel was halted.The HLT bit must be cleare...
Page 159 - Figure 6-2. Array Format for Array Chaining Modes
Chapter 6 Theory of Operation © National Instruments Corporation 6-23 GPIB-1014 User Manual Start of array # of entries = 3 BAR BTC DMAC Memory Address A Transfer Count A Memory Address B Transfer Count B Memory Address C Transfer Count C Data Block A Data Block B Data Block C Address and Transfer C...
Page 160 - Figure 6-3. Array Format for Linked Chaining Modes
Theory of Operation Chapter 6 GPIB-1014 User Manual 6-24 © National Instruments Corporation Start of array BAR BTC DMAC Data Block A Data Block B Data Block C Address and Transfer Count Array Data Blocks xxxx (not used) Memory Address A Transfer Count A Link to next entry Memory Address B Transfer C...
Page 162 - GPIB Interface; The GPIB-1014 is interfaced to the GPIB using an NEC
Theory of Operation Chapter 6 GPIB-1014 User Manual 6-26 © National Instruments Corporation transfer, the Memory Address and Device Address Registers point to the location of the nextoperand and the Memory Transfer Counter contains the number of operands yet to be transferred.If an error occurs duri...
Page 163 - Test and Troubleshooting; DMA Stand-Alone Testing
Chapter 6 Theory of Operation © National Instruments Corporation 6-27 GPIB-1014 User Manual request is enabled for the condition. An important fact to remember is that ISR1 and ISR2 arealways cleared when read, even if the condition that caused the bit to be initially set remains true. Data to and f...
Page 165 - Interpreting Test Procedures; Verify that the test instructions have been followed correctly.
© National Instruments Corporation 7-1 GPIB-1014 User Manual Chapter 7Diagnostic and Troubleshooting TestProcedures This chapter contains test procedures for determining if the GPIB-1014 is installed and operatingcorrectly. The tests are similar to those used by National Instruments to verify correc...
Page 166 - GPIB-1014 Hardware Installation Tests
Diagnostic and Troubleshooting Test Procedures Chapter 7 GPIB-1014 User Manual 7-2 © National Instruments Corporation 2. Examine any read and write routines being used in connection with the checkout procedure for errors. 3. Recheck the jumper settings described in Chapter 3. After these items have ...
Page 173 - GPIB synchronized
Chapter 7 Diagnostic and Troubleshooting Test Procedures © National Instruments Corporation 7-9 GPIB-1014 User Manual 113 ISR1 = 2? after transferred the first two bytes on Channel 0and the carry cycle byte on Channel 1, check if DIis cleared before write the last data byte to DIR 111 DIR = 3 write ...
Page 174 - Characteristic
© National Instruments Corporation A-1 GPIB-1014 User Manual Appendix AHardware Specifications This appendix specifies the electrical, environmental, and physical characteristics of theGPIB-1014 board and the conditions under which it should be operated. Table A-1. Electrical Characteristics Charact...
Page 175 - Dimensions
Hardware Specifications Appendix A GPIB-1014 User Manual A-2 © National Instruments Corporation Table A-3. Physical Characteristics Characteristic Specification Dimensions 6.3 in. by 9.2 in. I/O Connector GPIB-1014-1S IEEE 488 Standard 24-pin GPIB-1014-2 VMEbus P2 connector
Page 177 - Initialize the interface functions of the GPIB devices (IFC).
© National Instruments Corporation C-1 GPIB-1014 User Manual Appendix CSample Programs This appendix contains listings of routines in 68000 assembly language code that implement theessential elements of these major utility functions: • Initialize the GPIB-1014 interface (INIT). • Initialize the inte...
Page 199 - Multiline Interface Messages
Multiline Interface Messages Appendix D GPIB-1014 User Manual D-2 © National Instruments Corporation Multiline Interface Messages Hex Oct Dec ASCII Msg Hex Oct Dec ASCII Msg 00 000 0 NUL 20 040 32 SP MLA0 01 001 1 SOH GTL 21 041 33 ! MLA1 02 002 2 STX 22 042 34 " MLA2 03 003 3 ETX 23 043 35 # ML...
Page 201 - This chapter describes the operation of the GPIB.; Types of Messages
© National Instruments Corporation E-1 GPIB-1014 User Manual Appendix EOperation of the GPIB This chapter describes the operation of the GPIB. Communication among interconnected GPIB devices is achieved by passing messages through theinterface system. Types of Messages The GPIB carries device-depend...
Page 202 - The Controller-In-Charge and System Controller
Operation of the GPIB Appendix E GPIB-1014 User Manual E-2 © National Instruments Corporation Some bus configurations do not require a Controller. For example, one device may always be aTalker (called a Talk-only device) and there may be one or more Listen-only devices. A Controller is necessary whe...
Page 203 - Interface Management Lines
Appendix E Operation of the GPIB © National Instruments Corporation E-3 GPIB-1014 User Manual NRFD (not ready for data) NRFD indicates when a device is ready or not ready to receive a message byte. The line is drivenby all devices when receiving commands and by Listeners when receiving data messages...
Page 204 - Physical and Electrical Characteristics; Figure E-1. The GPIB Connector and Signal Assignments
Operation of the GPIB Appendix E GPIB-1014 User Manual E-4 © National Instruments Corporation Physical and Electrical Characteristics Devices are usually connected with a cable assembly consisting of a shielded 24 conductor cablewith both a plug and receptacle connector at each end. This design allo...
Page 206 - Configuration Requirements; The following restrictions are typical.
Operation of the GPIB Appendix E GPIB-1014 User Manual E-6 © National Instruments Corporation Figure E-3. Star Configuration Configuration Requirements To achieve the high data transfer rate that the GPIB was designed for, the physical distancebetween devices and the number of devices on the bus are...
Page 207 - Related Documents
Appendix E Operation of the GPIB © National Instruments Corporation E-7 GPIB-1014 User Manual Bus extenders are available from National Instruments and other manufacturers for use when theselimits must be exceeded. Related Documents For more information on topics covered in this section, consult the...
Page 219 - Technical Support Phone:
© National Instruments Corporation G-1 GPIB-1014 User Manual Appendix GCustomer Communication For your convenience, this appendix contains forms to help you gather the information necessaryto help us solve technical problems you might have as well as a form you can use to comment onthe product docum...
Page 220 - Technical Support Form
Technical Support Form ____________________________________________________ Photocopy this form and update it each time you make changes to your software or hardware, and use the completedcopy of this form as a reference for your current configuration. Completing this form accurately before contacti...
Page 223 - Documentation Comment Form
Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products. Thisinformation helps us provide quality products to meet your needs. Title: GPIB-1014 User Manual Edition Date: March 1997 Part Number: 320030-01 Please comment on the complete...
Page 224 - Prefix
© National Instruments Corporation Glossary-1 GPIB-1014 User Manual Glossary ___________________________________________________ Prefix Meaning Value n- µ - m- k- M- nano-micro-milli-kilo-mega- 10- 9 10- 6 10- 3 10 3 10 6 ≤ is less than or equal to ≥ is greater than or equal to ° degrees A amperes A...
Page 225 - Index; Numbers
GPIB-1014 User Manual Index- 1 © National Instruments Corporation Index Numbers 0 (Reserved Bit) Channel Error Register, 4-60Channel Priority Register, 4-61Channel Status Register, 4-59Configuration Register 2 (CFG2), 4-66Device Control Register, 4-52General Control Register, 4-63Operation Control R...
Page 227 - Clear Parallel Poll Flag command
Index GPIB-1014 User Manual Index- 3 © National Instruments Corporation C cabling, 3-10capability codes for GPIB-1014, 2-13 to 2-15CC (Carry Cycle Bit), 4-65CCR. See Channel Control Register (CCR).CDO[7-0] (Command/Data Out Bits 7 through 0), 4-7CDOR. See Command/Data Out Register (CDOR).CER. See Ch...
Page 228 - compare address lines
Index © National Instruments Corporation Index- 4 GPIB-1014 User Manual commands or command messages, E-1multiline GPIB commands (table), 4-25 to 4-26, D-2 to D-3 compare address lines location of, 3-3setting base address, 3-4 compliance levels for GPIB-1014 IEEE 1014 interrupter, 2-15configuration ...
Page 229 - data transfer features. See also DMA data transfers.
Index GPIB-1014 User Manual Index- 5 © National Instruments Corporation VMEbus, 6-3 data or data messages, E-1DATA SEND-DSEND sample program, C-14 to C-16data transfer bus (DTB) requester description of, 2-7VMEbus modules not provided, 2-7 data transfer features. See also DMA data transfers. program...
Page 230 - DMAC channel operation
Index © National Instruments Corporation Index- 6 GPIB-1014 User Manual DMA gating and control circuitry, 6-7 to 6-8DMA registers 68450 internal DMA registers (chart), 2-5Address Registers, 4-48Base Address Register (BAR), 4-48Base Transfer Counter Register (BTCR), 4-48Channel Control Register (CCR)...
Page 233 - handshake lines
Index GPIB-1014 User Manual Index- 9 © National Instruments Corporation parts list and schematic diagrams, B-1 to B-9theory of operation 68450 DMAC, 6-14 to 6-23address decoding, 6-3 to 6-4clock and reset circuitry, 6-4 to 6-5Configuration registers, 6-5 to 6-6DMA gating and control, 6-7 to 6-8DTB r...
Page 234 - interface registers
Index © National Instruments Corporation Index- 10 GPIB-1014 User Manual GPIB-1014 compatibility, 1-1GPIB-1014 compliance levels, 2-15 IFC (interface clear) line, E-3Immediate Execute Pon command codes for, 4-28description, 4-29 IMR1. See Interrupt Mask Register 1 (IMR1).initialization of GPIB-1014,...
Page 235 - jumpers and switches
Index GPIB-1014 User Manual Index- 11 © National Instruments Corporation register map, 4-1Serial Poll Mode Register (SPMR), 4-19Serial Poll Status Register (SPSR), 4-19writing to hidden registers, 4-4 Internal Counter Register (ICR), 4-34interrupt control. See GPIB Synchronization and Interrupt Cont...
Page 237 - programming
Index GPIB-1014 User Manual Index- 13 © National Instruments Corporation OCR. See Operation Control Register.operands and addressing, DMAC channel operation, 6-17operating environment, A-1Operation Control Register (OCR), 4-53 to 4-54optional equipment for GPIB-1014, 1-3 P P[3-1] (Parallel Poll Resp...
Page 238 - sending/receiving messages
Index © National Instruments Corporation Index- 14 GPIB-1014 User Manual COMMAND SEND-CSEND, C-19DATA SEND-DSEND, C-14 to C-16GPIB-1014 Sample Functions for Driver, C-2 to C-4INITIALIZE-INIT, C-5 to C-6INTERFACE CLEAR-IFC, C-7overview, C-1PASS CONTROL-PASSC, C-21READ, C-12 to C-13RECEIVE-RCV, C-11RE...
Page 239 - Configuration registers
Index GPIB-1014 User Manual Index- 15 © National Instruments Corporation overview, 5-6programmed implementation, 5-6 R READ sample program, C-12 to C-13RECEIVE-RCV sample program, C-11receiving messages. See sending/receiving messages.registers Configuration registers definition of, 2-12DMA Configur...
Page 242 - VMEbus signals
Index © National Instruments Corporation Index- 18 GPIB-1014 User Manual REN (remote enable), E-3SRQ (service request), E-3 VMEbus signals chart of, 2-1 to 2-2control signals, 6-2operation, 6-1 to 6-3 SIZE (Size Bits 5 through 4), 4-53slave-addressing, VMEbus, 2-2 to 2-3slave cycles, Timing State Ma...
Page 243 - addressed implementation
Index GPIB-1014 User Manual Index- 19 © National Instruments Corporation codes for, 4-28description, 4-31 Talker/Listener/Controller (TLC). See also Controller function; DMAC channel operation. addressed implementation Address Mode 1, 5-6Address Mode 2, 5-6 to 5-7Address Mode 3, 5-7 to 5-8 definitio...
Page 245 - troubleshooting test procedures
Index GPIB-1014 User Manual Index- 21 © National Instruments Corporation troubleshooting test procedures DMA stand alone testing, 6-24GPIB interface testing, 6-24hardware installation tests, 7-2 to 7-8interpreting test procedures, 7-1overview, 7-1verification of GPIB-1014 before installation, 3-10 U...
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