Epson ARM.POWERED ARM720T- Manuals

CONTENTS ARM720T CORE CPU MANUAL EPSON iii 10 ETM Interface 10.1 About the ETM interface .......................................................................... 10-1 10.2 Enabling and disabling the ETM7 interface ............................................. 10-1 10.3 Connections between the ETM7...

CONTENTS iv EPSON ARM720T CORE CPU MANUAL List of Figures Figure 1-1 720T Block diagram .................................................................................... 1-2 Figure 1-2 ARM720T processor functional signals....................................................... 1-3 Figure 1-3 ARM i...

CONTENTS vi EPSON ARM720T CORE CPU MANUAL List of Tables Table 1-1 Key to tables ............................................................................................... 1-6 Table 1-2 ARM instruction summary ........................................................................... 1-8 Table...

Preface ARM720T CORE CPU MANUAL EPSON xi Preface This preface introduces the ARM720T Revision 4 (AMBA AHB Bus Interface Version) CORE CPU Manual . It contains the following sections: About this document ....................................................................................................

Preface xii EPSON ARM720T CORE CPU MANUAL Chapter 8 Coprocessor Interface Read this chapter for a description on how to connect coprocessors to the ARM1156F-S coprocessor interface. Chapter 9 Debugging Your System Read this chapter for a description of the hardware extensions and integrated on-chip ...

Preface ARM720T CORE CPU MANUAL EPSON xiii Timing diagram conventions This manual contains one or more timing diagrams. The following key explains the components used in these diagrams. Any variations are clearly labeled when they occur. Therefore, no additional meaning must be attached unless speci...

Preface xiv EPSON ARM720T CORE CPU MANUAL THIS PAGE IS BLANK.

1: Introduction ARM720T CORE CPU MANUAL EPSON 1-1 1 Introduction This chapter provides an introduction to the ARM720T processor. It contains the following sections: 1.1 About the ARM720T processor .................................................................. 1-1 1.2 Coprocessors ..................

1: Introduction ARM720T CORE CPU MANUAL EPSON 1-3 The functional signals on the ARM720T processor are shown in Figure 1-2. Figure 1-2 ARM720T processor functional signals 1.1.1 EmbeddedICE-RT logic The EmbeddedICE-RT logic provides integrated on-chip debug support for the ARM720T core. It enables yo...

1: Introduction 1-4 EPSON ARM720T CORE CPU MANUAL Changes to the programmer’s model To provide support for the EmbeddedICE-RT macrocell, the following changes have been made to the programmer’s model for the ARM720T processor:Debug Control Register There are two new bits in the Debug Control Registe...

1: Introduction ARM720T CORE CPU MANUAL EPSON 1-5 1.2 Coprocessors The ARM720T processor has an internal coprocessor designated CP15 for internal control of the device (see Chapter 3 Configuration ). The ARM720T processor also includes a port for the connection of on-chip external coprocessors. This...

1: Introduction 1-6 EPSON ARM720T CORE CPU MANUAL 1.3.1 Format summary This section provides a summary of the ARM and Thumb instruction sets: • ARM instruction set on page 1-7 • Thumb instruction set on page 1-14 A key to the instruction set tables is shown in Table 1-1.The ARM7TDMI-S core on the AR...

1: Introduction ARM720T CORE CPU MANUAL EPSON 1-7 1.3.2 ARM instruction set This section gives an overview of the ARM instructions available. For full details of these instructions, see the ARM Architecture Reference Manual . The ARM instruction set formats are shown in Figure 1-3. Figure 1-3 ARM in...

1: Introduction 1-10 EPSON ARM720T CORE CPU MANUAL Addressing mode 2, <a_mode2> , is shown in Table 1-3. Coprocessors Data operations CDP{cond} p<cpnum>, <op1>, <CRd>, <CRn>, <CRm>, <op2> Move to ARM reg from coproc MRC{cond} p<cpnum>, <op1>, <...

1: Introduction ARM720T CORE CPU MANUAL EPSON 1-11 Addressing mode 2 (privileged), <a_mode2P> , is shown in Table 1-4. Addressing mode 3 (signed byte, and halfword data transfer), <a_mode3> , is shown in Table 1-5. Addressing mode 4 (load), <a_mode4L> , is shown in Table 1-6. Table...

1: Introduction 1-12 EPSON ARM720T CORE CPU MANUAL Addressing mode 4 (store), <a_mode4S> , is shown in Table 1-7. Addressing mode 5 (coprocessor data transfer), <a_mode5> , is shown in Table 1-8. Operand 2, <Oprnd2> , is shown in Table 1-9. Fields, {field} , are shown in Table 1-10...

1: Introduction 1-14 EPSON ARM720T CORE CPU MANUAL 1.3.3 Thumb instruction set This section gives an overview of the Thumb instructions available. For full details of these instructions, see the ARM Architecture Reference Manual . The Thumb instruction set formats are shown in Figure 1-4. Figure 1-4...

1: Introduction 1-18 EPSON ARM720T CORE CPU MANUAL 1.4 Silicon revisions This manual is for revision r4p2 of the ARM720T macrocell. See Product revision status on page xii for details of revision numbering. There are no functional differences from previous revisions.

2: Programmer’s Model ARM720T CORE CPU MANUAL EPSON 2-1 2 Programmer’s Model This chapter describes the programmer’s model for the ARM720T processor. It contains the following sections: 2.1 Processor operating states ......................................................................... 2-1 2.2 M...

2: Programmer’s Model 2-2 EPSON ARM720T CORE CPU MANUAL 2.2 Memory formats The ARM720T processor views memory as a linear collection of bytes numbered upwards from zero, as follows: Bytes 0 to 3 Hold the first stored word. Bytes 4 to 7 Hold the second stored word. Bytes 8 to 11 Hold the third stored...

2: Programmer’s Model ARM720T CORE CPU MANUAL EPSON 2-3 2.2.2 Little-endian format In little-endian format, the lowest numbered byte in a word is considered the least significant byte of the word, and the highest numbered byte the most significant. Byte 0 of the memory system is therefore connected ...

2: Programmer’s Model 2-4 EPSON ARM720T CORE CPU MANUAL 2.5 Operating modes The ARM720T processor supports seven modes of operation, as shown in Table 2-1. 2.5.1 Changing operating modes Mode changes can be made under software control, by external interrupts or during exception processing. Most appl...

2: Programmer’s Model ARM720T CORE CPU MANUAL EPSON 2-5 Interrupt modes FIQ mode has seven banked registers mapped to r8-14 (r8_fiq-r14_fiq). In ARM state, many FIQ handlers can use these banked registers to avoid having to save any registers onto a stack. User, IRQ, Supervisor, Abort, and Undefined...

2: Programmer’s Model 2-6 EPSON ARM720T CORE CPU MANUAL 2.6.2 The Thumb state register set The Thumb state register set is a subset of the ARM state set. You have direct access to: • eight general registers, (r0–r7) • the PC • a Stack Pointer (SP) register • a Link Register (LR) • the CPSR. There ar...

2: Programmer’s Model ARM720T CORE CPU MANUAL EPSON 2-7 2.6.3 The relationship between ARM and Thumb state registers The Thumb state registers relate to the ARM state registers in the following ways: • Thumb state r0–r7, and ARM state r0–r7 are identical • Thumb state CPSR and SPSRs, and ARM state C...

2: Programmer’s Model 2-8 EPSON ARM720T CORE CPU MANUAL 2.7 Program status registers The ARM720T processor contains a CPSR, and five SPSRs for use by exception handlers. These registers: • hold information about the most recently performed ALU operation • control the enabling and disabling of interr...

2: Programmer’s Model ARM720T CORE CPU MANUAL EPSON 2-9 2.7.3 Reserved bits The remaining bits in the PSRs are reserved. When changing flag or control bits of a PSR, you must ensure that these unused bits are not altered. Also, your program must not rely on them containing specific values, because i...

2: Programmer’s Model 2-10 EPSON ARM720T CORE CPU MANUAL 2.8 Exceptions Exceptions arise whenever the normal flow of a program has to be halted temporarily, for example to service an interrupt from a peripheral. Before an exception can be handled, the current processor state is preserved so that the...

2: Programmer’s Model ARM720T CORE CPU MANUAL EPSON 2-11 2.8.2 Action on leaving an exception On completion, the exception handler: 1 Moves the LR, minus an offset where appropriate, to the PC. The offset varies depending on the type of exception. 2 Copies the SPSR back to the CPSR. 3 Clears the int...

2: Programmer’s Model 2-12 EPSON ARM720T CORE CPU MANUAL 2.8.4 Fast interrupt request The FIQ exception is used for most performance-critical interrupts in a system. In ARM state the processor has sufficient private registers to remove the necessity for register saving, minimizing the overhead of co...

2: Programmer’s Model ARM720T CORE CPU MANUAL EPSON 2-13 After fixing the reason for the abort, the handler must execute the following irrespective of the processor state (ARM or Thumb): SUBS PC, r14_abt, #4 for a Prefetch Abort SUBS PC, r14_abt, #8 for a Data Abort This restores both the PC and the...

2: Programmer’s Model 2-14 EPSON ARM720T CORE CPU MANUAL 2.8.10 Exception priorities When multiple exceptions arise at the same time, a fixed priority system determines the order in which they are handled: 1 Reset (highest priority). 2 Data Abort. 3 FIQ. 4 IRQ. 5 Prefetch Abort. 6 Undefined Instruct...

2: Programmer’s Model ARM720T CORE CPU MANUAL EPSON 2-15 2.9 Relocation of low virtual addresses by the FCSE PID The ARM720T processor provides a mechanism, Fast Context Switch Extension (FCSE), to translate virtual addresses to physical addresses based on the current value of the FCSE Process IDent...

2: Programmer’s Model 2-16 EPSON ARM720T CORE CPU MANUAL 2.10 Reset When the HRESETn signal goes LOW, the ARM720T processor: 1 Abandons the executing instruction. 2 Flushes the cache and Translation Lookaside Buffer (TLB). 3 Disables the Write Buffer (WB), cache, and MMU. 4 Resets the FCSE PID. 5 Co...

2: Programmer’s Model ARM720T CORE CPU MANUAL EPSON 2-17 2.11 Implementation-defined behavior of instructions The ARM Architecture Reference Manual defines the instruction set of the ARM720T processor: • See Indexed addressing on a Data Abort for the behavior of instructions that are identified as i...

3: Configuration ARM720T CORE CPU MANUAL EPSON 3-1 3 Configuration This chapter describes the configuration of the ARM720T processor. It contains the following sections. 3.1 About configuration.................................................................................... 3-1 3.2 Internal copro...

3: Configuration 3-2 EPSON ARM720T CORE CPU MANUAL 3.2 Internal coprocessor instructions The instruction set for the ARM720T processor enables you to implement specialized additional instructions using coprocessors. These are separate processing units that are coupled to the ARM720T processor, altho...

3: Configuration ARM720T CORE CPU MANUAL EPSON 3-3 3.3 Registers The ARM720T processor contains registers that control the cache and MMU operation. You can access these registers using MCR and MRC instructions to CP15 with the processor in a privileged mode. Table 3-1 shows a summary of valid CP15 r...

3: Configuration 3-4 EPSON ARM720T CORE CPU MANUAL 3.3.2 Control Register Reading from CP15 Register 1 reads the control bits. The CRm and opcode_2 fields Should Be Zero when reading CP15 Register 1. Control Register read format is shown in Figure 3-4. Figure 3-4 Control Register read format Writing...

3: Configuration ARM720T CORE CPU MANUAL EPSON 3-5 Bits 12:10 When read, this returns an Unpredictable value. When written, it Should Be Zero, or a value read from these bits on the same processor. Note: Using a read-write-modify sequence when modifying this register provides the greatest future com...

3: Configuration 3-6 EPSON ARM720T CORE CPU MANUAL 3.3.4 Domain Access Control Register Reading from CP15 Register 3 returns the value of the Domain Access Control Register.Writing to CP15 Register 3 writes the value of the Domain Access Control Register.The Domain Access Control Register consists o...

3: Configuration ARM720T CORE CPU MANUAL EPSON 3-7 3.3.6 Fault Address Register Reading CP15 Register 6 returns the value of the Fault Address Register (FAR). The FAR holds the virtual address of the access that was attempted when a fault occurred. The FAR is only updated on data faults. There is no...

3: Configuration 3-8 EPSON ARM720T CORE CPU MANUAL In the instructions shown in Table 3-3, c7 is the preferred value for the CRn field, because it indicates a unified MMU.Reading from CP15 Register 8 is undefined.The Invalidate TLB single entry function invalidates any TLB entry corresponding to the...

3: Configuration ARM720T CORE CPU MANUAL EPSON 3-9 3.3.10 Register 14, reserved Accessing this register is undefined. Writing to Register 14 is Undefined. 3.3.11 Test Register The CP15 Register 15 is used for device-specific test operations. For more information, see Chapter 11 Test Support .

4: Instruction and Data Cache ARM720T CORE CPU MANUAL EPSON 4-1 4 Instruction and Data Cache This chapter describes the instruction and data cache. It contains the following sections: 4.1 About the instruction and data cache ....................................................... 4-1 4.2 IDC validit...

4: Instruction and Data Cache 4-2 EPSON ARM720T CORE CPU MANUAL 4.1.3 Read-lock-write The IDC treats the read-lock-write instruction as a special case: Read phase Always forces a read of external memory, regardless of whether the data is contained in the cache. Write phase Is treated as a normal wri...

5: Write Buffer ARM720T CORE CPU MANUAL EPSON 5-1 5 Write Buffer This chapter describes the write buffer. It contains the following sections: 5.1 About the write buffer................................................................................ 5-1 5.2 Write buffer operation .......................

5: Write Buffer 5-2 EPSON ARM720T CORE CPU MANUAL 5.2 Write buffer operation You control the operation of the write buffer with CP15 register 1, the Control Register (see Control Register on page 3-4). When the CPU performs a write operation, the translation entry for that address is inspected and t...

6: The Bus Interface ARM720T CORE CPU MANUAL EPSON 6-1 6 The Bus Interface This chapter describes the signals on the bus interface of the ARM720T processor. It contains the following sections: 6.1 About the bus interface .............................................................................. ...

6: The Bus Interface 6-2 EPSON ARM720T CORE CPU MANUAL Figure 6-1 shows a transfer with no wait states (this is the simplest type of transfer). Figure 6-1 Simple AHB transfer A granted bus master starts an AHB transfer by driving the address and control signals. These signals provide the following i...

6: The Bus Interface ARM720T CORE CPU MANUAL EPSON 6-3 6.2 Bus interface signals The signals in the ARM720T processor bus interface can be grouped into the following categories: Transfer type HTRANS[1:0]See Transfer types on page 6-5. Address and control HADDR[31:0]HWRITEHSIZE[2:0]HBURST[2:0]HPROT[3...

6: The Bus Interface ARM720T CORE CPU MANUAL EPSON 6-5 6.3 Transfer types The ARM720T processor bus interface is pipelined, so the address-class signals and the memory request signals are broadcast in the bus cycle ahead of the bus cycle to which they refer. This gives the maximum time for a memory ...

6: The Bus Interface ARM720T CORE CPU MANUAL EPSON 6-7 6.4 Address and control signals The address and control signals are described in the following sections: • HADDR[31:0] • HWRITE • HSIZE[2:0] • HBURST[2:0] on page 6-8 • HPROT[3:0] on page 6-8. 6.4.1 HADDR[31:0] HADDR[31:0] is the 32-bit address ...

6: The Bus Interface ARM720T CORE CPU MANUAL EPSON 6-9 6.5 Slave transfer response signals After a master has started a transfer, the slave determines how the transfer progresses. No provision is made in the AHB specification for a bus master to cancel a transfer after it has begun.Whenever a slave ...

6: The Bus Interface 6-10 EPSON ARM720T CORE CPU MANUAL 6.5.2 HRESP[1:0] HRESP[1:0] is used by the slave to show the status of a transfer. The HRESP[1:0] encodings are shown in Table 6-5. For a full description of the slave transfer responses, see the AMBA Specification (Rev 2.0) . 6.6 Data buses To...

6: The Bus Interface ARM720T CORE CPU MANUAL EPSON 6-11 6.6.2 HRDATA[31:0] The read data bus is driven by the appropriate slave during read transfers. If the slave extends the read transfer by holding HREADY LOW, the slave has to provide valid data only at the end of the final cycle of the transfer,...

6: The Bus Interface 6-12 EPSON ARM720T CORE CPU MANUAL Table 6-7 shows active byte lanes for big-endian systems. 6.7 Arbitration The arbitration mechanism is described fully in the AMBA Specification (Rev 2.0) . This mechanism is used to ensure that only one master has access to the bus at any one ...

6: The Bus Interface ARM720T CORE CPU MANUAL EPSON 6-13 6.8 Bus clocking There are two clock inputs on the ARM720T processor bus interface. 6.8.1 HCLK The bus is clocked by the system clock, HCLK. This clock times all bus transfers. All signal timings are related to the rising edge of HCLK. 6.8.2 HC...

7: Memory Management Unit ARM720T CORE CPU MANUAL EPSON 7-1 7 Memory Management Unit This chapter describes the Memory Management Unit (MMU). It contains the following sections: 7.1 About the MMU.......................................................................................... 7-1 7.2 MMU pr...

7: Memory Management Unit 7-2 EPSON ARM720T CORE CPU MANUAL 7.1.1 Access permissions and domains For large and small pages, access permissions are defined for each subpage (4KB for small pages, 16KB for large pages). Sections and tiny pages have a single set of access permissions. All regions of mem...

7: Memory Management Unit ARM720T CORE CPU MANUAL EPSON 7-3 7.2 MMU program-accessible registers Table 7-1 lists the CP15 registers that are used in conjunction with page table descriptors stored in memory to determine the operation of the MMU. All the CP15 MMU registers, except register c8, contain...

7: Memory Management Unit 7-4 EPSON ARM720T CORE CPU MANUAL 7.3 Address translation The MMU translates VAs generated by the CPU core, and by CP15 register c13, into physical addresses to access external memory. It also derives and checks the access permission, using the TLB.The MMU table walking har...

7: Memory Management Unit 7-6 EPSON ARM720T CORE CPU MANUAL 7.3.2 Level one fetch Bits [31:14] of the Translation Table Base Register are concatenated with bits [31:20] of the MVA to produce a 30-bit address as shown in Figure 7-3. Figure 7-3 Accessing translation table level one descriptors This ad...

7: Memory Management Unit ARM720T CORE CPU MANUAL EPSON 7-7 Level one descriptor bit assignments are shown in Table 7-2. The two least significant bits of the level one descriptor indicate the descriptor type as shown in Table 7-3. Table 7-2 Level one descriptor bits Bits Description Section Coarse ...

7: Memory Management Unit 7-8 EPSON ARM720T CORE CPU MANUAL 7.3.4 Section descriptor A section descriptor provides the base address of a 1MB block of memory. Figure 7-5 shows the format of a section descriptor. Figure 7-5 Section descriptor Section descriptor bit assignments are described in Table 7...

7: Memory Management Unit ARM720T CORE CPU MANUAL EPSON 7-9 Coarse page table descriptor bit assignments are described in Table 7-5. 7.3.6 Fine page table descriptor A fine page table descriptor provides the base address of a page table that contains level two descriptors for large page, small page,...

7: Memory Management Unit 7-10 EPSON ARM720T CORE CPU MANUAL 7.3.7 Translating section references Figure 7-8 shows the complete section translation sequence. Figure 7-8 Section translation   Note: You must check access permissions contained in the level one descriptor before generating the physical ...

7: Memory Management Unit ARM720T CORE CPU MANUAL EPSON 7-11 A level two descriptor defines a tiny, a small, or a large page descriptor, or is invalid: • a large page descriptor provides the base address of a 64KB block of memory • a small page descriptor provides the base address of a 4KB block of ...

7: Memory Management Unit 7-12 EPSON ARM720T CORE CPU MANUAL 7.3.9 Translating large page references Figure 7-10 shows the complete translation sequence for a 64KB large page. Figure 7-10 Large page translation from a coarse page table Because the upper four bits of the page index and low-order four...

7: Memory Management Unit ARM720T CORE CPU MANUAL EPSON 7-13 7.3.10 Translating small page references Figure 7-11 shows the complete translation sequence for a 4KB small page. Figure 7-11 Small page translation from a coarse page table If a small page descriptor is included in a fine page table, the...

7: Memory Management Unit 7-14 EPSON ARM720T CORE CPU MANUAL 7.3.11 Translating tiny page references Figure 7-12 shows the complete translation sequence for a 1KB tiny page. Figure 7-12 Tiny page translation from a fine page table Page translation involves one additional step beyond that of a sectio...

7: Memory Management Unit ARM720T CORE CPU MANUAL EPSON 7-15 7.4 MMU faults and CPU aborts The MMU generates an abort on the following types of faults: • alignment faults (data accesses only) • translation faults • domain faults • permission faults. In addition, an external abort can be raised by th...

7: Memory Management Unit 7-16 EPSON ARM720T CORE CPU MANUAL 7.5 Fault address and fault status registers On an abort, the MMU places an encoded 4-bit value, FS[3:0], along with the 4-bit encoded domain number, in the data FSR, and the MVA associated with the abort is latched into the FAR. If an acc...

7: Memory Management Unit ARM720T CORE CPU MANUAL EPSON 7-17 7.6 Domain access control MMU accesses are primarily controlled through the use of domains. There are 16 domains and each has a 2-bit field to define access to it. Two types of user are supported, clients and managers. The domains are defi...

7: Memory Management Unit 7-18 EPSON ARM720T CORE CPU MANUAL Table 7-10 shows how to interpret the Access Permission (AP) bits and how their interpretation is dependent on the S and R bits (control register bits 8 and 9). Table 7-11 Interpreting access permission (AP) bits AP S R Supervisorpermissio...

7: Memory Management Unit ARM720T CORE CPU MANUAL EPSON 7-19 7.7 Fault checking sequence The sequence the MMU uses to check for access faults is different for sections and pages. The sequence for both types of access is shown in Figure 7-14. Figure 7-14 Sequence for checking faults The conditions th...

7: Memory Management Unit 7-20 EPSON ARM720T CORE CPU MANUAL 7.7.2 Translation fault There are two types of translation fault: Section A section translation fault is generated if the level one descriptor is marked as invalid. This happens if bits [1:0] of the descriptor are both 0. Page A page trans...

7: Memory Management Unit ARM720T CORE CPU MANUAL EPSON 7-21 7.8 External aborts In addition to the MMU-generated aborts, the ARM720T processor can be externally aborted by the AMBA bus. This can be used to flag an error on an external memory access. However, not all accesses can be aborted in this ...

8: Coprocessor Interface ARM720T CORE CPU MANUAL EPSON 8-1 8 Coprocessor Interface This chapter describes the coprocessor interface on the ARM720T processor. It contains the following sections: 8.1 About coprocessors ......................................................................................

8: Coprocessor Interface 8-2 EPSON ARM720T CORE CPU MANUAL The coprocessor: 1 Decodes instructions to determine whether it can accept the instruction. 2 Indicates whether it can accept the instruction (by signaling on EXTCPA and EXTCPB). 3 Fetches any values required from its own register bank. 4 Pe...

8: Coprocessor Interface ARM720T CORE CPU MANUAL EPSON 8-3 8.2 Coprocessor interface signals The signals used to interface the ARM720T core to a coprocessor are grouped into four categories.The clock and clock control signals include the main processor clock and bus reset: • HCLK • EXTCPCLKEN • HRES...

8: Coprocessor Interface 8-4 EPSON ARM720T CORE CPU MANUAL 8.3 Pipeline-following signals Every coprocessor in the system must contain a pipeline follower to track the instructions executing in the ARM720T processor pipeline. The coprocessors connect to the ARM720T processor input data bus, EXTCPDOU...

8: Coprocessor Interface ARM720T CORE CPU MANUAL EPSON 8-5 8.4 Coprocessor interface handshaking The ARM720T core and any coprocessors in the system perform a handshake using the signals shown in Table 8-2. These signals are explained in more detail in Coprocessor signaling on page 8-6. 8.4.1 The co...

8: Coprocessor Interface 8-6 EPSON ARM720T CORE CPU MANUAL 8.4.3 Coprocessor signaling The coprocessor signals as follows: Coprocessor absent If a coprocessor cannot accept the instruction currently in Decode it must leave EXTCPA and EXTCPB both HIGH. Coprocessor present If a coprocessor can accept ...

8: Coprocessor Interface ARM720T CORE CPU MANUAL EPSON 8-7 8.4.5 Coprocessor register transfer instructions The coprocessor register transfer instructions, MCR and MRC, transfer data between a register in the ARM720T processor register bank and a register in the coprocessor register bank. An example...

8: Coprocessor Interface 8-8 EPSON ARM720T CORE CPU MANUAL 8.4.7 Coprocessor load and store operations The coprocessor load and store instructions, LDC and STC, are used to transfer data between a coprocessor and memory. They can be used to transfer either a single word of data or a number of the co...

8: Coprocessor Interface ARM720T CORE CPU MANUAL EPSON 8-9 8.5 Connecting coprocessors A coprocessor in a system based on an ARM720T processor must have 32-bit connections to: • transfer data from memory (instruction stream and LDC) • write data from the ARM720T processor (MCR) • read data to the AR...

8: Coprocessor Interface 8-10 EPSON ARM720T CORE CPU MANUAL 8.6 Not using an external coprocessor If you are implementing a system that does not include any external coprocessors, you must tie both EXTCPA and EXTCPB HIGH. This indicates that no external coprocessors are present in the system. If any...

9: Debugging Your System 9-2 EPSON ARM720T CORE CPU MANUAL 9.1 About debugging your system The advanced debugging features of the ARM720T processor make it easier to develop application software, operating systems, and the hardware itself. 9.1.1 A typical debug system The ARM720T processor forms one...

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-3 9.2 Controlling debugging The major blocks of the ARM720T processor are: ARM CPU core This has hardware support for debug. EmbeddedICE-RT macrocell A set of registers and comparators that you use to generate debug exceptions (such as breakpo...

9: Debugging Your System 9-4 EPSON ARM720T CORE CPU MANUAL 9.2.1 Debug modes You can perform debugging in either of the following modes: Halt mode When the system is in halt mode, the core enters debug state when it encounters a breakpoint or a watchpoint. In debug state, the core is stopped and iso...

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-5 9.3 Entry into debug state If the system is in halt mode, any of the following types of interrupt force the processor into debug state: • a breakpoint (a given instruction fetch) • a watchpoint (a data access) • an external debug request. No...

9: Debugging Your System 9-6 EPSON ARM720T CORE CPU MANUAL 9.3.1 Entry into debug state on breakpoint The ARM720T processor marks instructions as being breakpointed as they enter the instruction pipeline, but the core does not enter debug state until the instruction reaches the Execute stage. Breakp...

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-7 9.3.3 Entry into debug state on debug request An ARM720T core in halt mode can be forced into debug state on debug request in either of the following ways: • through EmbeddedICE-RT programming (see Programming breakpoints on page 9-36, and P...

9: Debugging Your System 9-8 EPSON ARM720T CORE CPU MANUAL 9.3.5 Clocks The system and test clocks must be synchronized externally to the processor. The ARM Multi-ICE debug agent directly supports one or more cores within an ASIC design. Synchronizing off-chip debug clocking with the ARM720T process...

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-9 9.4 Debug interface The ARM720T processor debug interface is based on IEEE Std. 1149.1- 1990, Standard Test Access Port and Boundary-Scan Architecture . Refer to this standard for an explanation of the terms used in this chapter, and for a d...

9: Debugging Your System 9-10 EPSON ARM720T CORE CPU MANUAL 9.6 The EmbeddedICE-RT macrocell The ARM720T processor EmbeddedICE-RT macrocell module provides integrated on-chip debug support for the ARM720T core. The EmbeddedICE-RT module is connected directly to the core and therefore functions on th...

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-11 Abort status register This register identifies whether an abort exception entry was caused by a breakpoint, a watchpoint, or a real abort. For more information, see Abort status register on page 9-38. Debug Communications Channel (DCC) The ...

9: Debugging Your System 9-12 EPSON ARM720T CORE CPU MANUAL 9.8 EmbeddedICE-RT register map The locations of the EmbeddedICE-RT registers are shown in Table 9-1. 9.9 Monitor mode debugging The ARM720T processor contains logic that enables the debugging of a system without stopping the core entirely....

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-13 9.9.2 Restrictions on monitor-mode debugging There are several restrictions you must be aware of when the ARM core is configured for monitor-mode debugging: • Breakpoints and watchpoints cannot be data-dependent in monitor mode. No support ...

9: Debugging Your System 9-14 EPSON ARM720T CORE CPU MANUAL 9.10 The debug communications channel The ARM720T EmbeddedICE-RT macrocell contains a Debug Communication Channel (DCC) for passing information between the target and the host debugger. This is implemented as coprocessor 14.The DCC comprise...

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-15 The Domain Access Control Register bit assignments are shown in Table 9-2. Note: If execution is halted, bit 0 might remain asserted. The debugger can clear it by writing to the Domain Access Control Register.Writing to this register is rar...

9: Debugging Your System 9-16 EPSON ARM720T CORE CPU MANUAL 9.10.2 Communications through the DCC Messages can be sent and received through the DCC. Sending a message to the debugger Messages are sent from the processor to the debugger as follows: 1 When the processor wishes to send a message to Emb...

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-17 9.11 Scan chains and the JTAG interface There are three JTAG-style scan chains within the ARM720T processor. These enable debugging and EmbeddedICE-RT programming.A JTAG-style Test Access Port (TAP) controller controls the scan chains. For ...

9: Debugging Your System 9-18 EPSON ARM720T CORE CPU MANUAL Scan chain 15 Scan chain 15 is dedicated to the system control coprocessor registers (the CP15 registers).There are 37 bits in scan chain 15. From DBGTDI to DBGTDO, the order of the bits is: • read/write bit • instruction encoding bits [3:0...

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-19 9.12 The TAP controller The TAP controller is a state machine that determines the state of the boundary-scan test signals DBGTDI and DBGTDO. Figure 9-8 shows the state transitions that occur in the TAP controller. Figure 9-8 Test access por...

9: Debugging Your System 9-20 EPSON ARM720T CORE CPU MANUAL 9.13 Public JTAG instructions Table 9-4 shows the public JTAG instructions. In the following descriptions, the ARM720T processor samples DBGTDI and DBGTMS on the rising edge of HCLK with DBGTCKEN HIGH. The TAP controller states are shown in...

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-21 9.13.3 IDCODE (b1110) The IDCODE instruction connects the device identification code register (or ID register) between DBGTDI and DBGTDO. The ID register is a 32-bit register that enables the manufacturer, part number, and version of a comp...

9: Debugging Your System 9-22 EPSON ARM720T CORE CPU MANUAL 9.14 Test data registers The six test data registers that can connect between DBGTDI and DBGTDO are described in the following sections: • Bypass register • ARM720T processor device identification (ID) code register • Instruction register o...

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-23 9.14.3 Instruction register Purpose Changes the current TAP instruction. Length 4 bits. Operating mode In the SHIFT-IR state, the instruction register is selected as the serial path between DBGTDI, and DBGTDO.During the CAPTURE-IR state, th...

9: Debugging Your System 9-24 EPSON ARM720T CORE CPU MANUAL 9.14.5 Scan chains 1 and 2 The scan chains enable serial access to the core logic, and to the EmbeddedICE-RT hardware for programming purposes. Each scan chain cell is simple and comprises a serial register and a multiplexor. The scan cells...

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-25 During SHIFT-DR, a data value is shifted into the serial register. Bits 32 to 36 specify the address of the EmbeddedICE-RT register to be accessed. During UPDATE-DR, this register is either read or written depending on the value of bit 37 (...

9: Debugging Your System 9-26 EPSON ARM720T CORE CPU MANUAL 9.16 Examining the core and the system in debug state When the ARM720T processor is in debug state, you can examine the core and system state by forcing the load and store multiples into the instruction pipeline.Before you can examine the c...

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-27 9.16.1 Determining the core state When the processor has entered debug state from Thumb state, the simplest course of action is for the debugger to force the core back into ARM state. The debugger can then execute the same sequence of instr...

9: Debugging Your System 9-28 EPSON ARM720T CORE CPU MANUAL All these instructions execute at debug speed. Debug speed is much slower than system speed. This is because between each core clock, 33 clocks occur in order to shift in an instruction, or shift out data. Executing instructions this slowly...

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-29 When the ARM720T processor returns to debug state after a system speed access, bit 33 of scan chain 1 is set HIGH. The state of bit 33 gives the debugger information about why the core entered debug state the first time this scan chain is r...

9: Debugging Your System 9-30 EPSON ARM720T CORE CPU MANUAL Figure 9-3 on page 9-5 shows that the final memory access occurs in the cycle after DBGACK goes HIGH. This is the point at which the cycle counter must be disabled. Figure 9-11 on page 9-29 shows that the first memory access that the cycle ...

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-31 9.18.3 Watchpoint with another exception If a watchpointed access simultaneously causes a Data Abort, the ARM720T processor enters debug state in abort mode. Entry into debug is held off until the core changes into abort mode and has fetche...

9: Debugging Your System 9-32 EPSON ARM720T CORE CPU MANUAL 9.18.6 Summary of return address calculations To determine whether entry to debug state was due to a breakpoint, watchpoint, or debug request (DBGRQ), bit 33 (DBGBREAK) of scan chain 1 must be consulted together with bit 12 (DBGMOE) of the ...

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-33 9.19.2 Interrupts When the ARM720T processor enters debug state, interrupts are automatically disabled.If an interrupt is pending during the instruction prior to entering debug state, the ARM720T processor enters debug state in the mode of ...

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-35 9.20.2 Using the data, and address mask registers For each value register in a register pair, there is a mask register of the same format. Setting a bit to 1 in the mask register has the effect of making the corresponding bit in the value r...

9: Debugging Your System 9-36 EPSON ARM720T CORE CPU MANUAL DBGEXT[1:0] Is an external input to EmbeddedICE-RT logic that enables the watchpoint to be dependent on some external condition. The DBGEXT input for Watchpoint 0 is labeled DBGEXT[0].The DBGEXT input for Watchpoint 1 is labeled DBGEXT[1]. ...

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-37 3 Program the data value register only when you require a data-dependent breakpoint, that is only when you have to match the actual instruction code fetched as well as the address. If the data value is not required, program the data mask re...

9: Debugging Your System 9-38 EPSON ARM720T CORE CPU MANUAL 9.22 Programming watchpoints This section contains examples of how to program the watchpoint unit to generate breakpoints and watchpoints. Many other ways of programming the watchpoint unit registers are possible. For example, simple range ...

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-39 9.24 Debug control register The Debug Control Register is six bits wide. Writes to the Debug Control Register occur when a watchpoint unit register is written. Reads of the Debug Control Register occur when a watchpoint unit register is rea...

9: Debugging Your System 9-40 EPSON ARM720T CORE CPU MANUAL 9.24.1 Disabling interrupts IRQs and FIQs are disabled under the following conditions: • during debugging (DBGACK HIGH) • when the INTDIS bit is set. The core interrupt enable signal, IFEN, is driven as shown in Table 9-10. 9.24.2 Forcing D...

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-41 9.25 Debug status register The debug status register is 13 bits wide. If it is accessed for a write (with the read/write bit set), the status bits are written. If it is accessed for a read (with the read/write bit clear), the status bits ar...

9: Debugging Your System ARM720T CORE CPU MANUAL EPSON 9-43 9.26 Coupling breakpoints and watchpoints You can couple watchpoint units 1 and 0 together using the CHAIN and RANGE inputs. The use of CHAIN enables Watchpoint 0 to be triggered only if Watchpoint 1 has previously matched. The use of RANGE...

9: Debugging Your System 9-44 EPSON ARM720T CORE CPU MANUAL 9.26.2 DBGRNG signal The DBGRNG signal is derived as follows: DBGRNG = ((({Av[31:0],Cv[4:0]} XNOR {A[31:0],C[4:0]}) OR {Am[31:0],Cm[4:0]}) == 0xFFFFFFFFF) AND ((({Dv[31:0],Cv[7:5]} XNOR {D[31:0],C[7:5]}) OR Dm[31:0],Cm[7:5]}) == 0x7FFFFFFFF...

10: ETM Interface ARM720T CORE CPU MANUAL EPSON 10-1 10 ETM Interface This chapter describes the ETM interface that is provided on the ARM720T processor. It contains the following sections: 10.1 About the ETM interface ......................................................................... 10-1 10...

10: ETM Interface ARM720T CORE CPU MANUAL EPSON 10-3 10.4 Clocks and resets The ARM720T processor uses a single clock, HCLK, as both the main system clock and the JTAG clock. You must connect the processor clock to both HCLK and TCK on the ETM. You can then use TCKEN to control the JTAG interface.To...

11: Test Support ARM720T CORE CPU MANUAL EPSON 11-1 11 Test Support This chapter describes the test methodology and the CP15 test registers for the ARM720T processor synthesized logic and TCM. It contains the following sections: 11.1 About the ARM720T test registers.....................................

11: Test Support 11-2 EPSON ARM720T CORE CPU MANUAL 11.2 Automatic Test Pattern Generation (ATPG) Scan insertion is already performed and fixed for the ARM720T processor. You can use Automatic Test Pattern Generation (ATPG) tools to create the necessary scan patterns to test the logic outputs from a...

11: Test Support ARM720T CORE CPU MANUAL EPSON 11-3 11.3 Test State Register The test state register contains only one bit, bit 0: Bit 0 set Enable MMU and cache test. Bit 0 clear Disable MMU and cache test. At reset (HRESETn LOW), bit 0 is cleared.The test state register operations are shown in Tab...

11: Test Support 11-6 EPSON ARM720T CORE CPU MANUAL The CAM match, RAM read format for data is shown in Figure 11-9. Figure 11-9 Data format, CAM match RAM read 11.4.1 Addressing the CAM and RAM For the CAM read or write, and RAM read or write operations you must specify the segment, index, and word...

11: Test Support 11-8 EPSON ARM720T CORE CPU MANUAL ; Now read and check MOV r8,#8MOV r2,#0x10MOV r1,#0 loop1 MCR p15,3,r1,c15,c3,0 ; write C15.C to ‘0’ MCR p15,2,r2,c15,c11,2 ; read RAM to C15.C MRC p15,3,r5,c15,c3,0 ; read C15.C to R4 ADD r2,r2,#0x04CMP r5,r0BNE TEST_FAILSUBS r8,r8,#1BNE loop1B TE...

A: Signal Descriptions ARM720T CORE CPU MANUAL EPSON A-1 A Signal Descriptions This chapter describes the interface signals of the ARM720T processor. It contains the following sections: A.1 AMBA interface signals ............................................................................. A-1 A.2 C...

A: Signal Descriptions A-2 EPSON ARM720T CORE CPU MANUAL A.2 Coprocessor interface signals The coprocessor interface signals are shown in Table A-2. Table A-2 Coprocessor interface signal descriptions Name Type Description EXTCPA Input External coprocessor absent.This signal must be HIGH if no exter...

A: Signal Descriptions ARM720T CORE CPU MANUAL EPSON A-3 A.3 JTAG and test signals JTAG and test signal descriptions are shown in Table A-3. Table A-3 JTAG and test signal descriptions Name Type Description DBGIR[3:0] Output TAP instruction register.These signals reflect the current instruction load...

A: Signal Descriptions A-4 EPSON ARM720T CORE CPU MANUAL A.4 Debugger signals The debugger signal descriptions are shown in Table A-4. DBGTDO Output Test data out.JTAG test data out signal. DBGTMS Input Test mode select.JTAG test mode select signal. a. These signals are only active when scan chain 0...

A: Signal Descriptions ARM720T CORE CPU MANUAL EPSON A-5 A.5 Embedded trace macrocell interface signals The ETM interface signals are shown in Table A-5. DBGRNG[1:0] Output Range out.These signals indicate that the relevant EmbeddedICE-RT watchpoint register has matched the conditions currently pres...

A: Signal Descriptions ARM720T CORE CPU MANUAL EPSON A-7 A.6 ATPG test signals ATPG test signals used by the ARM720T processor are shown in Table A-6. A.7 Miscellaneous signals Miscellaneous signals used by the ARM720T processor are shown in Table A-7. Table A-6 ATPG test signal descriptions Name Ty...

Glossary Glossary-6 EPSON ARM720T CORE CPU MANUAL Test Access Port The collection of four mandatory and one optional terminals that form the input/output and control interface to a JTAG boundary-scan architecture. The mandatory terminals are TDI, TDO, TMS, and TCK. The optional terminal is nTRST. Th...

Index ARM DDI 0229B EPSON Index-1 Index The items in this index are listed in alphabetical order, with symbols and numerics appearing at the end. The references given are to page numbers. A Abort Data 9-6, 9-31handler 9-6mode 2-4Prefetch 9-32vector 9-31 Abort status register 9-38Aborted watchpoint 9...

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ARM720T Revision 4 (AMBA AHB Bus Interface Version) CORE CPU MANUAL EPSON Electronic Devices Website ELECTRONIC DEVICES MARKETING DIVISION http://www.epsondevice.com Issue April, 2004 Printed in Japan C A Document code: 405003400 CORE CPU MANUAL ARM720T Revision 4 (AMBA AHB Bus Interface Version) CO...