Texas Instruments TNETX4090 - Manual

Texas Instruments TNETX4090

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Table of Contents:

  • Page 2 – SWITCH
  • Page 7 – Terminal Functions
  • Page 14 – MII management interface
  • Page 15 – RDRAM interface
  • Page 16 – DIO interface
  • Page 17 – LED interface
  • Page 18 – DIO interface description; TNETX4090 Programmer’s Reference; Table 2. DIO Internal Register Address Map
  • Page 24 – a detailed description of the statistic registers.
  • Page 25 – Table 3. Port Statistics 1
  • Page 26 – Table 4. Port Statistics 2
  • Page 27 – receiving/transmitting management frames
  • Page 28 – state of DIO signal terminals during hardware reset; Following the reset, no EEPROM autoload is performed.; Table 7. DIO Interface During Hardware Reset; IEEE Std 802.1Q VLAN tags on the NM port; The first TPID byte output contains:
  • Page 29 – All other bits in the byte are reserved and are 0.; Figure 2. NM Frame Format
  • Page 30 – When; in NMRxControl
  • Page 31 – NM bandwidth and priority; PHY management interface
  • Page 32 – MAC interface; receive control
  • Page 33 – interframe gap enforcement
  • Page 34 – Mxx_RXD3 is ignored by the switch when link is low.
  • Page 36 – Figure 4. TNETX4090 Gigabit Port to SERDES Device Connections
  • Page 37 – Each of these terminals:; Table 8. Port 8 Duplex Negotiation in MII Mode
  • Page 38 – pretagging and extended port awareness; Figure 5. Transmit Pretag Timing
  • Page 39 – Table 10. Transmit Pretag Bit Definitions
  • Page 40 – Table 12. Directed Format Receive Pretag Bit Definitions; ring-cascade topology
  • Page 41 – The two IDs within the pretag are not the same.; The devices in the ring are connected as shown in Table 13.
  • Page 42 – EEPROM interface; At the end of hard reset (rising edge on RESET); Figure 9. Flash EEPROM Configuration
  • Page 43 – A current-source pullup device is provided on; interaction of EEPROM load with the SIO register; The SIO register is not loaded during the EEPROM download.; summary of EEPROM load outcomes
  • Page 44 – compatibility with future device revisions; Table 15. Port LED States; Table 16. Collision LED States
  • Page 45 – Table 17. LED Status Bit Definitions and Shift Order; lamp test; PCS duplex LED
  • Page 46 – Figure 10. Multiple RDRAM Module Connections
  • Page 47 – JTAG interface; Table 18. JTAG Instruction Opcodes; The IDCODE for the TNETX4090 is shown in Table 20.; Table 20. JTAG ID Code
  • Page 48 – frame routing; VLAN support; Figure 11. VLAN Overview
  • Page 49 – IEEE Std 802.1Q tags – reception; unknown VLAN; IEEE Std 802.1Q header – transmission
  • Page 50 – aging algorithms; frame-routing determination; TNETX4090 Programmer’s Reference Guide, literature
  • Page 53 – port routing code
  • Page 54 – removal of source port; If the source port is a member of a trunk (see; port mirroring; port trunking/load sharing
  • Page 55 – port trunking example; Table 22. Trunk Group 1 Port Membership (Trunk1Ports Register); extended port awareness
  • Page 56 – flow control
  • Page 57 – The transfer direction is determined by rdwrite.
  • Page 58 – reading RDRAM; Reading from RDRAM memory is accomplished as follows:; internal wrap test; This causes the following:
  • Page 59 – Figure 13. Internal Wrap Example; The switch is configured in the same manner as internal wrap.; Figure 14. Duplex Wrap Example
  • Page 60 – DD; recommended operating conditions
  • Page 61 – timing requirements over recommended operating conditions
  • Page 62 – physical medium attachment interface (port 8)
  • Page 63 – transmit
  • Page 64 – Figure 18. GMII Receive
  • Page 65 – Figure 20. GMII Clock
  • Page 66 – Figure 21. MII Receive
  • Page 67 – Figure 22. MII Transmit
  • Page 70 – Figure 26. DIO and DMA Reads
  • Page 73 – PARAMETER MEASUREMENT INFORMATION; Figure 30. Loading for Active Transitions
  • Page 75 – Figure 35. TTL 3-State Output Disable and Enable Voltage Waveforms
  • Page 76 – MECHANICAL DATA; PLASTIC BALL GRID ARRAY (CAVITY DOWN) PACKAGE
  • Page 77 – PACKAGING INFORMATION; PACKAGE OPTION ADDENDUM
  • Page 78 – IMPORTANT NOTICE
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TNETX4090

ThunderSWITCH II

9-PORT 100-/1000-MBIT/S ETHERNET

SWITCH

SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999

1

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

D

Single-Chip 100-/1000-Mbit/s Device

D

Integrated Physical Coding Sublayer (PCS)
Logic Provides Direct Interface to Gigabit
Transceivers

D

Integrated Address-Lookup Engine and
Table Memory for 2-K Addresses

D

Supports IEEE Std 802.1Q Virtual-LAN
(VLAN) Tagging Scheme

D

Provides Data Path for Network
Management Information [No External
Media-Access Control (MAC) Required]

D

Full-Duplex IEEE Std 802.3 Flow Control

D

Half-Duplex Back-Pressure Flow Control

D

Fully Nonblocking Architecture Using
High-Bandwidth Rambus Memory

D

Simple Expansion Via the Gigabit Interface
for Higher-Density Port Solutions

D

Port Trunking/Load Sharing for
High-Bandwidth Interswitch Links

D

Supports Pretag Extended Port Awareness

D

EEPROM Interface for Autoconfiguration
(No CPU Required for Nonmanaged Switch)

D

Provides Direct Input/Output (DIO) Interface
for Configuration and Statistics Information

D

Supports On-Chip Per-Port Storage for
Etherstat

and Remote Monitoring (RMON)

Management Information Bases (MIBs)

D

Fabricated in 2.5-/3.3-V Low-Voltage
Technology

D

Supports Ring-Cascade Mode

D

Supports Spanning Tree

D

Packaged in 352-Terminal Ball Grid Array
Package

description

The TNETX4090 is a 9-port 100-/1000-Mbit/s nonblocking Ethernet

switch with an on-chip address-lookup

engine. The TNETX4090 provides a low-cost, high-performance switch solution. The TNETX4090 is a fully
manageable desktop switch solution achieved by combining the TNETX4090 with physical interfaces and
high-bandwidth rambus-based packet memory and a CPU. The TNETX4090 also provides an interface capable
of receiving and transmitting simple-network management protocol (SNMP) and bridge protocol data units
(BPDU) (spanning tree) frames.

The TNETX4090 provides eight 10-/100-Mbit/s interfaces and one 100-/1000-Mbit/s interface. In half-duplex
mode, all ports support back-pressure flow control to reduce the risk of data loss for a long burst of activity. In
the full-duplex mode of operation, the device uses IEEE Std 802.3 frame-based flow control. With full-duplex
capability, ports 0–7 support 200-Mbit/s aggregate bandwidth connections. Port 8 supports 2 Gbit/s to desktops,
high-speed servers, hubs, or other switches in the full-duplex mode. The physical coding sublayer (PCS)
function is integrated on chip to provide a direct 10-bit interface to the gigabit Ethernet transceiver. The
TNETX4090 also supports port trunking/load sharing on the 10-/100-Mbit ports. This can be used to group ports
on interswitch links to increase the effective bandwidth between the systems. In the ring-cascade mode, port 8
can be used to connect multiple devices in a ring topology, which provides a low-cost, high-port-density desktop
switch. Pretagging and extended port awareness allow the TNETX4090 to be used as a front end to a router
or crossbar switch to build a cost-effective, high-density, high-performance system.

The internal address-lookup engine (IALE) supports up to 2-K unicast/multicast and broadcast addresses and
up to 64 IEEE Std 802.1Q VLANs. For interoperability, each port can be programmed as an access port or
non-access port to recognize VLAN tags and transmit frames with VLAN tags to other systems that support
VLAN tagging. The IALE performs destination- and source-address comparisons and forwards unknown
source- and destination-address packets to ports specified via programmable masks.

Copyright

1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TI, ThunderSWITCH, and ThunderSWITCH II are trademarks of Texas Instruments Incorporated.
Ethernet and Etherstat are trademarks of Xerox Corporation.
Secure Fast Switching is a trademark of Cabletron Systems, Inc.
Port-trunking and load-sharing algorithms were contributed by Cabletron Systems, Inc. and are derived from, and compatible with, Secure Fast
Switching

.

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Summary

Page 2 - SWITCH

TNETX4090ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description (continued) Switching Engine (Queue Manager) Rambus DRAM Controller VLAN 802.1Q and Address-Lookup Engine 2048 CAM 100/1000 ...

Page 7 - Terminal Functions

TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions JTAG interface TERMINAL I/O INTERNAL DESCRIPTION NAME NO. I/O RESISTOR† DESCRIPTION TCLK L24 I Pullup Test clock. Cl...

Page 14 - MII management interface

TNETX4090ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) 10-/100-Mbit/s MAC interface (MII mode) (ports 0–7) (continued) TERMINAL I/O INTERNAL DESCRIPTION NAME N...

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