Texas Instruments TNETE211 - Manuals

Trademarks vi Trademarks Ethernet is a trademark of Xerox Corporation. ThunderLAN and Adaptive Performance Optimization are trademarks of Texas InstrumentsIncorporated.

Contents vii Contents 1 ThunderLAN Overview 1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 ThunderLAN Architecture 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Contents viii 4.4.1 No Interrupt (Invalid Code). Int_type = 000b 4-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.2 Tx EOF Interrupt. Int_type = 001b 4-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.3 Statistics Overflow Interrupt. Int_type = 010b 4-...

Figures xi Contents Figures 1–1 The ThunderLAN Controller 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 PCI Bus Byte Assignment 1-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Tables xii Tables 2–1 ThunderLAN EEPROM Map 2-30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1 Adapter Check Bit Definitions 4-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2 Adapter ...

Tables xiii Contents A–25 ThunderLAN PHY Status Register Bits A-50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–1 PHY Generic Control Register Bits B-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–2 PHY Generic...

Running Title—Attribute Reference 1-1 Chapter Title—Attribute Reference ThunderLAN Overview The ThunderLAN family consists of highly integrated, single-chip networkinghardware. It uses a high-speed architecture that provides a complete peripher-al component interconnect (PCI)- to-10Base-T/AUI (adapt...

ThunderLAN Architecture 1-2 1.1 ThunderLAN Architecture Figure 1–1. The ThunderLAN Controller PCI Bus PCI controller FIFO registers Multiplexed SRAM LAN controller PHY LAN 802.3 100M-bps MII An integrated PHY provides interface functions for 10Base-T carrier sensemultiple access/collision detect (CS...

Networking Protocols 1-3 ThunderLAN Overview 1.2 Networking Protocols The MII also allows freedom in choosing a networking protocol. It allows theuse of standard 100M bps CSMA/CD PHY chips. ThunderLAN uses these sig-nal lines to interface to an external 100M bps demand priority PHY. This givesThunde...

PCI Interface 1-4 1.3 PCI Interface The PCI local bus is a high-performance, 32- or 64-bit bus with multiplexed ad-dress and data lines. The bus is designed to be a medium between highly inte-grated peripheral controller components such as ThunderLAN, add-in boards,and processor/memory systems. 1.3....

PCI Interface 1-5 ThunderLAN Overview 1.3.2 Byte Ordering ThunderLAN follows the PCI Local Bus Specification convention when trans- ferring data on the PCI bus. The PCI bus data is transferred on the PAD[31::0]lines. PAD31 is the most significant bit, and PAD0 is the least significant bit. The 32 da...

2-1 ThunderLAN Registers ThunderLAN uses a variety of registers to perform its networking functions.These include peripheral component interface (PCI) registers, host registers,internal direct input /output (DIO) registers, media independent interface (MII)registers, and physical interface (PHY) reg...

Register Addresses 2-2 2.1 Register Addresses The following figure shows the various register spaces provided by Thunder-LAN. It also shows how a driver uses ThunderLAN’s registers to interface toexternal devices such as PHYs, BIOS ROMs, and EEPROMs. Figure 2–1. How ThunderLAN Registers are Addresse...

PCI Configuration Space 2-4 2.2 PCI Configuration Space Figure 2–2. The PCI Configuration Space Registers read only read/write read/write read/write read/write read/write read/write read only read/write read only Byte 0 Byte 1 Byte 2 Byte 3 0 31 FFh 44h 40h 3Ch 38h 34h 30h 28h 18h 14h 10h 0Ch 08h 04...

PCI Configuration Space 2-5 ThunderLAN Registers - Set up the PCI bus. Several PCI bus options can be selected throughthese registers, including latency and grant. (Refer to PCI Local Bus Spec- ification, subsection 3.5) - Map a BIOS ROM using the BIOS ROM base address register Many of the registers...

PCI Configuration Space 2-7 ThunderLAN Registers r.h.ah = PCI_FUNCTION_ID; r.h.al = FIND_PCI_DEVICE; r.x.cx = DeviceID; r.x.dx = VendorID; r.x.si = Index; int86(PCI_INT, &r, &r); *pDev = (WORD)r.x.bx; return (int)r.h.ah; } This code returns the function ID that is used to request reads and w...

Host Registers 2-9 ThunderLAN Registers 2.3 Host Registers Figure 2–4. Host Registers offset Base address +12 +8 +4 +0 DIO_DATA DIO_ADR HOST_INT CH_PARM HOST_CMD 0 15 16 31 ThunderLAN implements the host registers shown above. These are the pri-mary control points for ThunderLAN. Through the host re...

Host Registers 2-10 To enable reads of adjacent addresses without reposting the address, bit 15of the DIO_ADR register can be set, which causes the address to be post-in-cremented by 4 after each access of the DIO_DATA register. This function isuseful when reading the statistics or reading the inter...

Internal Registers 2-11 ThunderLAN Registers 2.4 Internal Registers Figure 2–5. Internal Registers DIO address 0x44 0x40 0x3C 0x38 0x34 0x30 0x2C 0x28 0x24 0x20 0x1C 0x18 0x14 0x10 0x0C 0x08 0x04 0x00 LEDreg BSIZEreg MaxRx collisions Excessive collisions Late errors Carrier loss Acommit Multicollisi...

Internal Registers 2-12 - Setting commit levels and PCI burst levels - Interfacing via the management interface to the PHY registers - Determining status interrupts - Setting eight bytes of default PCI configuration data if the EEPROMchecksum is bad - Setting the various unicast and multicast addres...

Internal Registers 2-13 ThunderLAN Registers is used to set the network transmit commit level. The BSIZEreg register is used to set the bus burst size on both Tx and Rx frames. The internal registers are accessed via the DIO_DATA and DIO_ADR hostregisters. DIO_ADR holds the DIO address of the regist...

MII PHY Registers 2-15 ThunderLAN Registers 2.5 MII PHY Registers Figure 2–6. MII PHY Registers Register Vendor-specific registers Reserved by IEEE 802.3 Autonegotiation next page transmit Autonegotiation expansion Autonegotiation link-partner ability Autonegotiation advertisement PHY generic identi...

MII PHY Registers 2-16 The status register (GEN_sts in ThunderLAN products) includes bits to identifythe technology supported by the PHY. This technology includes protocol andduplex abilities. It indicates link, jabber, and autoconfiguration completion. Bit0 of the status register also indicates whe...

MII PHY Registers 2-17 ThunderLAN Registers is 0x1F. When the internal PHY for 10Base-T is used in a standalone mode,that is, when run from another controller through the MII pins, it is at address0x00. These are the only two addresses allowed for the internal PHY. The 100VG-AnyLAN PMI device, the T...

MII PHY Registers 2-18 up resistor, which is recommended to be attached to this line. The MII devicesshould see 1s. An alternate way to give the PHYs a series of 1s, is to: set(MDATA) set(MTXEN) clr(MCLK); //delay here DioRdByte(base_addr,Net_Sio); set(MCLK); Where MCLK is a constant for the third L...

MII PHY Registers 2-21 ThunderLAN Registers This samples data on the rising edge of the MCLK bit. Take the first bit into thePHY MII as follows: b &= ~MCLK; outp(diodata,b); b |= MDATA; outp(diodata,b); b |= MCLK; outp(diodata,b); //1 data bit out This concludes writing out the start delimiter b...

MII PHY Registers 2-22 to NetSio. Then the clock is cycled for each bit. The loop effectively cycles fivetimes. // Send the register number MSB first // Send the device number Internal=31(0x1f), External=0(0x00) for (i = 0x10;i;i >>= 1) { if (i&addr) b |= MDATA; else b &= ~MDATA; outp(...

External Devices 2-25 ThunderLAN Registers 2.6 External Devices This following section discusses the manner in which the ThunderLAN control-ler interfaces to external devices. These devices include: - A BIOS ROM - Light emitting diodes (LEDs) - A serial EEPROM - Any devices (PMIs/PMDs) attached to t...

External Devices 2-26 reserves the following two LED locations for its drivers. The bit numbers referto their locations in LEDreg. - Bit 0 (LSB) displays link status. - Bit 4 displays activity. 2.6.3 EEPROM The implementation-specific configuration information is read or written intothe EEPROM from ...

External Devices 2-30 2.6.4 ThunderLAN EEPROM Map ThunderLAN uses the following EEPROM map. Note that these values maybe used in several applications and systems including: - ThunderLAN hardware - A host running Texas Instruments ThunderLAN drivers - Texas Instruments diagnostic routines Table 2–1. ...

3-1 Initializing and Resetting This chapter describes the steps necessary to get a ThunderLAN device readyto transmit and receive frames. It provides examples of the necessary code,beginning with configuration of the ThunderLAN device on a peripheral com-ponent interconnect (PCI) system. The chapter...

Initializing 3-4 3.1.2 Finding the Controller in Memory and I/O Space To access the host registers, the I/O base address must be determined. ThisI/O base is needed, since the host registers are accessed as I/O ports. The I/Obase address register in the ThunderLAN controller has the LSB hardwired toh...

Initializing 3-5 Initializing and Resetting 3.1.3 Finding Which Interrupt was Assigned When the base register is established, the driver needs to find out what inter-rupt was assigned to the card. The next code segment from GetPciConfig be-low retrieves the PCI_INTLINE which in x86-based PCs refers ...

Initializing 3-6 3.1.4 Turning on the I/O Port and Memory Address Decode The next step in the GetPciConfig section of the code is responsible for turningon the ThunderLAN controller by enabling the decode of memory and I/O portaddresses. Without this step, there is no access to the host registers an...

Initializing 3-7 Initializing and Resetting 3.1.5 Recovering the Silicon Revision Value At this point, the sample program needs to know what the default silicon revi-sion for the controller is. There is a revision byte in the configuration space thatcan be read with a PciRdxxxx command. This configu...

Resetting 3-8 3.2 Resetting Resetting ThunderLAN is required when conditions such as an incorrect pow-er-up cause the register value in the device to deviate from that needed forproper operation. To perform either a software or hardware reset, the program-mer must complete the steps indicated. 3.2.1...

Resetting 3-9 Initializing and Resetting 3.2.2 Software Reset The driver needs to reset ThunderLAN at startup when an adapter check inter-rupt occurs or when an upper layer requires the driver to do so. ThunderLANmay only need to be reinitialized when link is lost. To reset ThunderLAN thedriver must...

4-1 Interrupt Handling ThunderLAN and its host device indicate communication with each other bysending and receiving interrupts to the bus data stream. This chapter providesinformation on setting up code which recognizes, prioritizes, and acknowl-edges these interrupts. It defines specific interrupt...

Loading and Unloading an Interrupt Service Routine (ISR) 4-3 Interrupt Handling This routine converts either the eight low hardware interrupts, or the eight highinterrupts, or a software interrupt higher than 0xF to the vector table, thenmakes an O/S call to get the old vector and slips in the new. ...

Prioritizing Adapter Interrupts 4-5 Interrupt Handling 4.2 Prioritizing Adapter Interrupts All (non-PCI) adapter interrupts are governed by the interrupt pacing timer.The interrupt pacing timer is started whenever the HOST_CMD register Ackbit is written as a 1. When this timer expires and if any int...

Interrupt Type Codes 4-7 Interrupt Handling 4.4 Interrupt Type Codes The following subsections define specific interrupt codes which may occurduring ThunderLAN operation. It describes the conditions that result from theoccurrence of interrupts, and corrective actions to overcome these conditions. 4....

Interrupt Type Codes 4-9 Interrupt Handling 4.4.6 Tx EOC Interrupt. Int_type = 101b A Tx EOC interrupt occurs when ThunderLAN encounters a forward pointerof 0 in the Tx list structure or when the Ld_Thr bit is loaded with 0. In this routinethe driver: - Gets the pointer to the Tx buffer queue - Chec...

Interrupt Type Codes 4-10 4.4.8 Adapter Check Interrupt. Int_type = 110b and Int_Vec ≠ 00h An adapter check interrupt occurs when ThunderLAN enters an unrecover-able state and must be reset. This unrecoverable condition occurs whenThunderLAN does not agree with the parameters given to it by the driv...

Interrupt Type Codes 4-12 Table 4–2. Adapter Check Failure Codes Bit Name Function 00h 01h DataPar Data parity error: Indicates that during bus master operations, ThunderLAN has de-tected a PCI bus data parity error, and parity error checking was enabled (the PAR_Enbit in the PCI command register is...

Interrupt Type Codes 4-13 Interrupt Handling The error status bits are only relevant for some adapter check failure codes,as indicated by the following table: Table 4–3. Relevance of Error Status Bits for Adapter Check Failure Codes Bit Name Channel List/Data Receive/Transmit Read/Write 01h DataPar ...

5-1 List Structures ThunderLAN controllers use a list processing method to move data in and outof the host’s memory. A list is a structure in host memory which is composedof pointers to data. The list contains information telling ThunderLAN where inthe host memory to look for the data to be transmit...

List Management 5-2 5.1 List Management Some of the more commonly used list management terms are defined here: List A list is a structure in host memory which is composed of pointers todata. The list includes information on the location of a frame, its size,and its transmission/receive status. A lis...

List Management 5-3 List Structures can keep the transmit and receive channels continuously open by freeing upbuffers and relinking lists faster than frames are transferred by ThunderLAN.This is important in receive operations where the Rx channel must be opencontinuously to avoid losing frames from...

List Management 5-4 A driver is not limited in the number of lists it can manage as long as there ismemory to put them in. The question then arises as to how many lists are ap-propriate for a certain application. The number of lists allocated should be justenough to allow the driver to use the full ...

CSTAT Field Bit Requirements 5-5 List Structures 5.2 CSTAT Field Bit Requirements Texas Instruments specifies that some bits in the CSTAT field should be setto 1, but tells you to ignore them. This is because these bits are ignored by theadapter. The ThunderLAN CSTAT is very much like that in TI380 ...

Receive List Format 5-7 List Structures 5.4 Receive List Format Figure 5–3. Receive List Format – One_Frag = 0 List offset 0x54 0x50 0x4C 0x48 0x44 0x40 0x3C 0x38 0x34 0x30 0x2C 0x28 0x24 0x20 0x1C 0x18 0x14 0x10 0x0C 0x08 0x04 0x00 Data count Data address Data count Data count Data address Data add...

Receive List Format 5-8 Table 5–1. Receive Parameter List Fields Field Definition Forward pointer This full 32-bit field contains a pointer to the next receive parameter list in the chain. Thethree LSBs of this field are ignored, as lists must always be on an eight-byte addressboundary. When the poi...

Receive List Format 5-9 List Structures Figure 5–5. Receive CSTAT Request Fields LSB MSB 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 Cmp Frm 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Table 5–2. Receive CSTAT Request Bits Bit Name Function 15 0 Ignored by adapter. Set to 0 14 Frm_Cmp 0 Frame complete: Ignored by ada...

Receive List Format 5-10 Figure 5–6. Receive CSTAT Complete Fields LSB MSB DP 0 Rx RX EOC 1 1 1 Cmp Frm 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Error pr Reserved Table 5–3. Receive CSTAT Complete Bits Bit Name Function 15 0 Same value as previously set by the host in CSTAT request field 14 Frm_Cmp 1...

Transmit List Format 5-11 List Structures 5.5 Transmit List Format Figure 5–7. Transmit List Format ... through 0x55 User-specific information ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ...

Transmit List Format 5-12 Table 5–4. Transmit Parameter List Fields Field Definition Forward pointer This 32-bit field contains a pointer to the next transmit parameter list in the chain. Thethree LSBs of this field are ignored, as lists must always be on an eight-byte addressboundary. When the forw...

Transmit List Format 5-13 List Structures Figure 5–8. Transmit CSTAT Request Fields LSB MSB Reserved Network priority 0 Pass CRC 0 0 1 1 0 Cmp Frm 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Table 5–5. Transmit CSTAT Request Bits Bit Name Function 15 x Ignored by adapter. The value in this bit is a don’...

Transmit List Format 5-14 Figure 5–9. Transmit CSTAT Complete Fields LSB MSB 0 Pass TX EOC 1 1 1 Cmp Frm 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CRC Reserved 0 Network priority Table 5–6. Transmit CSTAT Complete Bits Bit Name Function 15 x Same value as previously set by the host in the CSTAT reques...

6-1 Transmitting and Receiving Frames This chapter describes the structure and format for transmitting and receivingframes using ThunderLAN. Frames are units of data that are transmitted ona network. These must appear in a consistent, logical format to be recognized.The chapter also describes the me...

GO Command 6-4 6.2 GO Command To transmit and receive data, the ThunderLAN driver must create a linked listof frames. This subsection describes the steps to create such a linked list, andthe process for initiating transfer by using a GO command. 6.2.1 Starting Frame Reception (Rx GO Command) To crea...

GO Command 6-6 The HOST_CMD register can be written in a single, 32-bit operation. This im-plies that several commands can be combined in one operation. An Rx EOCinterrupt can be acknowledged and Rx GO commands can be reissued in asingle operation. 6.2.2 Starting Frame Transmission (Tx GO Command) T...

GO Command 6-7 Transmitting and Receiving Frames 8) Gives the TX GO command by writing the address of the first available list to the CH_PARM register 9) Writes a 1 to the GO bit of the HOST_CMD register, with the transmit chan- nel selected This assumes the transmit interrupt threshold has been ini...

7-1 Physical Interface (PHY) This chapter describes ThunderLAN support for all IEEE 802.3-compliant de-vices through its media independent interface (MII). These include the internal10Base-T physical interface (PHY) and any MII-compliant networking PHYs.It also discusses IEEE 802.12-compliant device...

MII-Enhanced Interrupt Event Feature 7-5 Physical Interface (PHY) PHY interrupt function. The INTEN bit is used to enable and disable the PHYinterrupt function. Setting the INTEN bit enables the PHY internal event sys-tem to generate interrupts; clearing the INTEN bit disables the PHY from gen-erati...

Nonmanaged Mll Devices 7-7 Physical Interface (PHY) 7.2 Nonmanaged MII Devices Nonmanaged MII devices do not have a management interface (MDIO andMDCLK). As such, they do not have any registers. The driver must have a key-word that denotes that the PHY used is nonmanaged.

PHY Initialization 7-9 Physical Interface (PHY) 7.4 PHY Initialization The driver initializes each MII-attached PHY. Since there may be more thanone PHY attached to the MII, proper initialization ensures that one and onlyone PHY is active and driving the MII. (The condition where more than onePHY dr...

A-1 Appendix A Register Definitions This appendix contains register definitions for the TNETE100A, TNETE110A,and TNETE211 ThunderLAN implementations. ThunderLAN uses these reg-isters to store information on its internal status and its communication with thehost. This appendix describes the purpose a...

PCI Configuration Registers A-2 A.1 PCI Configuration Registers The PCI specification requires all PCI devices to support a configuration regis-ter space to allow jumperless autoconfiguration. The configuration space is256 bytes in length, of which the first 64-byte header region is explicitly defin...

PCI Configuration Registers A-3 Register Definitions Figure A–1. PCI Configuration Register Address Map read only read/write read/write read/write read/write read/write read/write read only read/write read only Byte 0 Byte 1 Byte 2 Byte 3 0 31 FFh 44h 40h 3Ch 38h 34h 30h 2Ch 18h 14h 10h 0Ch 08h 04h ...

PCI Configuration Registers A-4 The first bit written to or read from the EEPROM is the most significant bit ofthe byte, such as data(7). Therefore, writing the address C0h is accomplishedby writing a 1 and six 0s. ThunderLAN expects data to be stored in the EEPROM in a specific format.Nine bytes in...

PCI Configuration Registers A-5 Register Definitions Should autoconfiguration fail (bad checksum), this register is loaded with theThunderLAN device ID of 0500h. A.1.4 PCI Command Register (@ 04h) En I/O En Mem En BM Reserved En Par En SER Reserved 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Res Table A–1...

PCI Configuration Registers A-6 A.1.5 PCI Status Register (@ 06h) cap FBB det DP (01b) DEVSEL Res ab RT ab RM err SS err DP Reserved 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Table A–2. PCI Status Register Bits Bit Name Function 15 DP_err Detected parity error: Indicates that the adapter has detected a ...

PCI Configuration Registers A-9 Register Definitions pins. On reset (software or hardware), control of the interface is given to thePCI NVRAM register. 0 1 2 3 4 5 6 7 CLOCK CDIR Reserved Reserved DATA DDIR Reserved NVPR Byte 0 Table A–3. PCI NVRAM Register Bits Bit Name Function 7 NVPR Nonvolatile ...

PCI Configuration Registers A-10 A.1.18 PCI Min_Gnt (@ 3Eh) and Max_Lat (@ 3Fh) Registers These byte registers are used to specify the adapter’s desired settings for la-tency timers. For both registers, the value specifies a period of time in units of250 ns (quarter microsecond). These registers are...

Adapter Host Registers A-12 A.2 Adapter Host Registers Host command registers contain bits which are toggled to tell the channel touse receive or transmit FIFOs. ThunderLAN’s adapter host registers includethe adapter internal registers (see section A.3, Adapter Internal Registers).The following subs...

Adapter Host Registers A-19 Register Definitions and Nes bits. This allows the value read from the interrupt register to be writtento the HOST_CMD register to directly select the appropriate channel. If no in-terrupts are active, the interrupt pacing timer is running, or the PCI interrupthas been di...

Adapter Host Registers A-20 - If ADR_SEL[1::0] = 00, the 32 LSBs of the 68-bit word are accessed. - If ADR_SEL[1::0] = 01, the middle 32 bits of the 68-bit word are accessed. - If ADR_SEL[1::0] = 1X, the four MSBs of the 68-bit word are accessed (inthe four LSBs of DIO_DATA). PCI bus-byte enables ar...

Adapter Internal Registers A-21 Register Definitions A.3 Adapter Internal Registers The adapter’s internal registers are indirectly accessible from the PCI busthrough the DIO_ADR and DIO_DATA registers. These are usually referred toas DIO. ThunderLAN has an internal 32-bit bus that is used for DIO a...

Adapter Internal Registers A-22 Figure A–4. ADAPTER Internal Register Map DIO Address Byte 3 Byte 2 Byte 1 Byte 0 NetMask NetSts NetSio NetCmd 0x00 ManTest NetConfig 0x04 Default device ID MSbyte Default device ID LSbyte Default vendor ID MSbyte Default vendor ID LSbyte 0x08 Default Max_Lat Default ...

Adapter Internal Registers A-23 Register Definitions A.3.1 Network Command Register – NetCmd @ 0x00 (DIO) All bits in this register are set to 0 on an Ad_Rst or when PRST# is asserted. 0 1 2 3 4 5 6 7 TXPACE TRFRAM DUPLEX NOBRX CAF CSF NWRAP NRESET Byte 0 Table A–8. Network Command Register Bits Bit...

Adapter Internal Registers A-24 Table A–8. Network Command Register Bits (Continued) Bit Name Function 0 TXPACE Transmit pacing (CSMA/CD): This bit allows pacing of transmitted CSMA/CD frames toimprove network utilization of network file servers. When this bit is set, the pacing algo-rithm is enable...

Adapter Internal Registers A-25 Register Definitions Table A–9. Network Serial I/O Register Bits (Continued) Bit Name Function 12 EDATA EEPROM SIO data: This bit is used to read or write the state of the EDIO pin. WhenETXEN is set to 1, EDIO is driven with the value in this bit. When ETXEN is set to...

Adapter Internal Registers A-26 Table A–10. Network Status Register Bits (Continued) Bit Name Function 20 RXSTOP Receiver stopped: This bit indicates the completion of a receive STOP command. This bit is cleared by writing a 1 to its bit position. Writing a 0 has no effect. 19 – 16 Reserved A.3.4 Ne...

Adapter Internal Registers A-27 Register Definitions A.3.5 Network Configuration Register – NetConfig @ 0x04 (DIO) This 16-bit register is used for ThunderLAN’s controller configuration. Thisregister is only writable while the ThunderLAN controller is in reset. (NRESET= 0). All bits in this register...

Adapter Internal Registers A-29 Register Definitions Table A–13. MAC Protocol Selection Codes Code MAC Protocol Selected 0xb0000000b CSMA/CD (802.3 -10/100M bps) 0b0000001b External protocol: Enhanced 802.3u interface for 802.12 – 100M bps - 100VG-AnyLAN interface, with decreased priority determined...

Adapter Internal Registers A-32 A.3.10 Network Statistics Registers – @ 0x30 – 0x40 (DIO) The network statistics registers gather frame error information. Registers varyin size, depending on the frequency with which they increment, and may be8, 16, or 24 bits wide. Reading a statistics register clea...

Adapter Internal Registers A-33 Register Definitions Table A–14. Ethernet Error Counters Counter Definition Good Tx frames are without errors. This is a 24-bit counter. Good frames are transmitted morefrequently than errored frames. Tx frames are aborted during transmission, due to frame data not be...

Adapter Internal Registers A-34 Figure A–7. Demand Priority Error Counters DIO Address Byte 3 Byte 2 Byte 1 Byte 0 0x30 Rx overrun Good Rx frames 0x34 Tx underrun Good Tx frames 0x38 Code error frames CRC error frames Deferred Tx frames 0x3C 0x40 Table A–15. Demand Priority Error Counters Counter De...

Adapter Internal Registers A-35 Register Definitions Table A–16. Adapter Commit Register Bits Bit Name Function 31 – 28 Tx commitlevel Transmit commit level: This nibble code indicates the commit size in use by the adaptertransmitter. The code indicates the number of bytes that must be in a channel’...

Adapter Internal Registers A-36 A.3.13 Burst Size Register – BSIZEreg @ 0x44 (DIO) (Byte 1) This register is used to set the receive and transmit burst sizes to be used bythe adapter. This register is only writable while the ThunderLAN controller isin reset. (NRESET = 0). This register is set to 0x2...

Adapter Internal Registers A-37 Register Definitions A.3.14 Maximum Rx Frame Size Register – MaxRx @ 0x44 (DIO) (Bytes 2 + 3) Byte 3 Byte 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Maximum Rx frame size (in units of 8 bits) This register is used to set the maximum size of received network fra...

Adapter Internal Registers A-38 A.3.15 Interrupt Disable Register - INTDIS @ 0x48 (DIO) (BYTE 0) This register is used to disable RX EOC, RX EOF and TX EOC interrupts. TXEOF can be disabled by setting to Tx interrupt threshold value to a zero. Thisregister is only written to while the ThunderLAN Con...

10Base-T PHY Registers A-40 A.4.1 PHY Generic Control Register – GEN_ctl @ 0x0 Byte 0 Byte 1 Reserved COL TEST DUPLEX AUTO RSRT ISOLATE PDOWN 0 LOOPBK RESET 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 AUTO ENB Table A–19. PHY Generic Control Register Bits Bit Name Function 15 RESET PHY reset: Writing a 1 ...

10Base-T PHY Registers A-42 A.4.2 PHY Generic Status Register – GEN_sts @ 0x1 1 JABBER LINK 1 RFLT AUTOCOMPLT 1 1 0 0 0 Byte 0 Byte 1 Reserved 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Table A–20. PHY Generic Status Register Bits Bit Name Function 15 0 100Base-T4 capable: Not supported 14 0 100Base-Tx f...

10Base-T PHY Registers A-45 Register Definitions A.4.4 Autonegotiation Advertisement Register – AN_adv @ 0x4 Selector field Technology ability field TLRFLT Reserved 0 Byte 0 Byte 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Table A–21. Autonegotiation Advertisement Register Bits Bit Name Function 15 0 Au...

10Base-T PHY Registers A-46 A.4.5 Autonegotiation Link Partner Ability Register – AN_lpa @ 0x5 selector field Link partner technology ability field Link partner LPRFLT Reserved LPNXTPAGE Byte 0 Byte 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Table A–22. Autonegotiation Link Partner Ability Register Bit...

10Base-T PHY Registers A-47 Register Definitions A.4.6 Autonegotiation Expansion Register – AN_exp @ 0x6 LPANABLE PAGERX 0 LPNPABLE PARDETFLT Reserved Byte 0 Byte 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Table A–23. Autonegotiation Expansion Register Bits Bit Name Function 15 – 5 Reserved Read as 0 4...

10Base-T PHY Registers A-49 Register Definitions A.4.8 ThunderLAN PHY Control Register – TLPHY_ctl @ 0x11 TINT INTEN NFEW MTEST SQEEN AUISEL SWAPOL IGLINK Reserved Byte 0 Byte 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Table A–24. ThunderLAN PHY Control Register Bits Bit Name Function 15 IGLINK Ignore ...

B-1 Appendix A TNETE211 100VG-AnyLAN Demand Priority Physical Media Independent (PMI) Interface This appendix contains register definitions for the TNETE211 100VG-AnyLANPMI interface. ThunderLAN uses these registers to store information on its in-ternal status and its communication with the host. Th...

100VG-AnyLAN Training B-2 B.1 100VG-AnyLAN Training The algorithm used to open ThunderLAN to the network depends on the net-work protocol in use. The demand priority protocol specified in IEEE 802.12goes through a training process to open onto the wire. To open the controllerthe driver must: - Enter...

100VG-AnyLAN Training B-4 8) The driver now waits for a status interrupt. The MASK7 bit in the NetMask register must be set for the status interrupt to reach ThunderLAN. 9) When this interrupt arrives, perform frame exchange Training involves the exchange of 24 consecutive training frames between th...

100VG-AnyLAN Training B-5 TNETE211 100VG-AnyLAN Demand Priority Physical Media Independent (PMI) Interface If the training frame passes these criteria, it is valid. The driver updates acounter showing the number of consecutive valid training frames passed. Thedriver also keeps a separate counter sho...

TNETE211 Register Descriptions B-6 B.2 TNETE211 Register Descriptions This document is a specification for ThunderLAN’s TNETE211 PMI device,which interfaces the ThunderLAN MII and the PMD device. It is responsiblefor converting the nibble stream of data from the MII to the four-pair category-3cablin...

TNETE211 Register Descriptions B-8 Table B–1. PHY Generic Control Register Bits (Continued) Bit Name Function 11 PDOWN Power down: When this bit is set (default), the PHY is placed in a low-power consump-tion state. This bit resets the 802.12 MAC state machine to MAC0. It stops the Tx andRx function...

TNETE211 Register Descriptions B-10 Table B–3. ThunderLAN PHY Control Register Bits Bit Name Function 15 IGLINK Ignore link: When this bit is set to 0, the 100VG-AnyLAN Demand Priority PHY expectsto receive link pulses from the hub, and sets the LINK bit in the GEN_sts register to0 if they are not p...

TNETE211 Register Descriptions B-11 TNETE211 100VG-AnyLAN Demand Priority Physical Media Independent (PMI) Interface B.2.6 ThunderLAN PHY Status Register – TLPHY_sts @ 0x12 LSIL LRCV RTRIDL TRFRTO LSTATE RETRAIN 0 0 0 PHOK MINT Byte 0 Byte 1 CONFIG 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Table B–4. Th...