Texas Instruments TNETE110A - Manual

Texas Instruments TNETE110A

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Table of Contents:

  • Page 6 – Preface; Read This First; About This Manual; The; How to Use This Manual
  • Page 7 – Notational Conventions; This document uses the following conventions:; Related Documentation; MAC Parameters, Physical Layer, Medium Attachment Units and
  • Page 8 – North America, South America, Central America
  • Page 9 – Trademarks; Ethernet is a trademark of Xerox Corporation.
  • Page 10 – Contents; ThunderLAN Overview
  • Page 11 – List Structures
  • Page 14 – Figures
  • Page 15 – Tables
  • Page 16 – ThunderLAN PHY Status Register Bits
  • Page 18 – High performance with low use of host CPU; Topic; Chapter 1
  • Page 19 – Figure 1–1. The ThunderLAN Controller; LAN
  • Page 20 – Networking Protocols; The DMA of data into and out of the controller
  • Page 21 – PCI Interface; PCI Cycles
  • Page 22 – Byte Ordering; ThunderLAN follows the; Figure 1–2. PCI Bus Byte Assignment
  • Page 24 – ThunderLAN Registers; Chapter 2
  • Page 25 – Register Addresses; Figure 2–1. How ThunderLAN Registers are Addressed
  • Page 27 – PCI Configuration Space; Figure 2–2. The PCI Configuration Space Registers; PCI Local Bus Specification. These enable the PCI system to:
  • Page 28 – Figure 2–3. Configuration EEPROM Data Format
  • Page 30 – The following example reads a byte of a PCI register:
  • Page 32 – Host Registers; Figure 2–4. Host Registers
  • Page 33 – byte data space—all of the avail-
  • Page 34 – Internal Registers; Figure 2–5. Internal Registers
  • Page 35 – register is used to set many of the diagnostic modes such as
  • Page 36 – is used to set the network transmit commit level. The; BSIZEreg register is used; to set the bus burst size on both Tx and Rx frames.
  • Page 38 – MII PHY Registers; Figure 2–6. MII PHY Registers; The PHY registers are accessed to:
  • Page 39 – , an internal register, which uses the pointer; MTXEN controls the direction of the MDIO pin.
  • Page 40 – The synchronization code could be done this way:
  • Page 41 – An alternate way to give the PHYs a series of 1s, is to:
  • Page 44 – 0 is the read op code for an MII management operation.
  • Page 45 – To get an idle bit, turn off the data driver, then cycle the clock.
  • Page 48 – External Devices; A BIOS ROM; BIOS ROM
  • Page 49 – Bit 4 displays activity.; EEPROM
  • Page 53 – ThunderLAN EEPROM Map; ThunderLAN hardware; Table 2–1. ThunderLAN EEPROM Map
  • Page 58 – Chapter 3
  • Page 61 – Finding the Controller in Memory and I/O Space
  • Page 62 – Finding Which Interrupt was Assigned; PCI Local
  • Page 63 – Turning on the I/O Port and Memory Address Decode; Where these constants have the following values:
  • Page 64 – Recovering the Silicon Revision Value
  • Page 65 – Resetting; Hardware Reset
  • Page 66 – Software Reset; NetSio
  • Page 68 – Interrupt Handling; Chapter 4
  • Page 70 – The code that gets executed is:
  • Page 72 – Prioritizing Adapter Interrupts; Interrupts are prioritized in the following order:
  • Page 74 – Interrupt Type Codes; be found in the
  • Page 76 – register
  • Page 77 – Disables interrupts
  • Page 79 – Table 4–2. Adapter Check Failure Codes
  • Page 80 – Write it to the CH_PARM
  • Page 82 – Chapter 5
  • Page 83 – Figure 5–1. List Pointers and Buffers
  • Page 84 – Figure 5–2. Linked List Management Technique
  • Page 85 – Copy time < Network transmit time + Service time
  • Page 86 – CSTAT Field Bit Requirements
  • Page 88 – Receive List Format
  • Page 89 – Table 5–1. Receive Parameter List Fields
  • Page 90 – Figure 5–5. Receive CSTAT Request Fields; Receive CSTAT Request Bits
  • Page 91 – Figure 5–6. Receive CSTAT Complete Fields; Table 5–3. Receive CSTAT Complete Bits
  • Page 92 – Transmit List Format; Figure 5–7. Transmit List Format
  • Page 93 – Table 5–4. Transmit Parameter List Fields
  • Page 94 – Figure 5–8. Transmit CSTAT Request Fields; Table 5–5. Transmit CSTAT Request Bits
  • Page 95 – Figure 5–9. Transmit CSTAT Complete Fields; Table 5–6. Transmit CSTAT Complete Bits
  • Page 96 – Chapter 6
  • Page 99 – GO Command
  • Page 101 – Starting Frame Transmission (Tx GO Command)
  • Page 102 – to the CH_PARM register
  • Page 104 – Physical Interface; Chapter 7
  • Page 108 – Typical interrupt-generating events are shown in Table 7–2:; Table 7–2. Possible Sources of MII Event Interrupts
  • Page 110 – Nonmanaged MII Devices
  • Page 112 – PHY Initialization
  • Page 114 – Register Definitions; Appendix A
  • Page 115 – A.1 PCI Configuration Registers
  • Page 116 – Figure A–1. PCI Configuration Register Address Map; A.1.1 PCI Autoconfiguration from External 24C02 Serial EEPROM
  • Page 117 – Figure A–2. Configuration EEPROM Data Format
  • Page 118 – Table A–1. PCI Command Register Bits
  • Page 119 – Table A–2. PCI Status Register Bits
  • Page 122 – Table A–3. PCI NVRAM Register Bits
  • Page 123 – Table A–4. PCI Reset Control Register Bits
  • Page 125 – A.2 Adapter Host Registers; Figure A–3. Host Interface Address Map
  • Page 132 – RAM Addressing
  • Page 133 – PCI Local Bus Specification conventions. ThunderLAN
  • Page 134 – A.3 Adapter Internal Registers
  • Page 135 – Figure A–4. ADAPTER Internal Register Map
  • Page 136 – Table A–8. Network Command Register Bits
  • Page 137 – Table A–9. Network Serial I/O Register Bits
  • Page 138 – Table A–10. Network Status Register Bits
  • Page 139 – Table A–11. Network Status Mask Register Bits
  • Page 140 – Table A–12. Network Configuration Register Bits
  • Page 142 – Table A–13. MAC Protocol Selection Codes; Figure A–5. Default PCI Parameter Register
  • Page 145 – Figure A–6. Ethernet Error Counters
  • Page 146 – Table A–14. Ethernet Error Counters
  • Page 147 – Figure A–7. Demand Priority Error Counters; Table A–15. Demand Priority Error Counters
  • Page 148 – Table A–16. Adapter Commit Register Bits
  • Page 149 – Table A–17. Burst Size Register Bits
  • Page 150 – If a 133-byte frame is received in PEF mode with MaxRx set to 128, then:
  • Page 151 – Table A–18. Demand Priority Error Counters
  • Page 153 – Table A–19. PHY Generic Control Register Bits
  • Page 155 – Table A–20. PHY Generic Status Register Bits
  • Page 158 – Table A–21. Autonegotiation Advertisement Register Bits
  • Page 159 – Table A–22. Autonegotiation Link Partner Ability Register Bits
  • Page 160 – Table A–23. Autonegotiation Expansion Register Bits
  • Page 162 – Table A–24. ThunderLAN PHY Control Register Bits
  • Page 166 – Demand Priority Physical; Appendix B
  • Page 167 – Figure B–1. 802.12 Training Frame Format
  • Page 169 – Figure B–2. Training Flowchart; Check that the destination address is a null
  • Page 170 – Checking the RETRAIN bit in TLPHY_sts; when status interrupt arrives
  • Page 171 – B.2 TNETE211 Register Descriptions
  • Page 173 – Table B–2. PHY Generic Status Register Bits
  • Page 175 – Table B–3. ThunderLAN PHY Control Register Bits
  • Page 176 – Table B–4. ThunderLAN PHY Status Register Bits
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ThunderLAN

TNETE100A, TNETE110A, TNETE211

Programmer’s

Guide

October 1996

Network Business Products

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Summary

Page 6 - Preface; Read This First; About This Manual; The; How to Use This Manual

iii Preface Read This First About This Manual The ThunderLAN Programmer’s Guide assists you in using the following implementations of ThunderLAN networking hardware: - TNETE100A Ethernet t controller - TNETE110A Ethernet controller - TNETE211 100 VG-AnyLAN physical media interface (PMI) How to Use T...

Page 7 - Notational Conventions; This document uses the following conventions:; Related Documentation; MAC Parameters, Physical Layer, Medium Attachment Units and

Notational Conventions iv Notational Conventions This document uses the following conventions: - Program listings, program examples, and interactive displays are shownin a special font. Examples use a bold version of the special font foremphasis. Here is a sample program listing: 11 0005 0001 .field...

Page 8 - North America, South America, Central America

If You Need Assistance / Trademarks v Read This First If You Need Assistance. . . - World-Wide Web Sites TI Online http://www.ti.com Semiconductor PIC http://www.ti.com/sc/docs/pic/home.htm Networking Home Page http://www.ti.com/sc/docs/network/nbuhomex.htm - North America, South America, Central Am...

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