Page 2 - SWITCH
TNETX4090ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description (continued) Switching Engine (Queue Manager) Rambus DRAM Controller VLAN 802.1Q and Address-Lookup Engine 2048 CAM 100/1000 ...
Page 7 - Terminal Functions
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions JTAG interface TERMINAL I/O INTERNAL DESCRIPTION NAME NO. I/O RESISTOR† DESCRIPTION TCLK L24 I Pullup Test clock. Cl...
Page 14 - MII management interface
TNETX4090ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) 10-/100-Mbit/s MAC interface (MII mode) (ports 0–7) (continued) TERMINAL I/O INTERNAL DESCRIPTION NAME N...
Page 15 - RDRAM interface
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 15 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) RDRAM interface TERMINAL I/O INTERNAL DESCRIPTION NAME NO. I/O RESISTOR DESCRIPTION DBUS_CTL Y26 O None...
Page 16 - DIO interface
TNETX4090ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) DIO interface TERMINAL I/O INTERNAL DESCRIPTION NAME NO. I/O RESISTOR DESCRIPTION SAD0SAD1 AF22 AE22 I P...
Page 17 - LED interface
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 17 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) LED interface TERMINAL I/O INTERNAL DESCRIPTION NAME NO. I/O RESISTOR DESCRIPTION LED_CLK AD19 O None L...
Page 18 - DIO interface description; TNETX4090 Programmer’s Reference; Table 2. DIO Internal Register Address Map
TNETX4090ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DIO interface description The DIO is a general-purpose interface that is used with a range of microprocessor or computer systeminterfac...
Page 24 - a detailed description of the statistic registers.
TNETX4090ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DIO interface description (continued) Table 3 and Table 4 list the least significant byte address for the port-specific statistics. Eac...
Page 25 - Table 3. Port Statistics 1
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 25 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Table 3. Port Statistics 1 TAIL PORT NO. HEAD STATISTIC EVEN PORTS ODD PORTS 0 0x80xx Receive octet 00 80 1 0x80xx Good receive frames...
Page 26 - Table 4. Port Statistics 2
TNETX4090ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Table 4. Port Statistics 2 PORT NO. HEAD STATISTIC TAIL (ALL PORTS) 0 0x900x Pause transmit frames† 0 1 0x901x Pause receive frames† 4 ...
Page 27 - receiving/transmitting management frames
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 27 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DIO interface description (continued) Table 5. Address-Lookup Statistics PORT NO. HEAD STATISTIC N/A 0x9200–0x9FFC Reserved N/A 0xA000...
Page 28 - state of DIO signal terminals during hardware reset; Following the reset, no EEPROM autoload is performed.; Table 7. DIO Interface During Hardware Reset; IEEE Std 802.1Q VLAN tags on the NM port; The first TPID byte output contains:
TNETX4090ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 state of DIO signal terminals during hardware reset The CPU can perform a hardware reset by writing to an address in the range of 0x40–...
Page 29 - All other bits in the byte are reserved and are 0.; Figure 2. NM Frame Format
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 29 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 frame format on the NM port (continued) To provide a CRC word, which includes the header, the NM port generates a new CRC word as the ...
Page 30 - When; in NMRxControl
TNETX4090ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 frame format on the NM port (continued) Any device reading frames out of the NM port must expect frames to be in the format shown in Fi...
Page 31 - NM bandwidth and priority; PHY management interface
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 31 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 full-duplex NM port The NM port can intermix reception and transmission as desired. It is the direction of the NMData access (i.e.,rea...
Page 32 - MAC interface; receive control
TNETX4090ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAC interface receive control Data received from the PHYs is interpreted and assembled into the TNETX4090 buffer memory. Interpretation...
Page 33 - interframe gap enforcement
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 33 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 adaptive performance optimization (APO) Each Ethernet MAC incorporates APO logic. This can be enabled on an individual port basis. Whe...
Page 34 - Mxx_RXD3 is ignored by the switch when link is low.
TNETX4090ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 10-/100-Mbit/s MII (ports 0–7) speed, duplex, and flow-control negotiation Each individual port can operate at 10 Mbit/s or 100 Mbit/s ...
Page 36 - Figure 4. TNETX4090 Gigabit Port to SERDES Device Connections
TNETX4090ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 100-/1000-Mbit/s PHY interface (port 8) This port is controlled by an IEEE Std 802.3-compliant MAC. speed, duplex, and flow-control neg...
Page 37 - Each of these terminals:; Table 8. Port 8 Duplex Negotiation in MII Mode
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 37 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 speed, duplex, and flow-control negotiation (continued) In 100-Mbit/s mode, M08_RXD4 and M08_RXD5 are reconfigured as open-drain input...
Page 38 - pretagging and extended port awareness; Figure 5. Transmit Pretag Timing
TNETX4090ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 pretagging and extended port awareness The TNETX4090 can be incorporated into a hierarchical system, whereby this port is connected to ...
Page 39 - Table 10. Transmit Pretag Bit Definitions
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 39 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Table 10. Transmit Pretag Bit Definitions BIT NAME FUNCTION 31–28 reserved Reserved. These bits always are 0. 27 rxheader Receive head...
Page 40 - Table 12. Directed Format Receive Pretag Bit Definitions; ring-cascade topology
TNETX4090ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Table 12. Directed Format Receive Pretag Bit Definitions BIT NAME FUNCTION 31 1 One. Indicates directed format. The frame is routed to ...
Page 41 - The two IDs within the pretag are not the same.; The devices in the ring are connected as shown in Table 13.
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 41 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ring-cascade topology (continued) D Frames received on a ring port must have an out-of-band pretag in the clock cycle before Mxx_RXDV ...
Page 42 - EEPROM interface; At the end of hard reset (rising edge on RESET); Figure 9. Flash EEPROM Configuration
TNETX4090ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 EEPROM interface The EEPROM interface is provided so the system-level manufacturer can produce a CPU-less preconfiguredsystem. This als...
Page 43 - A current-source pullup device is provided on; interaction of EEPROM load with the SIO register; The SIO register is not loaded during the EEPROM download.; summary of EEPROM load outcomes
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 43 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 EEPROM interface (continued) After the initial start condition, a slave address containing a device address of 000 is output on EDIO, ...
Page 44 - compatibility with future device revisions; Table 15. Port LED States; Table 16. Collision LED States
TNETX4090ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 44 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 compatibility with future device revisions All EEPROM locations that correspond to reserved addresses in the memory map, register bits ...
Page 45 - Table 17. LED Status Bit Definitions and Shift Order; lamp test; PCS duplex LED
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 45 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Table 17. LED Status Bit Definitions and Shift Order ORDER NAME FUNCTION slast = 0 slast = 1 NAME FUNCTION 1st–12th 11th–22nd SW0–SW11...
Page 46 - Figure 10. Multiple RDRAM Module Connections
TNETX4090ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 46 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETX4090 9 DBUS_DA T A8–DBUS_DA T A 0 DBUS_CTL DBUS_EN DRX_CLK DTX_CLK BUS_CLK TXCLK RXCLK BUS ENABLEBUS CTRL BUS DATA (8–0) Concurren...
Page 47 - JTAG interface; Table 18. JTAG Instruction Opcodes; The IDCODE for the TNETX4090 is shown in Table 20.; Table 20. JTAG ID Code
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 47 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 JTAG interface The TNETX4090 is fully IEEE Std 1149.1 compliant. It also includes on-chip pullup resistors on the five JTAGterminals t...
Page 48 - frame routing; VLAN support; Figure 11. VLAN Overview
TNETX4090ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 48 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 frame routing VLAN support The internal routing engine supports the IEEE Std 802.1Q VLANs as shown in Figure 11 and described in thefol...
Page 49 - IEEE Std 802.1Q tags – reception; unknown VLAN; IEEE Std 802.1Q header – transmission
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 49 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IEEE Std 802.1Q tags – reception By the time the IALE examines the received frame, it contains an IEEE Std 802.1Q tag header (after th...
Page 50 - aging algorithms; frame-routing determination; TNETX4090 Programmer’s Reference Guide, literature
TNETX4090ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 50 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 aging algorithms time-threshold aging When learning addresses, the IALE adds the address to the table and tags it with a time stamp. If...
Page 53 - port routing code
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 53 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 E Mirr Bit = 1? Remove: – Disabled Ports– Ports Blocked by TxBlockPorts From Port Routing Code Yes If [(Source Port = MirrorPort orPor...
Page 54 - removal of source port; If the source port is a member of a trunk (see; port mirroring; port trunking/load sharing
TNETX4090ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 54 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 removal of source port Normally, the IALE does not route a frame to a port on which it was received. The port routing code is examinedt...
Page 55 - port trunking example; Table 22. Trunk Group 1 Port Membership (Trunk1Ports Register); extended port awareness
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 55 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 port trunking example This example shows how to set up the TNETX4090 to support two port trunks. The first trunk group consistsof port...
Page 56 - flow control
TNETX4090ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 56 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 flow control The TNETX4090 supports collision-based flow control for ports in half-duplex mode and IEEE Std 802.3x flowcontrol for port...
Page 57 - The transfer direction is determined by rdwrite.
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 57 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 other flow-control mechanisms hardware flow control If a port were in MII or GMII mode and full duplex, normally, its Mxx_COL would no...
Page 58 - reading RDRAM; Reading from RDRAM memory is accomplished as follows:; internal wrap test; This causes the following:
TNETX4090ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 58 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 reading RDRAM Reading from RDRAM memory is accomplished as follows: 1. Write the byte address for the access to ramaddress in RAMAddres...
Page 59 - Figure 13. Internal Wrap Example; The switch is configured in the same manner as internal wrap.; Figure 14. Duplex Wrap Example
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 59 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 internal wrap test (continued) TNETX4090 08 07 06 05 04 03 02 01 00 NM Figure 13. Internal Wrap Example The operational status of the ...
Page 60 - DD; recommended operating conditions
TNETX4090ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 60 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) † Supply voltage range, V DD(2.5) (see Note...
Page 61 - timing requirements over recommended operating conditions
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 61 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V...
Page 62 - physical medium attachment interface (port 8)
TNETX4090ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 62 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 physical medium attachment interface (port 8) receive PMA receive (see Figure 16) NO. MIN MAX UNIT 1 tc(Mxx_RBC) Cycle time, receive by...
Page 63 - transmit
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 63 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 transmit PMA transmit (see Figure 17) NO. MIN MAX UNIT 1 tc(Mxx_GTCLK) Cycle time, Mxx_GTCLK 8† 8† ns 2,3 tw(Mxx_GTCLK) Pulse duration...
Page 64 - Figure 18. GMII Receive
TNETX4090ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 64 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 GMII (port 8) Figures 18–20 show the timing for the 100-/1000-Mbit/s GMII when operating at 1000 Mbit/s. Both Mxx_CRS and Mxx_COL are d...
Page 65 - Figure 20. GMII Clock
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 65 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PMA and GMII clock (see Figure 20) NO. MIN MAX UNIT 1 tr(Mxx_GCLK) Pulse width low, Mxx_RFCLK 2.5 ns 2 th(Mxx_GCLK) Pulse width high, ...
Page 66 - Figure 21. MII Receive
TNETX4090ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 66 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MII (ports 0–8) Figures 21–23 show the timing for the eight MIIs operating at either 10-Mbit/s or 100-Mbit/s, and the GMIIoperating at ...
Page 67 - Figure 22. MII Transmit
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 67 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MII transmit (see Figure 22) NO. MIN MAX UNIT 1 td(Mxx_TXD) Delay time, from Mxx_TCLK ↑ to Mxx_TXD3–MxxTXD0 valid 5 15 ns 1 td(Mxx_TXE...
Page 70 - Figure 26. DIO and DMA Reads
TNETX4090ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 70 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DIO and DMA reads (see Figure 26) NO. MIN MAX UNIT 1 tw(SCSL) Pulse duration, SCS low 2tc ns 2 tsu(SRNW) Setup time, SRNW valid before ...
Page 73 - PARAMETER MEASUREMENT INFORMATION; Figure 30. Loading for Active Transitions
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 73 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION The following load circuits and voltage waveforms show the conditions used for measuring switching c...
Page 75 - Figure 35. TTL 3-State Output Disable and Enable Voltage Waveforms
TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 75 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION VDD 0 20% 47% 80% Input (active-low enable) Hi-Z Active VOH Hi-Z (forced low) 50% LVCMOS1.3 V TTL tP...
Page 76 - MECHANICAL DATA; PLASTIC BALL GRID ARRAY (CAVITY DOWN) PACKAGE
TNETX4090ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 76 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA GGP (S-PBGA-N352) PLASTIC BALL GRID ARRAY (CAVITY DOWN) PACKAGE 4073223/A 11/96 A 1 3 2 F E D C K J H G B P N M W V U T...
Page 77 - PACKAGING INFORMATION; PACKAGE OPTION ADDENDUM
PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) TNETX4090GGP OBSOLETE BGA GGP 352 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new des...
Page 78 - IMPORTANT NOTICE
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers shouldobtain the l...
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