Texas Instruments TMS380C26 - Manual

Texas Instruments TMS380C26

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Table of Contents:

  • Page 2 – pinout
  • Page 3 – NETWORK COMMPROCESSOR; description
  • Page 4 – block diagram and signal descriptions; Figure 2. TMS380C26 COMMprocessor Block Diagram
  • Page 5 – Terminal Functions
  • Page 20 – architecture; local memory. Available protocols include:
  • Page 23 – Adapter-Internal Pointers
  • Page 24 – for Ethernet
  • Page 25 – User-Access Hardware Registers
  • Page 26 – SWDDIR — Current SDDIR Signal Value; Pseudo-DMA from host system to TMS380C26.
  • Page 27 – SWHRQ — Current SHRQ Signal Value
  • Page 28 – SINTEN — System-Interrupt Enable; PEN — Adapter Parity Enable
  • Page 29 – SIFACL Control for Pseudo-DMA Operation; Figure 3. Pseudo-DMA Logic Related to SIFACL Bits
  • Page 30 – Supply voltage range, V; DD; Output voltage range; recommended operating conditions
  • Page 31 – PARAMETER MEASUREMENT INFORMATION; OL; V typical timing verification; Figure 4. Test Load Circuit
  • Page 32 – Figure 5. Clock Waveforms After Clock Stabilization
  • Page 33 – timing parameter symbology; Lower case subscripts are defined as follows:
  • Page 43 – Figure 10. Memory Bus Timing: Write Cycle
  • Page 44 – Figure 11. Memory Bus Timing: TMS380C26 Releases Control of Bus
  • Page 47 – Figure 13. Memory Bus Timing: TMS380C26 Resumes Control of Bus
  • Page 52 – Figure 17. Memory Bus Timing: DRAM Refresh Cycle
  • Page 53 – Figure 18. XMATCH and XFAIL Timing
  • Page 54 – Figure 19. Token Ring — Ring Interface Timing
  • Page 55 – Figure 20. Skew and Asymmetry from RCLK or PXTALIN to DRVR and DRVR
  • Page 56 – Figure 21. Ethernet Timing Of Clock Signals; ethernet timing of XMIT signals; Figure 22. Ethernet Timing of XMIT Signals
  • Page 57 – Figure 23. Ethernet Timing of RCV Signals — Start Of Frame
  • Page 58 – Figure 24. Ethernet Timing of RCV Signals — End Of Frame
  • Page 59 – Figure 25. Ethernet Timing of RCV Signals — No RXC; Figure 26. Ethernet Timing of XMIT Signals
  • Page 60 – Figure 27. Ethernet Timing of XMIT Signals
  • Page 65 – Figure 30. 80x8x Interrupt Acknowledge Timing – First SIACK Pulse; 0x8x interrupt acknowledge timing – second SIACK pulse
  • Page 66 – Figure 31. 80x8x Interrupt Acknowledge Timing – Second SIACK Pulse
  • Page 68 – Figure 32. 80x8x Mode Bus Arbitration Timing, SIF Takes Control
  • Page 70 – Figure 33. 80x8x Mode DMA Read Timing
  • Page 72 – Figure 34. 80x8x Mode DMA Write Timing
  • Page 73 – Figure 35. 80x8x Mode Bus Arbitration Timing, SIF Returns Control
  • Page 74 – Figure 36. 80x8x Mode Bus Release Timing
  • Page 76 – Figure 37. 68xxx DIO Read Timing
  • Page 78 – Figure 38. 68xxx DIO Write Timing
  • Page 80 – Figure 39. 68xxx Interrupt Acknowledge Cycle Timing
  • Page 82 – Figure 40. 68xxx Mode Bus Arbitration Timing, SIF Takes Control
  • Page 84 – Figure 41. 68xxx Mode DMA Read Timing
  • Page 86 – Figure 42. 68xxx Mode DMA Write Timing
  • Page 88 – Figure 43. 68xxx Mode Bus Arbitration Timing, SIF Returns Control
  • Page 89 – Figure 44. 68xxx Mode Bus Release and Error Timing
  • Page 90 – normal completion with delayed start†; rerun cycle with delayed start; Figure 45. 68xxx Bus Halt and Retry Cycle Waveforms
  • Page 91 – MECHANICAL DATA
  • Page 92 – IMPORTANT NOTICE; Copyright
Loading the manual

TMS380C26

NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

POST OFFICE BOX 1443

•

HOUSTON, TEXAS

77251–1443

Copyright

1993, Texas Instruments Incorporated

1

•

IEEE 802.5 and IBM Token-Ring Network
Compatible

•

IEEE 802.3 and Blue Book Ethernet
Network Compatible

•

Pin and Software Compatible With the
TMS380C16

•

Configurable Network Type and Speed:
– Selectable by Host Software Control

(Adapter Control Register)

– Selectable by Network Front-End
– Readable from Host (Adapter Control

Register)

•

Token-Ring Features
– 16- or 4-Megabit-per-Second Data Rates
– Supports up to 18K-Byte Frame Size

(16 Mbps Operation Only)

– Supports Universal and Local Network

Addressing

– Early Token Release Option (16 Mbps

Operation Only)

– Compatible With the TMS38054

•

Ethernet Features
– 10-Megabit-per-Second Data Rate
– Compatible With Most Ethernet Serial

Network Interface Devices

– Full Duplex Ethernet Operation Allows

Network Speed Self-test

•

Expandable Local LAN Subsystem Memory
Space up to 2 Megabytes

•

Supports Multicast Addressing of Network
Group Addresses Through Hashing

•

Glueless Interface to DRAMs

•

High-Performance 16-Bit CPU for
Communications Protocol Processing

•

Up to 8 Megabyte-per-Second High-Speed
Bus Master DMA Interface

•

Low-Cost Host-Slave I/O Interface Option

•

Up to 32-Bit Host Address Bus

•

Selectable Host System Bus Options

•

80x8x or 68xxx-Type Bus and Memory
Organization
– 8- or 16-Bit Data Bus on 80x8x Buses
– Optional Parity Checking

•

Dual-Port DMA and Direct I/O Transfers to
Host Bus

•

Specification for External Adapter-Bus
Devices (SEADs) Supports External
Hardware Interface for User-Defined
External Logic

•

Enhanced Address Copy Option (EACO)
Interface Supports External Address
Checking Logic for Bridging or External
Custom Applications

•

Support for Module High-Impedance
In-Circuit Testing

•

Built-in Real-Time Error Detection

•

Bring-Up and Self-Test Diagnostics With
Loopback

•

Automatic Frame Buffer Management

•

Slow-Clock Low-Power Mode

•

Single 5-V Supply

•

1-

µ

m CMOS Technology

•

250 mA Typical Latch-Up Immunity at 25

°

C

•

ESD Protection Exceeds 2,000 V

•

132-Pin JEDEC Plastic Quad Flat Package
(PQ Suffix)

•

Operating Temperature Range
0

°

C to 70

°

C

network commprocessor applications diagram

TMS380C26

Attached

System

Bus

LAN Subsystem

Memory

Token Ring or

Ethernet Physical

Layer Circuitry

Transmit

Receive

To
Network

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

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Summary

Page 2 - pinout

TMS380C26NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 2 pinout The pin assignments for TMS380C26 (132-pin quad flat-pack) are shown in Figure 1. 132-PIN QUAD FLAT PACK (TOP VIEW) VSSCMRASMWMCASMAX2MAX0MDDIRVDD2SYNCINOSCINVSS2MROMENMACS...

Page 3 - NETWORK COMMPROCESSOR; description

TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3 description The TMS380C26 is a single-chip network communications processor (commprocessor) that supports tokenring, or Ethernet Local Area Networks (LANs). Either token ring at ...

Page 4 - block diagram and signal descriptions; Figure 2. TMS380C26 COMMprocessor Block Diagram

TMS380C26NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 4 block diagram and signal descriptions TMS380C26 has a bus interface to the host system, a bus interface to local memory, and an interface to thephysical layer circuitry. As a rule...

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