Texas Instruments TMS380C26 - Manuals

Page 2 - pinout

TMS380C26NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 2 pinout The pin assignments for TMS380C26 (132-pin quad flat-pack) are shown in Figure 1. 132-PIN QUAD FLAT PACK (TOP VIEW) VSSCMRASMWMCASMAX2MAX0MDDIRVDD2SYNCINOSCINVSS2MROMENMACS...

Page 3 - NETWORK COMMPROCESSOR; description

TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3 description The TMS380C26 is a single-chip network communications processor (commprocessor) that supports tokenring, or Ethernet Local Area Networks (LANs). Either token ring at ...

Page 4 - block diagram and signal descriptions; Figure 2. TMS380C26 COMMprocessor Block Diagram

TMS380C26NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 4 block diagram and signal descriptions TMS380C26 has a bus interface to the host system, a bus interface to local memory, and an interface to thephysical layer circuitry. As a rule...

Page 5 - Terminal Functions

TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 5 Terminal Functions PIN NAME NO. I/O DESCRIPTION BTSTRP 23 IN Bootstrap. The value on this pin is loaded into the BOOT bit of the SIFACL register at reset (i.e., whenthe SRESET pi...

Page 20 - architecture; local memory. Available protocols include:

TMS380C26NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 20 architecture The major blocks of the TMS380C26 include the Communications Processor (CP), System Interface (SIF),Memory Interface (MIF), Protocol Handler (PH), Clock Generator (C...

Page 23 - Adapter-Internal Pointers

TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 23 Adapter-Internal Pointers for Token-Ring † ADDRESS DESCRIPTION >00.FFF8‡ Pointer to software raw microcode level in chapter 0. >00.FFFA‡ Pointer to starting location of co...

Page 24 - for Ethernet

TMS380C26NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 24 Adapter-Internal Pointers for Ethernet † ADDRESS DESCRIPTION >00.FFF8‡ Software raw microcode level in chapter 0. >00.FFFA‡ Pointer to starting location of copyright notice...

Page 25 - User-Access Hardware Registers

TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 25 User-Access Hardware Registers 808x 16-Bit Mode: (SI/M = 1, S8/SHALT = 0) † Word Transfers Normal Mode SBHE = 0 SRS2 = 0 Pseudo-DMA Mode Active SBHE = 0 SRS2 = 0 Byte Transfers ...

Page 26 - SWDDIR — Current SDDIR Signal Value; Pseudo-DMA from host system to TMS380C26.

TMS380C26NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 26 SIF Adapter Control Register (SIFACL) The SIFACL register allows the host processor to control and to some extent reconfigure theTMS380C26 under software control. SIFACL Register...

Page 27 - SWHRQ — Current SHRQ Signal Value

TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 27 Bit 6: SWHRQ — Current SHRQ Signal Value This bit contains the current value on the SHRQ/SBRQ pin when in Intel mode, and the inverseof the SHRQ/SBRQ pin when in Motorola mode. ...

Page 28 - SINTEN — System-Interrupt Enable; PEN — Adapter Parity Enable

TMS380C26NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 28 Bit 12: SINTEN — System-Interrupt Enable This bit allows the host processor to enable or disable system interrupt requests from theTMS380C26. The system interrupt request from th...

Page 29 - SIFACL Control for Pseudo-DMA Operation; Figure 3. Pseudo-DMA Logic Related to SIFACL Bits

TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 29 SIFACL Control for Pseudo-DMA Operation Pseudo-DMA is software controlled by the use of five bits in the SIFACL register. The logic model for the SIFACLregister control of pseud...

Page 30 - Supply voltage range, V; DD; Output voltage range; recommended operating conditions

TMS380C26NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 30 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) † Supply voltage range, V DD (see Note 6) 7 V . . . . . . . . . . . . . . . . . . . . ...

Page 31 - PARAMETER MEASUREMENT INFORMATION; OL; V typical timing verification; Figure 4. Test Load Circuit

TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 31 PARAMETER MEASUREMENT INFORMATION Outputs are driven to a minimum high-logic level of 2.4 volts and to a maximum low-logic level of 0.6 volts. Theselevels are compatible with TT...

Page 32 - Figure 5. Clock Waveforms After Clock Stabilization

TMS380C26NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 32 PARAMETER MEASUREMENT INFORMATION OSCIN OSCOUT MBCLK1† MBCLK2† 4 Periods 8 Periods 12 Periods 16 Periods 20 Periods WhenCLKDIV = 1 Reference † The MBCLK1 and MBCLK2 signals have ...

Page 33 - timing parameter symbology; Lower case subscripts are defined as follows:

TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 33 PARAMETER MEASUREMENT INFORMATION timing parameters The timing parameters for all the pins of TMS380C26 are shown in the following tables and are illustrated in theaccompanying ...

Page 43 - Figure 10. Memory Bus Timing: Write Cycle

TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 43 PARAMETER MEASUREMENT INFORMATION Data/Parity Out ADD/STS Address Address Enable Address/ MDDIR MBEN MW MCAS MRAS MAXPH, MAXPL,MADH0–MADH7, MADL0–MADL7 MAX0,MAX2, MROMEN 60 63 6...

Page 44 - Figure 11. Memory Bus Timing: TMS380C26 Releases Control of Bus

TMS380C26NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 44 PARAMETER MEASUREMENT INFORMATION memory bus timing: TMS380C26 releases control of bus t M is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum) NO. PARAMETE...

Page 47 - Figure 13. Memory Bus Timing: TMS380C26 Resumes Control of Bus

TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 47 PARAMETER MEASUREMENT INFORMATION 80 79 80 79 80 79 80 79 80 79 80 79 MBCLK1 MAX0,MAX2, MOROMEN MAXPH, MAXPL, MADH0–MADH7, MADL0–MADL7 MRAS MCAS MW MOE Figure 13. Memory Bus Tim...

Page 52 - Figure 17. Memory Bus Timing: DRAM Refresh Cycle

TMS380C26NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 52 PARAMETER MEASUREMENT INFORMATION memory bus timing: DRAM refresh timing t M is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum) NO. PARAMETER MIN MAX UNIT...

Page 53 - Figure 18. XMATCH and XFAIL Timing

TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 53 PARAMETER MEASUREMENT INFORMATION XMATCH and XFAIL timing t M is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum) NO. PARAMETER MIN MAX UNIT 127 Delay fro...

Page 54 - Figure 19. Token Ring — Ring Interface Timing

TMS380C26NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 54 PARAMETER MEASUREMENT INFORMATION token ring — ring interface timing No. PARAMETER MIN TYP MAX UNIT 153 Period of RCLK (see Note 14) 4Mbps 125 ns 153 Period of RCLK (see Note 14)...

Page 55 - Figure 20. Skew and Asymmetry from RCLK or PXTALIN to DRVR and DRVR

TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 55 PARAMETER MEASUREMENT INFORMATION token ring — transmitter timing (see Figure 20) NO. PARAMETER MIN TYP MAX UNIT 159 Delay from DRVR rising edge (1.8 V) to DRVR falling edge (1....

Page 56 - Figure 21. Ethernet Timing Of Clock Signals; ethernet timing of XMIT signals; Figure 22. Ethernet Timing of XMIT Signals

TMS380C26NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 56 PARAMETER MEASUREMENT INFORMATION ethernet timing of clock signals NO. PARAMETER MIN TYP MAX UNIT 300 CLKPHS Pulse duration of TXC 45 ns 301 CLKPER Cycle time of TXC 95 1000 ns T...

Page 57 - Figure 23. Ethernet Timing of RCV Signals — Start Of Frame

TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 57 PARAMETER MEASUREMENT INFORMATION ethernet timing of RCV signals — start of frame NO. PARAMETER MIN TYP MAX UNIT 310 RXDSET Setup of RXD before RXC no longer low 20 ns 311 RXDHL...

Page 58 - Figure 24. Ethernet Timing of RCV Signals — End Of Frame

TMS380C26NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 58 PARAMETER MEASUREMENT INFORMATION ethernet timing of RCV signals — end of frame NO. PARAMETER MIN TYP MAX UNIT 320 CRSSET Setup time of CRS low before RXC no longer low to determ...

Page 59 - Figure 25. Ethernet Timing of RCV Signals — No RXC; Figure 26. Ethernet Timing of XMIT Signals

TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 59 PARAMETER MEASUREMENT INFORMATION ethernet timing of RCV signals — no RXC NO. PARAMETER MIN TYP MAX UNIT 330 NORXC Time with no clock pulse on RXC, when CRS is high (see Note 19...

Page 60 - Figure 27. Ethernet Timing of XMIT Signals

TMS380C26NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 60 PARAMETER MEASUREMENT INFORMATION ethernet timing of XMIT signals NO. PARAMETER MIN TYP MAX UNIT 350 JAMTIM Time from COLL sampled high (TXC high) to first transmitted ”JAM” bit ...

Page 65 - Figure 30. 80x8x Interrupt Acknowledge Timing – First SIACK Pulse; 0x8x interrupt acknowledge timing – second SIACK pulse

TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 65 PARAMETER MEASUREMENT INFORMATION 80x8x interrupt acknowledge timing – first SIACK pulse NO. PARAMETER MIN MAX UNIT 286 Pulse duration, SIACK high between DIO accesses (see Note...

Page 66 - Figure 31. 80x8x Interrupt Acknowledge Timing – Second SIACK Pulse

TMS380C26NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 66 PARAMETER MEASUREMENT INFORMATION SADH0–SADH7, SADL0–SADL7, SPH, SPL (see Note A) SRDY† SDBEN SDDIR SRD SWR SIACK SCS, SRSX, SRS0–SRS2, SBHE Only SCS needs to be inactive. All ot...

Page 68 - Figure 32. 80x8x Mode Bus Arbitration Timing, SIF Takes Control

TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 68 POST OFFICE BOX 1443 HOUST ON, TEXAS 77001 • PARAMETER MEASUREMENT INFORMATION SOWN (see Note A) SDDIR SADH0–SADH7, SADL0–SADL7, SPH, SPL SBHE SRD, SWR SHRQ SIF Outputs: SBBSY, SHLDA SBCLK SIF Inputs: SIF Master Bus Exchange U...

Page 70 - Figure 33. 80x8x Mode DMA Read Timing

TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 70 POST OFFICE BOX 1443 HOUST ON, TEXAS 77001 • PARAMETER MEASUREMENT INFORMATION 214 Address Data Address ExtendedAddress Valid Low (High) SDDIR SDBEN (see Note A) SRDY SADH0–SADH7, SADL0–SADL7, SPH, SPL (see Note C) SALE SXAL S...

Page 72 - Figure 34. 80x8x Mode DMA Write Timing

TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 72 POST OFFICE BOX 1443 HOUST ON, TEXAS 77001 • PARAMETER MEASUREMENT INFORMATION 218 SDDIR SDBEN SRDY SADL0–SADH7,SADH0–SADL7, SPH, SPL (see Note B) SALE SXAL SWR SRD SBHE (see Note A) SBCLK TWAIT V T1 T4 T3 T2 T1 TX T4 208b 208...

Page 73 - Figure 35. 80x8x Mode Bus Arbitration Timing, SIF Returns Control

TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 73 PARAMETER MEASUREMENT INFORMATION 80x8x mode bus arbitration timing, SIF returns control NO. PARAMETER MIN MAX UNIT 220† Delay from SBCLK low in I1 cycle to SADH0–SADH7, SADL0–S...

Page 74 - Figure 36. 80x8x Mode Bus Release Timing

TMS380C26NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 74 PARAMETER MEASUREMENT INFORMATION 80x8x mode bus release timing NO. PARAMETER MIN MAX UNIT 208a Setup of asynchronous input SBRLS low before SBCLK no longer high to guarantee rec...

Page 76 - Figure 37. 68xxx DIO Read Timing

TMS380C26NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 76 PARAMETER MEASUREMENT INFORMATION (High) Valid Output Data Valid SADH0–SADH7, SADL0–SADL7, SPH, SPL SDTACK† SDBEN SDDIR SUDS, SLDS SRNW SIACK SCS, SRSX, SRS0, SRS1 260 282a 275 2...

Page 78 - Figure 38. 68xxx DIO Write Timing

TMS380C26NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 78 PARAMETER MEASUREMENT INFORMATION SADH0–SADH7, SADL0–SADL7, SPH, SPL SDTACK† SDBEN‡ SDDIR SUDS, SLDS (see Note A) SRNW SIACK SCS SRSX, SRS0, SRS1 HI-Z HI-Z HI-Z HI-Z (High) Valid...

Page 80 - Figure 39. 68xxx Interrupt Acknowledge Cycle Timing

TMS380C26NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 80 PARAMETER MEASUREMENT INFORMATION Output Data Valid (High) Only SCS needs to be Inactive. All Others are Don’t Care. SADH0–SADH7, SADL0–SADL7, SPH, SPL (see Note A) SDTACK† SDBEN...

Page 82 - Figure 40. 68xxx Mode Bus Arbitration Timing, SIF Takes Control

TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 82 POST OFFICE BOX 1443 HOUST ON, TEXAS 77001 • PARAMETER MEASUREMENT INFORMATION SOWN (see Note B) SDDIR SADH0–SADH7, SADL0–SADL7, SPH, SPL SRNW SAS, SLDS, SUDS SBRQ (see Note A) SIF Outputs: SBERR, SDTACK, SBBSY SBGR SBCLK SIF ...

Page 84 - Figure 41. 68xxx Mode DMA Read Timing

TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 84 POST OFFICE BOX 1443 HOUST ON, TEXAS 77001 • PARAMETER MEASUREMENT INFORMATION SALE SDBEN (see Note A) SDDIR SDTACK (see Notes B and C) SADL0–SADH7,SADH0–SADL7, SPH, SPL SXAL SRNW SUDS, SLDS SAS (see Note A) SBCLK HI-Z Data In...

Page 86 - Figure 42. 68xxx Mode DMA Write Timing

TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 86 POST OFFICE BOX 1443 HOUST ON, TEXAS 77001 • PARAMETER MEASUREMENT INFORMATION 233a 211a TWAIT V T1 T4 T3 T2 T1 TX T4 SDBEN SDDIR SDTACK (see Notes A and B) SADL0–SADH7,SADH0–SADL7, SPL, SPH SALE SXAL SRNW SUDS, SLDS SAS SBCLK...

Page 88 - Figure 43. 68xxx Mode Bus Arbitration Timing, SIF Returns Control

TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 88 POST OFFICE BOX 1443 HOUST ON, TEXAS 77001 • PARAMETER MEASUREMENT INFORMATION User Bus Exchange SIF Master T1 I2 I1 T4 T3 T2 SOWN SDDIR SADH0–SADH7, SADL0–SADL7, SPH, SPL SRNW SAS, SUDS, SLDS SBRQ (see Note A) SIF Outputs: SD...

Page 89 - Figure 44. 68xxx Mode Bus Release and Error Timing

TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 89 PARAMETER MEASUREMENT INFORMATION 68xxx mode bus release and error timing NO. PARAMETER MIN MAX UNIT 208a Setup of asynchronous input before SBCLK no longer high to guarantee re...

Page 90 - normal completion with delayed start†; rerun cycle with delayed start; Figure 45. 68xxx Bus Halt and Retry Cycle Waveforms

TMS380C26NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 90 PARAMETER MEASUREMENT INFORMATION normal completion with delayed start† SBCLK T1 T(W or 2) T3 T4 SDTACK SBERR SHALT TH T1 rerun cycle with delayed start † SBCLK T1 T2 T3 T4 THB T...

Page 91 - MECHANICAL DATA

TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 91 MECHANICAL DATA JEDEC plastic leaded quad flat package (PQ suffix) Each of these chip carrier packages consists of a circuit mounted on a lead frame and encapsulated within anel...

Page 92 - IMPORTANT NOTICE; Copyright

IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinueany product or service without notice, and advise customers to obtain the latest version of relevant informationto verify, before placing orders, that information being r...