Texas Instruments TMS320TCI648x - Manual

Texas Instruments TMS320TCI648x

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Table of Contents:

  • Page 3 – Contents
  • Page 5 – Index
  • Page 14 – Read This First; About This Manual; SPRAAB0
  • Page 15 – Related Documentation From Texas Instruments; Trademarks; RapidIO is a registered trademark of RapidIO Trade Association.
  • Page 16 – Overview; General RapidIO System; RapidIO Architectural Hierarchy; Figure 1
  • Page 17 – Figure 1. RapidIO Architectural Hierarchy
  • Page 18 – Figure 2; Figure 2. RapidIO Interconnect Architecture; Figure 3
  • Page 19 – RapidIO Feature Support in SRIO; Figure 3. Serial RapidIO Device to Device Interface Diagrams; RapidIO Interconnect Specification V1.2 compliance, Errata 1.2
  • Page 20 – Features Not Supported:; Compliance with the Global Shared Memory specification (GSM); Table 1. TI Devices Supported By This Document
  • Page 21 – Peripheral Data Flow; SRIO Functional Description; Table 2. Registers Checked for Multicast DeviceID; Registers Checked For Multicast DeviceID; Figure 4
  • Page 22 – SRIO Packets; Operation Sequence; Figure 4. SRIO Peripheral Block Diagram
  • Page 23 – Example Packet – Streaming Write; Figure 5; Figure 5. Operation Sequence; An example packet is shown as two data streams in
  • Page 24 – Control Symbols; Figure 7; Figure 7. Serial RapidIO Control Symbol Format
  • Page 25 – SRIO Packet Type; SRIO Pins; details the handling of such packets.; Table 3. Packet Types; Ftype; Table 4
  • Page 26 – Functional Operation; Component Block Diagram; Table 4. Pin Description; Figure 8
  • Page 27 – Figure 8. SRIO Component Block Diagram
  • Page 28 – SERDES Macro and its Configurations; Enabling the PLL; Figure 9
  • Page 29 – Bit; Table 6
  • Page 30 – Enabling the Receiver; Table 6. Line Rate versus PLL Output Clock Frequency; Table 7; Table 7. Effect of the RATE Bits; Table 8; Table 8. Frequency Range versus MPY Value; and described in
  • Page 31 – Descriptions
  • Page 33 – Enabling the Transmitter; shows the fields of SERDES_CFGTXn_CNTL and
  • Page 35 – SERDES Configuration Example; SWING Bits
  • Page 36 – and; Table 14. LSU Control/Command Register Fields; LSU Register Field
  • Page 37 – Table 15. LSU Status Register Fields
  • Page 38 – Figure 13. LSU Registers Timing
  • Page 39 – Detailed Data Path Description; illustrates the
  • Page 40 – Direct I/O TX Operation; Figure 15. Load/Store Module Data Flow Diagram
  • Page 42 – Direct I/O RX Operation
  • Page 43 – Reset and Power Down State; Message Passing; So the general flow is as follows:
  • Page 44 – RX Operation; illustrates the scheme.; Figure 16. CPPI RX Scheme for RapidIO; shows the packet
  • Page 45 – Figure 17. Message Request Packet; . A detailed summary of
  • Page 46 – Figure 18. Mailbox to Queue Mapping Register Pair
  • Page 47 – shows the RX buffer descriptor fields and; Figure 19. RX Buffer Descriptor Fields; Field
  • Page 48 – Table 18. RX Buffer Descriptor Field Descriptions (continued)
  • Page 49 – . This scenario is similar; Figure 20. RX CPPI Mode Explanation
  • Page 50 – Teardown of an RX queue causes the following actions:
  • Page 51 – TX Operation; Figure 21. CPPI Boundary Diagram
  • Page 52 – Figure 22. TX Buffer Descriptor Fields
  • Page 54 – . This scheme allows configurability of the queue
  • Page 56 – Field Pair
  • Page 59 – No new messages will be sent.
  • Page 60 – Message Passing Software Requirements
  • Page 61 – Initialization Example
  • Page 62 – Figure 24. RX Buffer Descriptors
  • Page 63 – Figure 25. TX Buffer Descriptors; The doorbell operation is shown in
  • Page 64 – Figure 26. Doorbell Operation
  • Page 65 – Table 3
  • Page 66 – Detailed Description; HOL blocking is undesired, but allowable for TX CPPI queues
  • Page 67 – illustrates the registers that contain the flow masks, and; Figure 28. Transmit Source Flow Control Masks
  • Page 68 – Endianness; Table 25. Fields Within Each Flow Mask; Figure 6
  • Page 69 – Translation for MMR space; Figure 30. Configuration Bus Example
  • Page 70 – Reset and Power Down; Table 26. Reset Hierarchy; Bus
  • Page 72 – The 18 block-specific registers are represented by
  • Page 73 – Table 28. Block Enable and Block Enable Status Field Descriptions
  • Page 74 – Software Shutdown Details; Emulation; Table 29. Peripheral Control Register (PCR) Field Descriptions
  • Page 75 – TX Buffers, Credit, and Packet Reordering; Multiple Ports With 1x Operation
  • Page 77 – Enabling the SRIO Peripheral; Table 30. Port Mode Register Settings; Device
  • Page 78 – Peripheral Initializations; Set Device ID Registers
  • Page 79 – Bootload Capability; Configuration and Operation; Assert the PEREN bit to enable logical layer data flow; internal ROM code to initialize SRIO.
  • Page 80 – Figure 41. Bootload Operation; Section 4
  • Page 81 – Table 31. Multicast DeviceID Operation; . If the packet’s DestID doesn’t match either, the
  • Page 83 – Logical/Transport Error Handling and Logging; names the functional
  • Page 85 – CPU Interrupts; Interrupt Conditions; The following interrupts are supported by the RIO peripheral.; Figure 45. RapidIO DOORBELL Packet for Interrupt Use
  • Page 86 – Interrupt Condition Status and Clear Registers
  • Page 87 – Doorbell Interrupt Condition Status and Clear Registers; Table 35. Interrupt Condition Status and Clear Bits; through
  • Page 88 – CPPI Interrupt Condition Status and Clear Registers; The ICSRs and the ICCRs for the RXU and the TXU are shown in
  • Page 89 – LSU Interrupt Condition Status and Clear Registers; Figure 50. RX CPPI Interrupt Condition Status and Clear Registers; Figure 51. TX CPPI Interrupt Condition Status and Clear Registers; The ICSR and the ICCR for the LSUs are shown in
  • Page 90 – Figure 52. LSU Interrupt Condition Status and Clear Registers
  • Page 91 – The ICSR and the ICCR for the SRIO ports are shown in
  • Page 92 – Interrupt Function; Step; Step
  • Page 93 – Interrupt Condition Routing Registers; Doorbell Interrupt Condition Routing Registers; Table 39. Interrupt Condition Routing Options; same bit field map, with the following addresses:
  • Page 94 – CPPI Interrupt Condition Routing Registers; Figure 54. Doorbell 0 Interrupt Condition Routing Registers; shows the ICRRs for the RXU, and; Figure 55. RX CPPI Interrupt Condition Routing Registers
  • Page 95 – LSU Interrupt Condition Routing Registers; Figure 56. TX CPPI Interrupt Condition Routing Registers
  • Page 96 – Figure 57. LSU Interrupt Condition Routing Registers; The ICRRs shown in
  • Page 97 – Interrupt Status Decode Registers; shows which interrupt sources can be mapped to
  • Page 98 – . The doorbell interrupt sources can be mapped to bits 15–0.; Figure 60. Interrupt Sources Assigned to ISDR Bits; illustrates the decode routing for
  • Page 100 – Interrupt Handling
  • Page 102 – Introduction; SRIO Registers; Offset
  • Page 111 – The peripheral ID register (PID) is shown in
  • Page 112 – Table 42. Peripheral Control Register (PCR) Field Descriptions
  • Page 119 – shown in
  • Page 120 – . The general form for a block n enable status register
  • Page 122 – The RapidIO DEVICEID2 register (DEVICEID_REG2 is shown in
  • Page 126 – Low Freq Gain
  • Page 128 – There are four of these registers, to support four ports (see
  • Page 132 – The four doorbell interrupts are mapped to these registers (see
  • Page 133 – of a doorbell interrupt condition clear register is shown in
  • Page 144 – applies to an ICRx
  • Page 145 – Figure 88. RX CPPI Interrupt Condition Routing Registers
  • Page 146 – Figure 89. TX CPPI Interrupt Condition Routing Registers
  • Page 147 – shows the ICRRs for the LSU interrupt requests, and; Figure 90. LSU Interrupt Condition Routing Registers
  • Page 150 – Destinations
  • Page 155 – There are four of these registers, one for each LSU (see
  • Page 164 – There are sixteen of these registers (see
  • Page 169 – shows the registers, and; Register
  • Page 170 – Figure 108. Transmit CPPI Supported Flow Mask Registers; Table 114. TX Queue n FLOW_MASK Field Descriptions
  • Page 173 – . For additional programming information, see
  • Page 174 – . As part of this scheme, software must program the 16; Figure 112. Transmit CPPI Weighted Round Robin Control Registers
  • Page 177 – lists all of these; Mappers
  • Page 179 – Figure 113. Mailbox to Queue Mapping Register Pair
  • Page 200 – Each of the four ports is supported by a register of this type (see
  • Page 234 – , each of the registers captures one of the four 32-bit
  • Page 241 – rate counting enable field
Loading the manual

TMS320TCI648x Serial RapidIO (SRIO)

User's Guide

Literature Number: SPRUE13A

September 2006

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Summary

Page 3 - Contents

Contents Preface .............................................................................................................................. 14 1 Overview .................................................................................................................. 16 1.1 General RapidIO Syst...

Page 5 - Index

5.69 Port Link Maintenance Request CSR n (SPn_LM_REQ) ................................................ 200 5.70 Port Link Maintenance Response CSR n (SPn_LM_RESP) ............................................ 201 5.71 Port Local AckID Status CSR n (SPn_ACKID_STAT) .......................................

Page 14 - Read This First; About This Manual; SPRAAB0

Preface SPRUE13A – September 2006 Read This First About This Manual This document describes the Serial RapidIO ® (SRIO) peripheral on the TMS320TCI648x™ devices. Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the f...

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