Page 3 - Contents
Contents Preface .............................................................................................................................. 14 1 Overview .................................................................................................................. 16 1.1 General RapidIO Syst...
Page 5 - Index
5.69 Port Link Maintenance Request CSR n (SPn_LM_REQ) ................................................ 200 5.70 Port Link Maintenance Response CSR n (SPn_LM_RESP) ............................................ 201 5.71 Port Local AckID Status CSR n (SPn_ACKID_STAT) .......................................
Page 14 - Read This First; About This Manual; SPRAAB0
Preface SPRUE13A – September 2006 Read This First About This Manual This document describes the Serial RapidIO ® (SRIO) peripheral on the TMS320TCI648x™ devices. Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the f...
Page 15 - Related Documentation From Texas Instruments; Trademarks; RapidIO is a registered trademark of RapidIO Trade Association.
www.ti.com Related Documentation From Texas Instruments Trademarks TMS320TCI648x, C6000, TMS320C62x, TMS320C67x, TMS320C6000, Code Composer Studio aretrademarks of Texas Instruments. RapidIO is a registered trademark of RapidIO Trade Association. InfiniBand is a trademark of the InfiniBand Trade Ass...
Page 16 - Overview; General RapidIO System; RapidIO Architectural Hierarchy; Figure 1
1 Overview 1.1 General RapidIO System 1.1.1 RapidIO Architectural Hierarchy User's Guide SPRUE13A – September 2006 Serial RapidIO (SRIO) The RapidIO peripheral used in the TMS320TCI648x is called a serial RapidIO (SRIO). This chapterdescribes the general operation of a RapidIO system, how this modul...
Page 17 - Figure 1. RapidIO Architectural Hierarchy
www.ti.com Globally shared memory spec logical Future Message passing system I/O Logical specification Information necessary for the end pointto process the transaction (i.e., transactiontype, size, physical address) to end in the system (i.e., routing address) Information to transport packet from e...
Page 18 - Figure 2; Figure 2. RapidIO Interconnect Architecture; Figure 3
www.ti.com 1.1.2 RapidIO Interconnect Architecture Host Subsystem I/O Control Subsystem DSP Farm TDM,GMII, Utopia Communications Subsystem PCI Subsystem InfiniBand HCA ™ To System Area Network Memory Memory Memory Memory RapidIO RapidIO RapidIO RapidIO RapidIO Backplane PCI RapidIO RapidIO RapidIO R...
Page 19 - RapidIO Feature Support in SRIO; Figure 3. Serial RapidIO Device to Device Interface Diagrams; RapidIO Interconnect Specification V1.2 compliance, Errata 1.2
www.ti.com Serial RapidIO 1x Device to 1x Device Interface Diagram Serial RapidIO 4x Device to 4x Device Interface Diagram 1x Device TD[0] TD[0] RD[0] RD[0] TD[0] TD[0] 1x Device RD[0] RD[0] RD[0-3] RD[0-3] 4x Device TD[0-3] RD[0-3] RD[0-3] TD[0-3] 4x Device TD[0-3] TD[0-3] 1.2 RapidIO Feature Suppo...
Page 20 - Features Not Supported:; Compliance with the Global Shared Memory specification (GSM); Table 1. TI Devices Supported By This Document
www.ti.com 1.3 Standards 1.4 External Devices Requirements 1.5 TI Devices Supported By This Document Overview Features Not Supported: • Compliance with the Global Shared Memory specification (GSM) • 8/16 LP-LVDS compatible • Destination support of RapidIO Atomic Operations • Simultaneous mixing of f...
Page 21 - Peripheral Data Flow; SRIO Functional Description; Table 2. Registers Checked for Multicast DeviceID; Registers Checked For Multicast DeviceID; Figure 4
www.ti.com 2 SRIO Functional Description 2.1 Overview 2.1.1 Peripheral Data Flow SRIO Functional Description This peripheral is designed to be an externally driven slave module that is capable of acting as a master inthe DSP system. This means that an external device can push (burst write) data to t...
Page 22 - SRIO Packets; Operation Sequence; Figure 4. SRIO Peripheral Block Diagram
www.ti.com 1.25 to 3.125 Gbps differential data RX Clock recovery S2P 10bClk 8b/10b decode 8b Clock recovery RX 8b 8b/10b decode 10bClk S2P Clock recovery RX 8b 8b/10b decode 10bClk S2P Clock recovery RX 8b 8b/10b decode 10bClk S2P PLL TX TX TX TX P2S P2S P2S P2S 8b 8b 8b 8b 10b 8b/10b coding Clk 8b...
Page 23 - Example Packet – Streaming Write; Figure 5; Figure 5. Operation Sequence; An example packet is shown as two data streams in
www.ti.com Initiator Request Packet Issued Operation Completed for Master Acknowledge Symbol Acknowledge Symbol Response Packet Forwarded Request Packet Forwarded Acknowledge Symbol Acknowledge Symbol Response Packet Issued Fabric Target Target Completes Operation OperationIssued By Master 2.1.2.2 E...
Page 24 - Control Symbols; Figure 7; Figure 7. Serial RapidIO Control Symbol Format
www.ti.com double-word 0 4 double-word n-1 acklD rsv prio tt ftype destID sourcelD address rsrv xamsbs double-word 1 ... double-word n-2 CRC PHY LOG TRA LOG TRA PHY 5 3 2 2 8 8 29 1 2 64 64 (n-4)*64 64 64 16 16 n*64+32 16 4 2 10 LOG PHY 10 TRA 2 4 9 * 6 4 + 32 LOG TRA 16 PHY 16 double-word 0 5 a c k...
Page 25 - SRIO Packet Type; SRIO Pins; details the handling of such packets.; Table 3. Packet Types; Ftype; Table 4
www.ti.com 2.1.2.4 SRIO Packet Type 2.2 SRIO Pins SRIO Functional Description The type of received packet determines how the packet routing is handled. Reserved or undefined packettypes are destroyed before being processed by the logical layer functional blocks. This prevents erroneousallocation of ...
Page 26 - Functional Operation; Component Block Diagram; Table 4. Pin Description; Figure 8
www.ti.com 2.3 Functional Operation 2.3.1 Component Block Diagram SRIO Functional Description Table 4. Pin Description Pin Signal Pin Name Count Direction Description RIOTX3/ RIOTX3 2 Output Transmit Data – Differential point-to-point unidirectional bus. Transmitspacket data to a receiving device’s ...
Page 27 - Figure 8. SRIO Component Block Diagram
www.ti.com Port 0 8 x 276 TX 8 x 276 RX 8 x 276 RX 8 x 276 TX Port 1 8 x 276 TX 8 x 276 RX Port 2 8 x 276 RX 8 x 276 TX Port 3 Physicallayerbuffers SERDES 0 SERDES 1 SERDES 2 SERDES 3 SERDESdifferentialsignals 4x mode data path TX buffering 32 x 276B 8 buffers per 1X port - all priorities 32 buffers...
Page 28 - SERDES Macro and its Configurations; Enabling the PLL; Figure 9
www.ti.com 2.3.2 SERDES Macro and its Configurations 2.3.2.1 Enabling the PLL SRIO Functional Description SRIO offers many benefits to customers by allowing a scalable non-proprietary interface. With the use ofTI’s SERDES macros, the peripheral is very adaptable and bandwidth scalable. The same peri...
Page 29 - Bit; Table 6
www.ti.com SRIO Functional Description Table 5. SERDES Macro Configuration Register 0 (SERDES_CFG0_CNTL) Field Descriptions Bit Field Value Description 31–10 Reserved 0000h Reserved 9–8 LB Loop bandwidth. Specify loop bandwidth settings. Jitter on the reference clock willdegrade both the transmit ey...
Page 30 - Enabling the Receiver; Table 6. Line Rate versus PLL Output Clock Frequency; Table 7; Table 7. Effect of the RATE Bits; Table 8; Table 8. Frequency Range versus MPY Value; and described in
www.ti.com 2.3.2.2 Enabling the Receiver SRIO Functional Description Table 6. Line Rate versus PLL Output Clock Frequency Rate Line Rate PLL Output Frequency RATESCALE Full x Gbps 0.5x GHz 0.5 Half x Gbps x GHz 1 Quarter x Gbps 2x GHz 2 RIOCLK and RIOCLK FREQ = LINERATE × RATESCALE MPY The rate is d...
Page 31 - Descriptions
www.ti.com SRIO Functional Description The clock recovery algorithms listed in the CDR bits operate to adjust the clocks used to sample thereceived message so that the data samples are taken midway between data transitions. The second orderalgorithm can be optionally disabled, and both can be config...
Page 33 - Enabling the Transmitter; shows the fields of SERDES_CFGTXn_CNTL and
www.ti.com 2.3.2.3 Enabling the Transmitter SRIO Functional Description Table 9. SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL) Field Descriptions (continued) Bit Field Value Description 4–2 BUSWIDTH 000b Bus width. Always write 000b to this field, to indicate a 10-bit-wide par...
Page 35 - SERDES Configuration Example; SWING Bits
www.ti.com 2.3.2.4 SERDES Configuration Example 2.3.3 Direct I/O Operation SRIO Functional Description Table 13. SWING Bits of SERDES_CFGTXn_CNTL SWING Bits Amplitude (mV dfpp ) 000b 125 001b 250 010b 500 011b 625 100b 750 101b 1000 110b 1125 111b 1250 //full sample rate at 3.125 Gbps //SERDES refer...
Page 36 - and; Table 14. LSU Control/Command Register Fields; LSU Register Field
www.ti.com LSU _REG0 n RapidIO Address MSB Control 31 RapidIO Address LSB/Config_offset Control 31 0 LSU _REG1 n DSP Address Control 31 0 LSU _REG2 n RSV Control 31 0 LSU _REG3 n 12 11 Byte_count OutPortID Control 31 0 LSU _REG4 n 1 7 Interrupt Req 30 Priority 29 28 xambs 27 26 ID Size 25 24 DestID ...
Page 37 - Table 15. LSU Status Register Fields
www.ti.com SRIO Functional Description Table 14. LSU Control/Command Register Fields (continued) LSU Register Field RapidIO Packet Header Field DestID RapidIO destinationID field specifying the target device. Packet Type 4 MSBs: 4-bit ftype field for all packets 4 LSBs: 4-bit trans field for packet ...
Page 38 - Figure 13. LSU Registers Timing
www.ti.com LSU _REG1 n T0 T1 T2 T3 T4 T5 Tn Valid LSU _REG2 n Valid LSU _REG3 n Valid LSU _REG4 n Valid LSU _REG5 n Valid Rdy/BSY Completion Valid Valid After Transaction Completes SRIO Functional Description Figure 13. LSU Registers Timing The following code illustrates an LSU registers programming...
Page 39 - Detailed Data Path Description; illustrates the
www.ti.com Source Address DMA Read Destination Address Count Byte Count DSP Address RSV Interrupt Req 0 0 1 7 23 8 DestID 25 24 ID Size 27 26 xambs 29 28 Priority OutPortID 31 30 Hop Count Drbll 31 16 15 Packet 8 7 0 RapioIO Address/Config_offset NodeID CRC 16 Count*8 payload 2 xamsbs 1 wr ptr 29 ad...
Page 40 - Direct I/O TX Operation; Figure 15. Load/Store Module Data Flow Diagram
www.ti.com LSU2 LSU4 LSU3 LSU1 MMR command UDI Load/Store module RapidIO transport and physical layers Port x transmission FIFO queues TX FIFO RX FIFO Peripheral boundary Config bus access Write transfer descriptors CPU I/O pins L2 memory = Shared resource for CPPI and MAU Shared TX buffer Shared RX...
Page 42 - Direct I/O RX Operation
www.ti.com 2.3.3.3 Direct I/O RX Operation SRIO Functional Description Segmentation: The LSU handles two types of segmentation of outbound requests. The first type is when the Byte_Countof Read/Write requests exceeds 256 bytes (up to 4K bytes). The second type is when Read/Write requestRapidIO addre...
Page 43 - Reset and Power Down State; Message Passing; So the general flow is as follows:
www.ti.com 2.3.3.4 Reset and Power Down State 2.3.4 Message Passing SRIO Functional Description So the general flow is as follows: • Previously, the control/command registers were written and the request packet was sent • Response Packet Type13, Trans != 0001b arrives at module interface, and is han...
Page 44 - RX Operation; illustrates the scheme.; Figure 16. CPPI RX Scheme for RapidIO; shows the packet
www.ti.com 2.3.4.1 RX Operation Mailbox 1...64 from RapidIO packet Header - Received on any input port Mailbox mapper Q15 Q2 Q1 Q0 Queue assignable to any core Packetsequence Message n A Packet manager n+1 B n+2 B n + 3 C n+4 D n+5 B n+6 E Buffer descriptor queues: Descriptor per message All priorit...
Page 45 - Figure 17. Message Request Packet; . A detailed summary of
www.ti.com acklD rsv prio tt ftype ftype = 1011 destID sourcelD msglen ssize msgseg/xmbox double-word 0 double-word 1 ... double-word n-2 double-word n-1 CRC PHY LOG TRA LOG TRA PHY 5 3 2 2 4 8 8 4 4 4 64 64 (n-4)*64 64 64 16 16 n*64+16 16 4 2 10 n*64+64 letter 2 mbox 2 SRIO Functional Description F...
Page 46 - Figure 18. Mailbox to Queue Mapping Register Pair
www.ti.com SRIO Functional Description Figure 18. Mailbox to Queue Mapping Register Pair Mailbox to Queue Mapping Register L n (RXU_MAP_L n ) 31 30 29 24 23 22 21 16 LETTER_MASK MAILBOX_MASK LETTER MAILBOX R/W-11 R/W-111111 R/W-00 R/W-000000 15 0 SOURCEID R/W-0000h Mailbox to Queue Mapping Register ...
Page 47 - shows the RX buffer descriptor fields and; Figure 19. RX Buffer Descriptor Fields; Field
www.ti.com 31 0 1 2 15 23 7 27 11 19 3 29 o w ne r sh i p t ea r do w n eop eoq sop 3 reserved cc message_length 13 21 5 25 9 17 1 30 14 22 6 26 10 18 2 28 12 20 4 24 8 16 0 Bit Fields next_descriptor_pointer buffer_pointer src_id pri tt reserved mailbox Word Offset SRIO Functional Description If a ...
Page 48 - Table 18. RX Buffer Descriptor Field Descriptions (continued)
www.ti.com SRIO Functional Description Table 18. RX Buffer Descriptor Field Descriptions (continued) Field Description ownership Ownership: Indicates ownership of the message and is valid only on sop. This bit is setby the DSP core and cleared by the port when the message has been transmitted. TheDS...
Page 49 - . This scenario is similar; Figure 20. RX CPPI Mode Explanation
www.ti.com Switch Switch Endpoint Endpoint C0 C0 B0 B0 B2 B2 A1 A1 B1 B1 A0 A0 Open Open Open Open Open Open Open Full Open Open Full Full Retry Retry Retry Retry Retry Retry Accept Retry Retry Retry Action Action Retry Retry Scenario A - Default Scenario B - In order mode Data flow destined for the...
Page 50 - Teardown of an RX queue causes the following actions:
www.ti.com SRIO Functional Description In addition, multiple messages can be interleaved at the receive port due to ordering within a connectedswitch’s output queue. This can occur when using a single or multiple priorities. The RX CPPI block canhandle simultaneous interleaved multi-segment messages...
Page 51 - TX Operation; Figure 21. CPPI Boundary Diagram
www.ti.com CPPI block CPU DMA Config bus access L2 memory Buffer descriptor dual-port SRAM (Nx20B) Data buffer Peripheral boundary 32 32 32 128 C P P I c o n t r o l r e g i s t e r s 2.3.4.2 TX Operation SRIO Functional Description Figure 21. CPPI Boundary Diagram Outgoing messages are handled simi...
Page 52 - Figure 22. TX Buffer Descriptor Fields
www.ti.com 31 0 1 2 15 23 7 27 11 19 3 29 o w ne r sh i p t ea r do w n eop eoq sop 3 reserved retry_count cc message_length 13 21 5 25 9 17 1 30 14 22 6 26 10 18 2 28 12 20 4 24 8 16 0 Bit Fields next_descriptor_pointer buffer_pointer dest_id pri tt ssize mailbox port_id Word Offset SRIO Functional...
Page 54 - . This scheme allows configurability of the queue
www.ti.com SRIO Functional Description Table 21. TX Buffer Descriptor Field Definitions (continued) Field Description ssize RIO standard message payload size. Indicates how the hardware should segment theoutgoing message by specifying the maximum number of double-words per packet. Ifthe message is a...
Page 56 - Field Pair
www.ti.com SRIO Functional Description Figure 23. Weighted Round Robin Programming Registers (Address Offset 7E0h–7ECh) TX_QUEUE_CNTL0 - Address Offset 7E0h <-------------------------------- TX_Queue_Map3 -----------------------------> <-------------------------------- TX_Queue_Map2 -------...
Page 59 - No new messages will be sent.
www.ti.com 2.3.4.3 Reset and Power Down State SRIO Functional Description A transaction timeout is used by all outgoing message and direct I/O packets. It has the same value and isanalogous to the request-to-response timer discussed in the RX CPPI and LSU sections, which is definedby the 24-bit valu...
Page 60 - Message Passing Software Requirements
www.ti.com 2.3.4.4 Message Passing Software Requirements SRIO Functional Description Software performs the following functions for messaging: RX Operation • Assigns Mailbox-to-queue mapping and allowable SourceIDs/mailbox- Queue Mapping • Sets up associated buffer descriptor memory – CPPI RAM or L2 ...
Page 61 - Initialization Example
www.ti.com SRIO Functional Description Initialization Example SRIO_REGS->Queue0_RXDMA_HDP = 0 ; SRIO_REGS->Queue1_RXDMA_HDP = 0 ; SRIO_REGS->Queue2_RXDMA_HDP = 0 ; SRIO_REGS->Queue3_RXDMA_HDP = 0 ; SRIO_REGS->Queue4_RXDMA_HDP = 0 ; SRIO_REGS->Queue5_RXDMA_HDP = 0 ; SRIO_REGS->Qu...
Page 62 - Figure 24. RX Buffer Descriptors
www.ti.com Descriptor Descriptor Buffer Buffer Port RX DMA state RX queue head descriptor pointer SRIO Functional Description Figure 24. RX Buffer Descriptors TX Buffer Descriptor TX_DESCP0_0->TXDESC0 = CSL_FMK( SRIO_TXDESC0_N_POINTER,(int )TX_DESCP0_1 ); //link to TX_DESCP0_1 TX_DESCP0_0->TXD...
Page 63 - Figure 25. TX Buffer Descriptors; The doorbell operation is shown in
www.ti.com Descriptor Descriptor Buffer Buffer Port TX DMA state TX queue head descriptor pointer 2.3.5 Maintenance 2.3.6 Doorbell Operation SRIO Functional Description Figure 25. TX Buffer Descriptors Start Message Passing SRIO_REGS->Queue0_RXDMA_HDP = (int )RX_DESCP0_0 ; SRIO_REGS->Queue0_TX...
Page 64 - Figure 26. Doorbell Operation
www.ti.com acklD rsv prio tt 1010 destID sourcelD Reserved srcTID Reserved Doorbell Reg # rsv Doorbell bit CRC PHY LOG TRA LOG TRA PHY 5 3 2 2 4 8 8 8 8 9 2 1 4 16 16 32 16 4 2 10 info (msb) 8 info (lsb) 8 SRIO Functional Description for any desired purpose; see the RapidIO Interconnect Specificatio...
Page 65 - Table 3
www.ti.com 2.3.7 Atomic Operations 2.3.8 Congestion Control SRIO Functional Description SRIO_REGS->LSU1_REG0 = CSL_FMK( SRIO_LSU1_REG0_RAPIDIO_ADDRESS_MSB,0 ); SRIO_REGS->LSU1_REG1 = CSL_FMK( SRIO_LSU1_REG1_ADDRESS_LSB_CONFIG_OFFSET, 0); SRIO_REGS->LSU1_REG2 = CSL_FMK( SRIO_LSU1_REG2_DSP_AD...
Page 66 - Detailed Description; HOL blocking is undesired, but allowable for TX CPPI queues
www.ti.com 2.3.8.1 Detailed Description Reserved FLOW_CNTL0 31-18 R-0x00000 TT 17-16 R/W-01 FLOW_CNTL_ID 15-0 R/W-0x0000 Reserved FLOW_CNTL1 31-18 R-0x00000 TT 17-16 R/W-01 FLOW_CNTL_ID 15-0 R/W-0x0000 Reserved FLOW_CNTL2 31-18 R-0x00000 TT 17-16 R/W-01 FLOW_CNTL_ID 15-0 R/W-0x0000 Reserved FLOW_CNT...
Page 67 - illustrates the registers that contain the flow masks, and; Figure 28. Transmit Source Flow Control Masks
www.ti.com Reserved RIO_LSUn_FLOW_MASKS (Address Offsets: 0x041C, 0x043C, 0x045C, 0x047C) 31-16 R, 0x0000 LSU n Flow Mask 15-0 R/W, 0xFFFF TX Queue1 Flow Mask RIO_TX_CPPI_FLOW_MASKS0 (Address Offsets: 0x0704) 31-16 R/W, 0xFFFF TX Queue0 Flow Mask 15-0 R/W, 0xFFFF TX Queue3 Flow Mask RIO_TX_CPPI_FLOW...
Page 68 - Endianness; Table 25. Fields Within Each Flow Mask; Figure 6
www.ti.com 2.3.9 Endianness SRIO Functional Description Table 25. Fields Within Each Flow Mask Bit Field Value Description 15 FL15 0 TX source does not support Flow 15 from table entry 1 TX source supports Flow 15 from table entry 14 FL14 0 TX source does not support Flow 14 from table entry 1 TX so...
Page 69 - Translation for MMR space; Figure 30. Configuration Bus Example
www.ti.com 2.3.9.1 Translation for MMR space A0 A0 A2 A2 A1 A1 A3 A3 L2 offset 0x0 DSP defined MMR offset 0x1000 Bytelane 0 31 Byte lane 3 DMA 32b 0 2.3.9.2 Endian Conversion (TMS320TCI6482) RapidIO defined bit positions A0 A1 A2 A3 31 0 MMR offset 0x0000 B0 B1 B2 B3 MMR offset 0x0004 C0 C1 C2 C3 MM...
Page 70 - Reset and Power Down; Table 26. Reset Hierarchy; Bus
www.ti.com 2.3.10 Reset and Power Down SRIO Functional Description The RapidIO peripheral allows independent software controlled shutdown for the logical blocks listed in Table 26 . With the exception of BLK0_EN for the memory-mapped registers (MMRs), when the BLKn_EN signals are deasserted, the clo...
Page 72 - The 18 block-specific registers are represented by
www.ti.com SRIO Functional Description Table 27. Global Enable and Global Enable Status Field Descriptions Register (Bit) Field Value Description GBL_EN(31–1) Reserved 0 These read-only bits return 0s when read. GBL_EN(0) EN Global enable. This bit controls reset to all clock domains within theperip...
Page 73 - Table 28. Block Enable and Block Enable Status Field Descriptions
www.ti.com SRIO Functional Description Figure 35. BLK0_EN_STAT (Address 003Ch) 31 1 0 Reserved EN_STAT R-0 R-1 LEGEND: R = Read, W = Write, -n = Value after reset Figure 36. BLK1_EN (Address 0040h) 31 1 0 Reserved EN R-0 R/W-1 LEGEND: R = Read, W = Write, -n = Value after reset Figure 37. BLK1_EN_ST...
Page 74 - Software Shutdown Details; Emulation; Table 29. Peripheral Control Register (PCR) Field Descriptions
www.ti.com 2.3.10.3 Software Shutdown Details 2.3.11 Emulation SRIO Functional Description Power consumption is minimized for all logical blocks that are in shutdown. In addition to simply assertingthe appropriate reset signal to each logical block within the peripheral, clocks are gated off to thec...
Page 75 - TX Buffers, Credit, and Packet Reordering; Multiple Ports With 1x Operation
www.ti.com 2.3.12 TX Buffers, Credit, and Packet Reordering 2.3.12.1 Multiple Ports With 1x Operation SRIO Functional Description Table 29. Peripheral Control Register (PCR) Field Descriptions (continued) Bit Field Value Description 1 SOFT Soft stop. This bit and the FREE bit determine how the SRIO ...
Page 77 - Enabling the SRIO Peripheral; Table 30. Port Mode Register Settings; Device
www.ti.com 2.3.13 Initialization Example 2.3.13.1 Enabling the SRIO Peripheral 2.3.13.2 PLL, Ports, Device ID and Data Rate Initializations SRIO Functional Description For multi-segment messages, if the transfer is unsuccessful after 256 times of credit request for the firstsegment, the TXU moves to...
Page 78 - Peripheral Initializations; Set Device ID Registers
www.ti.com 2.3.13.3 Peripheral Initializations SRIO Functional Description SRIO_REGS->SERDES_CFG0_CNTL = 0x00000013; SRIO_REGS->SERDES_CFG1_CNTL = 0x00000000; SRIO_REGS->SERDES_CFG2_CNTL = 0x00000000; SRIO_REGS->SERDES_CFG3_CNTL = 0x00000000; SRIO_REGS->SERDES_CFGRX0_CNTL = 0x00081121...
Page 79 - Bootload Capability; Configuration and Operation; Assert the PEREN bit to enable logical layer data flow; internal ROM code to initialize SRIO.
www.ti.com 2.3.14 Bootload Capability 2.3.14.1 Configuration and Operation SRIO Functional Description SRIO_REGS->SP_RT_CTL = 0xFFFFFF00; // long SRIO_REGS->SP_GEN_CTL = 0x40000000; // agent, master, undiscovered SRIO_REGS->SP0_CTL = 0x00600000; // enable i/o SRIO_REGS->SP1_CTL = 0x00600...
Page 80 - Figure 41. Bootload Operation; Section 4
www.ti.com Boot Program Host Controller Optional I2C EEPROM DSP ROM 1x RapidIO 2.3.14.2 Bootload Data Movement 2.3.14.3 Device Wakeup 2.3.15 RX Multicast Support, Daisy Chain Operation and Packet Forwarding 2.3.15.1 RX Multicast Support SRIO Functional Description 4. DSP executes idle instruction.5....
Page 81 - Table 31. Multicast DeviceID Operation; . If the packet’s DestID doesn’t match either, the
www.ti.com 2.3.15.2 Daisy Chain Operation and Packet Forwarding 2.3.15.3 Enabling Multicast and Packet Forwarding SRIO Functional Description Table 31. Multicast DeviceID Operation Local DeviceID Multicast DeviceID Device Register Offset Register Offset Endpoint Device Requirements TMS320TCI6482 008...
Page 83 - Logical/Transport Error Handling and Logging; names the functional
www.ti.com 3 Logical/Transport Error Handling and Logging Logical/Transport Error Handling and Logging Error management registers allow detection and logging of logical/transport layer errors. The detectableerrors are captured in the logical layer error detect CSR (see Figure 44 ). Table 34 names th...
Page 85 - CPU Interrupts; Interrupt Conditions; The following interrupts are supported by the RIO peripheral.; Figure 45. RapidIO DOORBELL Packet for Interrupt Use
www.ti.com 4 Interrupt Conditions 4.1 CPU Interrupts 4.2 General Description acklD rsv prio tt 1010 destID sourcelD Reserved srcTID Reserved Doorbell Reg # rsv Doorbell bit CRC PHY LOG TRA LOG TRA PHY 5 3 2 2 4 8 8 8 8 9 2 1 4 16 16 32 16 4 2 10 info (msb) 8 info (lsb) 8 Interrupt Conditions This se...
Page 86 - Interrupt Condition Status and Clear Registers
www.ti.com 4.3 Interrupt Condition Status and Clear Registers Interrupt Conditions The DOORBELL packet’s 16-bit INFO field indicates which DOORBELL register interrupt bit to set. Thereare four DOORBELL registers, each currently with 16 bits, allowing 64 interrupt sources or circular buffers(see Tabl...
Page 87 - Doorbell Interrupt Condition Status and Clear Registers; Table 35. Interrupt Condition Status and Clear Bits; through
www.ti.com 4.3.1 Doorbell Interrupt Condition Status and Clear Registers Interrupt Conditions Table 35. Interrupt Condition Status and Clear Bits Field Access Reset Value Value Function ICSx R 0 0 Condition not present 1 Condition present ICCx W 0 0 No effect 1 Clear the condition status bit (ICSx) ...
Page 88 - CPPI Interrupt Condition Status and Clear Registers; The ICSRs and the ICCRs for the RXU and the TXU are shown in
www.ti.com 4.3.2 CPPI Interrupt Condition Status and Clear Registers Interrupt Conditions Figure 48. Doorbell 2 Interrupt Condition Status and Clear Registers Doorbell 2 Interrupt Condition Status Register (DOORBELL2_ICSR) (Address Offset 0220h) 31 16 Reserved R-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1...
Page 89 - LSU Interrupt Condition Status and Clear Registers; Figure 50. RX CPPI Interrupt Condition Status and Clear Registers; Figure 51. TX CPPI Interrupt Condition Status and Clear Registers; The ICSR and the ICCR for the LSUs are shown in
www.ti.com 4.3.3 LSU Interrupt Condition Status and Clear Registers Interrupt Conditions For transmission, the clearing of any ICSR bit is dependent on the CPU writing to the CP register for thequeue (QUEUEn_TXDMA_CP). The CPU acknowledges the interrupt after reclaiming all available bufferdescripto...
Page 90 - Figure 52. LSU Interrupt Condition Status and Clear Registers
www.ti.com Interrupt Conditions Figure 52. LSU Interrupt Condition Status and Clear Registers LSU Interrupt Condition Status Register (LSU_ICSR) (Address Offset 0260h) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ICS31 ICS30 ICS29 ICS28 ICS27 ICS26 ICS25 ICS24 ICS23 ICS22 ICS21 ICS20 ICS19 ICS18 ...
Page 91 - The ICSR and the ICCR for the SRIO ports are shown in
www.ti.com 4.3.4 Error, Reset, and Special Event Interrupt Condition Status and Clear Registers Interrupt Conditions Table 36. Interrupt Conditions Shown in LSU_ICSR and Cleared With LSU_ICCR (continued) Bit Associated LSU Interrupt Condition 6 LSU1 Retry Doorbell response received or Atomic test-an...
Page 92 - Interrupt Function; Step; Step
www.ti.com Interrupt Conditions The interrupt status bits found in the ERR_RST_EVNT (0x0270) can be cleared by writing to the ICCRregister (0x0278) in the same manner as other interrupts. However, in order for new event detection andinterrupt generation to occur for these special interrupts, additio...
Page 93 - Interrupt Condition Routing Registers; Doorbell Interrupt Condition Routing Registers; Table 39. Interrupt Condition Routing Options; same bit field map, with the following addresses:
www.ti.com 4.4 Interrupt Condition Routing Registers 4.4.1 Doorbell Interrupt Condition Routing Registers Interrupt Conditions Table 38. Interrupt Clearing Sequence for Special Event Interrupts (continued) Interrupt Function 1 st Step 2 nd Step 3 rd Step Port 3 Error Write 1 to clear: Write 1 to cle...
Page 94 - CPPI Interrupt Condition Routing Registers; Figure 54. Doorbell 0 Interrupt Condition Routing Registers; shows the ICRRs for the RXU, and; Figure 55. RX CPPI Interrupt Condition Routing Registers
www.ti.com 4.4.1.1 CPPI Interrupt Condition Routing Registers Interrupt Conditions When doorbell packets are received by the SRIO peripheral, these ICRRs route doorbell interrupt requeststo interrupt destinations. For example, if ICS6 = 1 in DOORBELL2_ICSR and ICR6 = 0010b inDOORBELL2_ICRR, the inte...
Page 95 - LSU Interrupt Condition Routing Registers; Figure 56. TX CPPI Interrupt Condition Routing Registers
www.ti.com 4.4.1.2 LSU Interrupt Condition Routing Registers Interrupt Conditions Figure 56. TX CPPI Interrupt Condition Routing Registers TX CPPI Interrupt Condition Routing Register (TX_CPPI_ICRR) (Address Offset 02D0h) 31 28 27 24 23 20 19 16 ICR7 ICR6 ICR5 ICR4 R/W-0000 R/W-0000 R/W-0000 R/W-000...
Page 96 - Figure 57. LSU Interrupt Condition Routing Registers; The ICRRs shown in
www.ti.com 4.4.1.3 Error, Reset, and Special Event Interrupt Condition Routing Registers Interrupt Conditions Figure 57. LSU Interrupt Condition Routing Registers LSU Interrupt Condition Routing Register 0 (LSU_ICRR0) (Address Offset 02E0h) 31 28 27 24 23 20 19 16 ICR7 ICR6 ICR5 ICR4 R/W-0000 R/W-00...
Page 97 - Interrupt Status Decode Registers; shows which interrupt sources can be mapped to
www.ti.com 4.5 Interrupt Status Decode Registers Interrupt Conditions Figure 58. Error, Reset, and Special Event Interrupt Condition Routing Registers Error, Reset, and Special Event ICRR (ERR_RST_EVNT_ICRR) (Address Offset 02F0h) 31 Reserved R-0 12 11 8 7 4 3 0 Reserved ICR2 ICR1 ICR0 R-0 R/W-0000 ...
Page 98 - . The doorbell interrupt sources can be mapped to bits 15–0.; Figure 60. Interrupt Sources Assigned to ISDR Bits; illustrates the decode routing for
www.ti.com Interrupt Conditions each bit in the ISDR. Bits within the LSU interrupt condition status register (ICSR) are logically grouped fora given core and ORed together into a single bit (bit 31) of the decode register. Similarly, the bits withinthe Error, Reset, and Special Event ICSR are ORed ...
Page 100 - Interrupt Handling
www.ti.com 4.8 Interrupt Handling Interrupt Conditions immediately starts down-counting each time the CPU writes these registers. When the rate control counterregister is written, and the counter value reaches zero (note that the CPU may write zero immediately fora zero count), the interrupt pulse g...
Page 102 - Introduction; SRIO Registers; Offset
www.ti.com 5 SRIO Registers 5.1 Introduction SRIO Registers Table 40 lists the names and address offsets of the memory-mapped registers for the Serial RapidIO (SRIO) peripheral. See the device-specific data manual for the exact memory addresses of theseregisters. Table 40. Serial RapidIO (SRIO) Regi...
Page 111 - The peripheral ID register (PID) is shown in
www.ti.com 5.2 Peripheral Identification Register (PID) SRIO Registers The peripheral identification register (PID) is a read-only register that contains the ID and ID revisionnumber for that peripheral. The PID stores version information used to identify the peripheral. Writes haveno effect to this...
Page 112 - Table 42. Peripheral Control Register (PCR) Field Descriptions
www.ti.com 5.3 Peripheral Control Register (PCR) SRIO Registers The peripheral control register (PCR) contains a bit that enables or disables data flow in the logical layerof the entire peripheral. In addition, the PCR has emulation control bits that control the peripheral behaviorduring emulation h...
Page 119 - shown in
www.ti.com 5.7 Block n Enable Register (BLKn_EN) SRIO Registers There are nine of these registers, one for each of nine logical blocks in the peripheral. The registers andthe blocks they support are listed in Table 46 . The general form for a block n enable register (BLKn_EN) is shown in Figure 68 a...
Page 120 - . The general form for a block n enable status register
www.ti.com 5.8 Block n Enable Status Register (BLKn_EN_STAT) SRIO Registers There are nine of these registers, one for each of nine logical blocks in the peripheral. The registers andthe blocks they support are listed in Table 48 . The general form for a block n enable status register (BLKn_EN_STAT)...
Page 122 - The RapidIO DEVICEID2 register (DEVICEID_REG2 is shown in
www.ti.com 5.10 RapidIO DEVICEID2 Register (DEVICEID_REG2) SRIO Registers The RapidIO DEVICEID2 register (DEVICEID_REG2 is shown in Figure 71 and described in Table 51 . For additional programming information, see Section 2.3.15.1 and Section 2.3.15.3 . Figure 71. RapidIO DEVICEID2 Register (DEVICEI...
Page 126 - Low Freq Gain
www.ti.com SRIO Registers Table 57. SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL) Field Descriptions (continued) Bit Field Value Description 15–14 LOS Loss of signal. Enables loss of signal detection with 2 selectable thresholds. 00b Disabled. Loss of signal detection disabled...
Page 128 - There are four of these registers, to support four ports (see
www.ti.com 5.14 SERDES Transmit Channel Configuration Register n (SERDES_CFGTXn_CNTL) SRIO Registers There are four of these registers, to support four ports (see Table 59 ). The general form for a SERDES transmit channel configuration register is summarized by Figure 75 and Table 60 . See Section 2...
Page 132 - The four doorbell interrupts are mapped to these registers (see
www.ti.com 5.16 DOORBELLn Interrupt Condition Status Register (DOORBELLn_ICSR) SRIO Registers The four doorbell interrupts are mapped to these registers (see Table 65 ). The general form of a doorbell interrupt condition status register is shown in Figure 77 and described in Table 66 . For additiona...
Page 133 - of a doorbell interrupt condition clear register is shown in
www.ti.com 5.17 DOORBELLn Interrupt Condition Clear Register (DOORBELLn_ICCR) SRIO Registers The four doorbells interrupts that are mapped are cleared by this register (see Table 67 ). The general form of a doorbell interrupt condition clear register is shown in Figure 78 and described in Table 68 ....
Page 144 - applies to an ICRx
www.ti.com 5.26 DOORBELLn Interrupt Condition Routing Registers (DOORBELLn_ICRR and SRIO Registers DOORBELLn_ICRR2) When doorbell packets are received by the SRIO peripheral, these ICRRs route doorbell interrupt requestsfrom the associated doorbell ICSR to user-selected interrupt destinations. Each ...
Page 145 - Figure 88. RX CPPI Interrupt Condition Routing Registers
www.ti.com 5.27 RX CPPI Interrupt Condition Routing Registers (RX_CPPI_ICRR and RX_CPPI_ICRR2) SRIO Registers Figure 88 and Table 79 summarize the ICRRs for the RXU. These registers route queue interrupts to interrupt destinations. For example, if ICS6 = 1 in RX_CPPI_ICSR and ICR6 = 0010b in RX_CPPI...
Page 146 - Figure 89. TX CPPI Interrupt Condition Routing Registers
www.ti.com 5.28 TX CPPI Interrupt Condition Routing Registers (TX_CPPI_ICRR and TX_CPPI_ICRR2) SRIO Registers Figure 89 and Table 80 summarize the ICRRs for the TXU. These registers route queue interrupts to interrupt destinations. For example, if ICS6 = 1 in TX_CPPI_ICSR and ICR6 = 0011b in TX_CPPI...
Page 147 - shows the ICRRs for the LSU interrupt requests, and; Figure 90. LSU Interrupt Condition Routing Registers
www.ti.com 5.29 LSU Interrupt Condition Routing Registers (LSU_ICRR0–LSU_ICRR3) SRIO Registers Figure 90 shows the ICRRs for the LSU interrupt requests, and Table 81 shows the general description for an ICRx field in any of the four registers. These registers route LSU interrupt requests from LSU_IC...
Page 150 - Destinations
www.ti.com 5.31 Interrupt Status Decode Register (INTDSTn_DECODE) SRIO Registers There are eight of these registers, one for each interrupt destination (see Table 83 ). This type of register is shown in Figure 92 and described in Table 84 . Interrupt sources are mapped to an interrupt decode registe...
Page 155 - There are four of these registers, one for each LSU (see
www.ti.com 5.33 LSUn Control Register 0 (LSUn_REG0) SRIO Registers There are four of these registers, one for each LSU (see Table 87 ). The general description for an LSU control register 0 is shown in Figure 94 and described in Table 88 . For additional programming see Section 2.3.3 . Table 87. LSU...
Page 164 - There are sixteen of these registers (see
www.ti.com 5.41 Queue n Transmit DMA Head Descriptor Pointer Register (QUEUEn_TXDMA_HDP) SRIO Registers There are sixteen of these registers (see Table 104 ). QUEUEn_TXDMA_HDP is shown in Figure 103 and described in Table 105 . For additional programming information, see Section 2.3.4.2 . Table 104....
Page 169 - shows the registers, and; Register
www.ti.com 5.46 Transmit CPPI Supported Flow Mask Registers (TX_CPPI_FLOW_MASKS[0–7]) SRIO Registers Each of the eight TX CPPI flow mask registers holds the flow masks for two TX descriptor buffer queues(see Table 113 ). Figure 108 shows the registers, and Figure 109 shows the general form of a flow...
Page 170 - Figure 108. Transmit CPPI Supported Flow Mask Registers; Table 114. TX Queue n FLOW_MASK Field Descriptions
www.ti.com SRIO Registers Figure 108. Transmit CPPI Supported Flow Mask Registers Transmit CPPI Supported Flow Mask Register 0 (TX_CPPI_FLOW_MASKS0) 31 16 15 0 QUEUE1_FLOW_MASK QUEUE0_FLOW_MASK R/W-FFh R/W-FFh Transmit CPPI Supported Flow Mask Register 1 (TX_CPPI_FLOW_MASKS1) 31 16 15 0 QUEUE3_FLOW_...
Page 173 - . For additional programming information, see
www.ti.com 5.48 Receive CPPI Control Register (RX_CPPI_CNTL) SRIO Registers Each bit in this register indicates whether the associated RX buffer descriptor queue must receivemessages in the order the source device attempts to transmit them. RX_CPPI_CNTL is shown in anddescribed in Table 116 . For ad...
Page 174 - . As part of this scheme, software must program the 16; Figure 112. Transmit CPPI Weighted Round Robin Control Registers
www.ti.com 5.49 Transmit CPPI Weighted Round Robin Control Registers (TX_QUEUE_CNTL[0–3]) SRIO Registers The transmission order among TX buffer descriptor queues is based on the programmable weightedround-robin scheme explained in Section 2.3.4.2 . As part of this scheme, software must program the 1...
Page 177 - lists all of these; Mappers
www.ti.com 5.50 Mailbox to Queue Mapping Registers (RXU_MAP_Ln and RXU_MAP_Hn) SRIO Registers Messages addressed to any of the 64 mailbox locations can be received on any of the RapidIO portssimultaneously. Packets are handled sequentially in order of receipt. A block of 32 mappers directs theinboun...
Page 179 - Figure 113. Mailbox to Queue Mapping Register Pair
www.ti.com SRIO Registers Figure 113. Mailbox to Queue Mapping Register Pair Mailbox to Queue Mapping Register L n (RXU_MAP_L n ) 31 30 29 24 23 22 21 16 LETTER_MASK MAILBOX_MASK LETTER MAILBOX R/W-11 R/W-111111 R/W-00 R/W-000000 15 0 SOURCEID R/W-0000h Mailbox to Queue Mapping Register H n (RXU_MAP...
Page 200 - Each of the four ports is supported by a register of this type (see
www.ti.com 5.69 Port Link Maintenance Request CSR n (SPn_LM_REQ) SRIO Registers Each of the four ports is supported by a register of this type (see Table 140 ). SPn_LM_REQ is shown in Figure 132 and described in Table 141 . Table 140. SPn_LM_REQ Registers and the Associated Ports Register Address Of...
Page 234 - , each of the registers captures one of the four 32-bit
www.ti.com 5.94 Port-Write-In Capture CSRs (SP_IP_PW_IN_CAPT[0–3]) SRIO Registers Four registers are used to capture the incoming 128-bit payload of a Port-Write. These four registers areshown in Figure 157 . As can be seen in Table 179 , each of the registers captures one of the four 32-bit words o...
Page 241 - rate counting enable field
Index SPRUE13A – September 2006 Index 1x/4x LP serial port maintenance block header register next expected ackID field 202 196 output port next transmitted ackID field 202 1x/4x mode selection field for ports 231 output port unacknowledged ackID status field 202 1X_MODE field of PER_SET_SNTL 113 une...
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