Page 2 - IMPORTANT NOTICE
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinueany product or service without notice, and advise customers to obtain the latest version of relevant informationto verify, before placing orders, that information being r...
Page 3 - Preface; Read This First; About This Manual; tion from Texas Instruments on page v.; How to Use This Manual; Turn to these locations:; PRELIMINARY
iii PRELIMINARY Preface Read This First About This Manual This reference guide describes the operation of the embedded flash EEPROMmodule on the TMS320F20x/F24x digital signal processor (DSP) devices andprovides sample code that you can use in developing your own software. Theperformance specificati...
Page 4 - Notational Conventions; This document uses the following conventions.
PRELIMINARY iv PRELIMINARY If you are looking for in-formation about: Turn to these locations: Over-erasure (depletion) andrecovery Section 1.1, Basic Concepts of Flash Memory TechnologySection 2.7, Recovering From Over-Erasure (Flash-Write Operation)Section 3.4, Flash-Write Algorithm Programming th...
Page 5 - Related Documentation From Texas Instruments; TMS320C24x DSP Controllers Reference Set Volume 2: Peripheral
Related Documentation From Texas Instruments PRELIMINARY v Read This First PRELIMINARY Related Documentation From Texas Instruments The following books describe the ’F20x/24x and related support tools. To ob-tain a copy of any of these TI documents, call the Texas Instruments LiteratureResponse Cent...
Page 6 - TMS320C2xx C Source Debugger User’s Guide (literature number
Related Documentation From Texas Instruments PRELIMINARY vi PRELIMINARY TMS320C2xx C Source Debugger User’s Guide (literature number SPRU151) tells you how to invoke the ’C2xx emulator and simulator ver-sions of the C source debugger interface. This book discusses variousaspects of the debugger inte...
Page 7 - North America, South America, Central America
If You Need Assistance . . . PRELIMINARY vii Read This First PRELIMINARY If You Need Assistance . . . - World-Wide Web Sites TI Online http://www.ti.com Semiconductor Product Information Center (PIC) http://www.ti.com/sc/docs/pic/home.htm DSP Solutions http://www.ti.com/dsps 320 Hotline On-line t ht...
Page 9 - Contents; Introduction
Contents ix Contents 1 Introduction 1 Ć 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Discusses basic flash memory technology; summarizes the features and benefits of theTMS320F20x/F24x flash module 1.1 Bas...
Page 11 - Figures
Figures xi Contents Figures 1–1 TMS320F20x/F24x Program Space Memory Maps 1 Ć 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 Flash Memory Logic Levels During Programming and Erasing 2 Ć 4 . . . . . . . . . . . . . . . . . . . . . . 2–2 Memory Maps in Register and Array Access ...
Page 12 - Tables
Tables xii Tables 1–1 TMS320 Devices With On-Chip Flash EEPROM 1 Ć 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 Operations that Modify the Contents of the Flash Array 2 Ć 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2 Flash Module Control Registers 2 Ć 8 ....
Page 13 - Topic; Basic Concepts of Flash Memory Technology; Chapter 1
1-1 Introduction The TMS320F20x/F24x digital signal processors (DSPs) contain on-chip flashEEPROM (electrically-erasable programmable read-only memory). The em-bedded flash memory provides an attractive alternative to masked programROM. Like ROM, flash memory is nonvolatile, but it has an advantage ...
Page 14 - block or flash operation, rather than being affected one bit at a
Basic Concepts of Flash Memory Technology PRELIMINARY 1-2 PRELIMINARY 1.1 Basic Concepts of Flash Memory Technology The term flash in this EEPROM technology refers to the speed of some of theoperations performed on the memory (these operations will be described ingreater detail later in this documen...
Page 15 - Table 1–1. TMS320 Devices With On-Chip Flash EEPROM; Device
TMS320F20x/F24x Flash Module PRELIMINARY 1-3 Introduction PRELIMINARY 1.2 TMS320F20x/F24x Flash Module The ’F20x/F24x flash EEPROM is implemented with one or two independentflash memory modules of 8K or 16K words. Each flash module is composedof a flash memory array, four control registers, and circ...
Page 19 - Flash Operations and Control Registers; Chapter 2
2-1 Flash Operations and Control Registers The operations that modify the contents of the ’F20x/F24x flash array are per-formed in software through the use of dedicated programming algorithms. Thischapter introduces the operations performed by these algorithms and explainsthe role of the control reg...
Page 20 - Clear – which is used to write ALL array bits to a zero state,
Operations that Modify the Contents of the ’F20x/F24x Flash Array PRELIMINARY 2-2 PRELIMINARY 2.1 Operations that Modify the Contents of the ’F20x/F24x Flash Array Operations that modify the contents of the flash array are generically referredto as either “programming,” which drives one or more bits...
Page 21 - This procedure is discussed in complete detail in Chapter 3.
Operations that Modify the Contents of the ’F20x/F24x Flash Array PRELIMINARY 2-3 Flash Operations and Control Registers PRELIMINARY This procedure is discussed in complete detail in Chapter 3. During these operations that are used to modify the contents of the flash array,three special read modes, ...
Page 22 - Table 2–1. Operations that Modify the Contents of the Flash Array; Change in Bit Level
Operations that Modify the Contents of the ’F20x/F24x Flash Array PRELIMINARY 2-4 PRELIMINARY Figure 2–1. Flash Memory Logic Levels During Programming and Erasing Erase operation Depletion Mode Logic 1 1 Margin 0 Margin Logic 0 VER0 Erase (Towards logic Clear Program Flash Write (Towards logic Refer...
Page 23 - The two access modes are summarized as follows:
Accessing the Flash Module PRELIMINARY 2-5 Flash Operations and Control Registers PRELIMINARY 2.2 Accessing the Flash Module In addition to the flash memory array, each flash module has four registers thatcontrol operations on the flash array. These registers are: Segment control register (SEG_CTR) ...
Page 24 - Figure 2–2. Memory Maps in Register and Array Access Modes
Accessing the Flash Module PRELIMINARY 2-6 PRELIMINARY Figure 2–2. Memory Maps in Register and Array Access Modes SEG_CTR register TST register WADRS register WDATA register Flash memory array Flash access control register (single bit) MODE = 1: Array-access modeMODE = 0: Register access mode 0100 ....
Page 25 - TMS320F24x Flash Access-Control Register; OUT
Accessing the Flash Module PRELIMINARY 2-7 Flash Operations and Control Registers PRELIMINARY Although the function is the same, the access control registers of the ’F206 de-vice are mapped at different addresses from that of the ’F24x devices, andtheir values are modified in a different way. 2.2.2 ...
Page 26 - Table 2–2. Flash Module Control Registers
Flash Module Control Registers PRELIMINARY 2-8 PRELIMINARY 2.3 Flash Module Control Registers Table 2–2 lists the control registers and their relative addresses within the fourlocations that repeat throughout the module’s address range. Table 2–2. Flash Module Control Registers Relative Register Des...
Page 27 - Table 2–3. Segment Control Register Field Descriptions; Bits
Flash Module Control Registers PRELIMINARY 2-9 Flash Operations and Control Registers PRELIMINARY Table 2–3. Segment Control Register Field Descriptions Bits Name Description 15–8 SEG7–SEG0 Segment enable bits. Each of these bits protects the specified segment against pro-gramming or enables program...
Page 28 - Table 2–4. Flash Array Segments Summary; SEG7–SEG0 Bits; 6 blocks. Some time after the first block is programmed,
Flash Module Control Registers PRELIMINARY 2-10 PRELIMINARY Table 2–4. Flash Array Segments Summary SEG7–SEG0 Bits ’F206/F240 Flash Module † ’F241/F243 Array Segment 15 14 13 12 11 10 9 8 Flash0 Flash1 F241/F243 Flash Module Array Segment Enabled 0 0 0 0 0 0 0 1 0000–07FFh 4000–47FFh 0000–03FFh 0 0 ...
Page 32 - clearing the; Flash Memory Logic Lev-
Erase Operation PRELIMINARY 2-14 PRELIMINARY 2.6 Erase Operation The erase operation of the ’F20x/F24x flash module prepares the flash arrayfor programming and enables reprogrammability of the flash array. Before thearray can be erased, all bits must be programmed to 0s. This procedure of pro-grammi...
Page 33 - Flash
Recovering From Over-Erasure (Flash-Write Operation) PRELIMINARY 2-15 Flash Operations and Control Registers PRELIMINARY 2.7 Recovering From Over-Erasure (Flash-Write Operation) Generally, not all bits in the flash array have the same amount of charge re-moved with each erase pulse. By the time all ...
Page 35 - Erase Algorithm; Chapter 3
3-1 Algorithm Implementations and Software Considerations This chapter discusses the implementations of the algorithms for performingthe operations described in the previous chapter. It also discusses items youmust consider when incorporating the algorithms into your ’F20x/F24x DSPapplication code. ...
Page 37 - Figure 3–1. Algorithms in the Overall Flow
How the Algorithms Fit Into the Program-Erase-Reprogram Flow PRELIMINARY 3-3 Algorithm Implementations and Software Considerations PRELIMINARY Figure 3–1. Algorithms in the Overall Flow Flash-write algorithm Erase algorithm Clear algorithm X = X+1 flash-write Recover using Fail Yes No X < 10 ? ar...
Page 38 - Figure 3–2. The Programming Algorithm in the Overall Flow
Programming (or Clear) Algorithm PRELIMINARY 3-4 PRELIMINARY 3.2 Programming (or Clear) Algorithm The programming algorithm sequentially writes any number of addresses witha specified bit pattern.This algorithm is used to program application code ordata into the flash array. With a slight modificati...
Page 39 - s required to program the bits in the
Programming (or Clear) Algorithm PRELIMINARY 3-5 Algorithm Implementations and Software Considerations PRELIMINARY The main feature of the program/clear algorithm is the concept of program-ming an entire row of bits in a group. The ’F20x/F24x flash array is organizedin rows of 32 words. That is, add...
Page 40 - Figure 3–3. Programming or Clear Algorithm Flow
Programming (or Clear) Algorithm PRELIMINARY 3-6 PRELIMINARY Figure 3–3. Programming or Clear Algorithm Flow Same row Device failure Continue Current address > end address? No Yes Row_done = true? No Yes No Yes End of row? No Yes Pulsecount =max†? Apply program pulse; row_done = false Increment a...
Page 41 - Step
Programming (or Clear) Algorithm PRELIMINARY 3-7 Algorithm Implementations and Software Considerations PRELIMINARY Another important consideration is the total amount of time required to do theprogramming. The number of programming pulses required to completely pro-gram a flash memory cell increases...
Page 44 - Figure 3–4. Erase Algorithm in the Overall Flow
Erase Algorithm PRELIMINARY 3-10 PRELIMINARY 3.3 Erase Algorithm The erase algorithm follows the clear algorithm in executing the entire initial-ization flow. Figure 3–4 highlights the erase algorithm’s place in the overallflow. Figure 3–4. Erase Algorithm in the Overall Flow Flash-write algorithm E...
Page 45 - Table 3–2. Steps for Applying One Erase Pulse; address complementing. When the array is read
Erase Algorithm PRELIMINARY 3-11 Algorithm Implementations and Software Considerations PRELIMINARY Table 3–2. Steps for Applying One Erase Pulse Step Action Description 1 Power up the V CCP pin. Set V CCP pin to V DD. If the V CCP pin for the flash module to be erased is not set to V DD , then the a...
Page 46 - ) The contents of the restored address are read.
Erase Algorithm PRELIMINARY 3-12 PRELIMINARY 4) The actual address is restored. 5) The contents of the restored address are read. The advantage of this approach is that it forces the worst-case switching condi-tion on the flash addressing logic during the reads, thus improving the marginof the erase...
Page 47 - Figure 3–5. Erase Algorithm Flow
Erase Algorithm PRELIMINARY 3-13 Algorithm Implementations and Software Considerations PRELIMINARY Figure 3–5. Erase Algorithm Flow Program array check Á Á Depletion Yes No Á Á All 32 words = 0000h? Read first 32 words Wait for t d(BUSY-INVERSE) Set VER0 and VER1 bits in SEG_CTR Á Á Clear all bits i...
Page 48 - Figure 3–6. Flash-Write Algorithm in the Overall Flow
Flash-Write Algorithm PRELIMINARY 3-14 PRELIMINARY 3.4 Flash-Write Algorithm The flash-write operation recovers bits in depletion mode, which can becaused by over-erasure. The flash-write algorithm’s place in the overall flowis highlighted in Figure 3–6. Figure 3–6. Flash-Write Algorithm in the Over...
Page 49 - Table 3–3. Steps for Applying One Flash-Write Pulse; Steps
Flash-Write Algorithm PRELIMINARY 3-15 Algorithm Implementations and Software Considerations PRELIMINARY Table 3–3. Steps for Applying One Flash-Write Pulse Steps Action Description 1 Power up the V CCP pin. Set the V CCP pin to V DD . If the V CCP pin for the flash module to be re- covered is not s...
Page 53 - Assembly Source Listings and; Assembly Source for Algorithms; Appendix A
A-1 Appendix A Assembly Source Listings and Program Examples The flash array is erased and programmed by code running on the DSP core.This code can originate from off-chip memory or can be loaded into on-chipRAM. The available flash programming tools for the ’F20x/F24x allow you toprogram the on-chi...
Page 54 - The source files given are:
Assembly Source for Algorithms PRELIMINARY A-2 PRELIMINARY A.1 Assembly Source for Algorithms The algorithm source files implement the flows given in Chapter 3. Each algo-rithm is written as an assembly language subroutine, beginning with a label atan entry point and ending with a return instruction...
Page 57 - Parameters to be declared and initialized by the calling code are:
Assembly Source for Algorithms PRELIMINARY A-5 Assembly Source Listings and Program Examples PRELIMINARY A.1.2 Clear Algorithm, SCLR20.ASM This code is an implementation of the clear (programming) algorithm de-scribed in section 3.2 on page 3-4. Recall that the clear algorithm is identical tothe pro...
Page 87 - A.3.2 Linker Command File for TMS320F206 Sample Assembly Code
Sample Assembly Code to Erase and Reprogram the TMS320F206 PRELIMINARY A-35 Assembly Source Listings and Program Examples PRELIMINARY prg_error:********************************************************** If here, then an error has occurred during ** ** programming. In an actual application, the syste...
Page 89 - C-Callable Interface to Flash Algorithms, is provided
Sample C Code to Erase and Reprogram the TMS320F206 PRELIMINARY A-37 Assembly Source Listings and Program Examples PRELIMINARY A.4 Sample C Code to Erase and Reprogram the TMS320F206 Because the algorithm implementations do not follow the C-calling conventionof the ’C2000 C environment, they cannot ...
Page 90 - A.4.2 Linker Command File for TMS320F206 Sample C Code
Sample C Code to Erase and Reprogram the TMS320F206 PRELIMINARY A-38 PRELIMINARY { /*Flash fails programming, EXIT*/ while(1){} /*Spin here forever*/ } } else{ /*Flash fails erase, EXIT*/ while(1){} /*Spin here forever*/ } } A.4.2 Linker Command File for TMS320F206 Sample C Code /*******************...
Page 97 - A.5.2 Linker Command File for TMS320F240 Sample Assembly Code
Sample Assembly Code to Erase and Reprogram the TMS320F240 PRELIMINARY A-45 Assembly Source Listings and Program Examples PRELIMINARY A.5.2 Linker Command File for TMS320F240 Sample Assembly Code /************************************************************//* Filename: ASMEXA24.CMD */ /* Descriptio...
Page 100 - A.6.2 Linker Command File for TMS320F240 Sample C Code
Using the Algorithms With C Code to Erase and Reprogram the ’F240 PRELIMINARY A-48 PRELIMINARY extern int erase(); /* Declare external func for flash erase. */ extern int program(); /* Declare external func for flash programming */ extern c240init(); /* Declare external func for C240 register init’l...
Page 102 - A.6.3 C Function for Disabling TMS320F240 Watchdog Timer
Using the Algorithms With C Code to Erase and Reprogram the ’F240 PRELIMINARY A-50 PRELIMINARY .bss :{} > B1 PAGE 1 .cinit :{} > B1 PAGE 1 .const : load = EXTRAM PAGE 0, run = DSRAM PAGE 1 { /* GET RUN ADDRESS */ __const_run = .;/* MARK LOAD ADDRESS */*(.c_mark)/* ALLOCATE .const */ *(.const)/...
Page 105 - Index
Index PRELIMINARY Index-1 PRELIMINARY Index A access modes code for changing A-25 array access 2-5, 2-10, 2-11, 2-16, 3-8 register access 2-5, 2-10, 2-11, 3-11 access–control register 2-5 to 2-7 modifying in TMS320F206 2-6 modifying in TMS320F24x 2-7 reading in TMS320F206 2-6 accessing the flash mod...
