Texas Instruments TMS320DM648 - Manual

Texas Instruments TMS320DM648

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Table of Contents:

  • Page 3 – Contents
  • Page 13 – Read This First; About This Manual; This document uses the following conventions.; Related Documentation From Texas Instruments; . Tip: Enter the literature number in the; SPRUEK5
  • Page 15 – SPRUEM2; Trademarks
  • Page 16 – Topic
  • Page 17 – Video Port; It provides the following functions:
  • Page 19 – Video Port FIFO
  • Page 21 – For 8-bit raw video, the FIFO is split into channel A and B, as shown in
  • Page 22 – shows how
  • Page 24 – Figure 1-8. 8-Bit Locked Raw Video Display FIFO Configuration
  • Page 25 – Video Port Registers
  • Page 26 – Video Port Pin Mapping; . Pin functionality detail for video display mode is listed in
  • Page 27 – Table 1-3. VDIN Data Bus Usage for Capture Modes; Capture Mode
  • Page 28 – VDOUT Data Bus Usage for Display Modes; Video Port Pin Multiplexing; Table 1-4. VDOUT Data Bus Usage for Display Modes; Display Mode
  • Page 29 – Reset Operation
  • Page 30 – Clears PEREN bit in PCR to 0.
  • Page 31 – Interrupt Operation
  • Page 32 – EDMA Operation
  • Page 33 – EDMA Size and Threshold Restrictions
  • Page 34 – Video Port Control Registers; The video port control registers are listed in; Offset
  • Page 35 – The video port control register (VPCTL) is shown in; Bit; Value
  • Page 36 – Table 2-3. Video Port Operating Mode Selection
  • Page 37 – The video port status register (VPSTAT) is shown in
  • Page 38 – The video port interrupt enable register (VPIE) is shown in
  • Page 40 – The video port interrupt status register (VPIS) is shown in
  • Page 46 – Video Capture Mode Selection; The video capture module operates in one of five modes as listed in; TCI Bit
  • Page 47 – BT.656 Video Capture Mode; Data Bit; Line Information Bits; . The - entries indicate detected double bit errors that; Table 3-4. Error Correction by Protection Bits; Received P
  • Page 48 – lines per field, and the number of active pixels per line.
  • Page 49 – Table 3-5. Common Video Source Parameters; Number of Active Lines
  • Page 50 – Y/C Video Capture Mode
  • Page 51 – BT.656 and Y/C Mode Field and Frame Operation
  • Page 52 – Capture Determination and Notification; CON
  • Page 53 – Table 3-7. Vertical Synchronization Programming; ) and allows the VCYSTARTn bit to be set to 1, but
  • Page 55 – Table 3-8. Horizontal Synchronization Programming; for VCTL
  • Page 56 – Table 3-9. Field Identification Programming; EXC
  • Page 57 – Video Input Filtering
  • Page 58 – Cr’; CMODE
  • Page 59 – and scaling for chrominance re-sampling is
  • Page 60 – Ancillary Data Capture; Figure 3-12. Capture Window Not Requiring Edge Pixel Replication
  • Page 61 – Raw Data Capture Mode
  • Page 62 – Table 3-11. Raw Data Mode Capture Operation
  • Page 63 – TCI Capture Mode
  • Page 65 – shows the system time clock counter operation.; Figure 3-17. System Time Clock Counter Operation; VCACTL Bit
  • Page 67 – Capture Line Boundary Conditions; In; Figure 3-20. Capture Line Boundary Example
  • Page 68 – Capturing Video in Raw Data Mode; Set VCEN bit to enable capture.
  • Page 69 – Handling FIFO Overrun Condition in Raw Data Mode; Capturing Data in TCI Capture Mode
  • Page 70 – Handling FIFO Overrun Condition in TCI Capture Mode; Video Capture Registers; based on STC absolute time.; Table 3-13. Video Capture Control Registers
  • Page 71 – and
  • Page 72 – Description; and described in
  • Page 86 – The TCI system time clock LSB register (TCISTCLKL) is shown in
  • Page 87 – The TCI system time clock MSB register (TCISTCLKM) is shown in
  • Page 88 – and described
  • Page 91 – Video Capture FIFO Registers; The capture FIFO mapping registers are listed in; Table 3-35. Video Capture FIFO Registers Function
  • Page 93 – Field 1; Video Display Mode Selection; . The DMODE bits are in; DMODE Bits; compatible) is shown in; Figure 4-1. NTSC Compatible Interlaced Display
  • Page 94 – Figure 4-2. SMPTE 296M Compatible Progressive Scan Display
  • Page 95 – Figure 4-3. Interlaced Blanking Intervals and Video Areas
  • Page 96 – Figure 4-4. Progressive Blanking Intervals and Video Area
  • Page 97 – Figure 4-5. Horizontal Blanking and Horizontal Sync Timing
  • Page 98 – BT.656 Video Display Mode; Figure 4-7. Video Display Module Synchronization Chain
  • Page 99 – The BT.656 line timing is shown in
  • Page 100 – The typical values for H, V, and F on different lines are shown in; Line Number; Figure 4-11. Digital Vertical F and V Transitions
  • Page 102 – Y/C Video Display Mode
  • Page 103 – Video Output Filtering; VDCTL Bit
  • Page 104 – and scaling for interspersed
  • Page 105 – Figure 4-18. Output Edge Pixel Replication
  • Page 106 – Ancillary Data Display; Figure 4-20. Interspersed Chroma Edge Replication
  • Page 107 – Raw Data Display Mode; FIFO Unpacking
  • Page 108 – Display Determination and Notification; Video Display Field and Frame Operation
  • Page 109 – Display Line Boundary Conditions
  • Page 110 – Display Timing Examples; Figure 4-24. Display Line Boundary Example; The horizontal output timing is shown in
  • Page 111 – Figure 4-25. BT.656 Interlaced Display Horizontal Timing Example
  • Page 112 – The interlaced BT.656 vertical output timing is shown in
  • Page 113 – Figure 4-26. BT.656 Interlaced Display Vertical Timing Example
  • Page 114 – Figure 4-27. Raw Interlaced Display Horizontal Timing Example
  • Page 115 – The vertical output timing for raw mode is shown in; Figure 4-28. Raw Interlaced Display Vertical Timing Example
  • Page 117 – Figure 4-29. Y/C Progressive Display Horizontal Timing Example
  • Page 118 – The vertical output timing is shown in
  • Page 120 – Displaying Video in Raw Data Mode
  • Page 121 – by total double words per Y EDMA.
  • Page 122 – Video Display Registers; Table 4-5. Video Display Control Registers; The video display status register (VDSTAT) is shown in
  • Page 124 – The video display control register (VDCTL) is shown in
  • Page 127 – The video display frame size register (VDFRMSZ) is shown in
  • Page 133 – The video display field 1 image size register (VDIMGSZ1) is shown in
  • Page 135 – The video display field 2 image size register (VDIMGSZ2) is shown in
  • Page 136 – The video display field 2 timing register (VDFLDT2) is shown in
  • Page 137 – The video display threshold register (VDTHRLD) is shown in
  • Page 138 – Generation of the horizontal synchronization is shown in; Generation of the vertical synchronization is shown in
  • Page 139 – Descriptions
  • Page 141 – The video display counter reload register (VDRELOAD) is shown in
  • Page 142 – The video display event register (VDDISPEVET) is shown in; The video display clipping register (VDCLIP) is shown in
  • Page 143 – for the raw data mode, and described in
  • Page 144 – The video display field bit register (VDVINT) is shown in
  • Page 145 – The video display field bit register (VDFBIT) is shown in
  • Page 148 – Video Display Registers Recommended Values; Table 4-34. Video Display Register Recommended Values
  • Page 149 – Video Display FIFO Registers; The display FIFO mapping registers are listed in; Table 4-36. Video Display FIFO Registers Function
  • Page 150 – GPIO Registers
  • Page 151 – . See the device-specific datasheet for the memory address of; Offset Address
  • Page 153 – The video port peripheral control register (PCR) is shown in
  • Page 154 – The video port pin function register (PFUNC) is shown in
  • Page 156 – The video port pin direction register (PDIR) is shown in; Value Description
  • Page 158 – The read-only video port pin data input register (PDIN) is shown in
  • Page 159 – PDOUT has these aliases:
  • Page 161 – The video port pin data set register (PDSET) is shown in
  • Page 162 – The video port pin data clear register (PDCLR) is shown in
  • Page 163 – The video port pin interrupt enable register (PIEN) is shown in
  • Page 164 – The video port pin interrupt polarity register (PIPOL) is shown in
  • Page 165 – The video port pin interrupt status register (PISTAT) is shown in
  • Page 166 – The video port pin interrupt clear register (PICLR) is shown in
  • Page 168 – The VIC port supports following features:; VIC Port Signal
  • Page 169 – kf; Operational Details; , where k is determined by the precision; Table 6-2. Example Values for Interpolation Rate
  • Page 170 – Enabling VIC Port; Perform the following steps to enable the VIC port.
  • Page 171 – VIC Port Registers; The VIC control register (VICCTL) is shown in
  • Page 172 – The VIC input register (VICIN) is shown in
  • Page 173 – The VIC clock divider register (VICDIV) is shown in
  • Page 174 – IMPORTANT NOTICE; Products
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TMS320DM647/DM648

Video Port/VCXO Interpolated Control (VIC)

Port

User's Guide

Literature Number: SPRUEM1

May 2007

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Summary

Page 3 - Contents

Contents Preface .............................................................................................................................. 13 1 Overview ................................................................................................................. 16 1.1 Video Port .............

Page 13 - Read This First; About This Manual; This document uses the following conventions.; Related Documentation From Texas Instruments; . Tip: Enter the literature number in the; SPRUEK5

Preface SPRUEM1 – May 2007 Read This First About This Manual This document describes the video port and VCXO interpolated control (VIC) port in the digital signalprocessors (DSPs). Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h....

Page 15 - SPRUEM2; Trademarks

www.ti.com Related Documentation From Texas Instruments SPRUEM2 — TMS320DM647/DM648 DSP Serial Port Interface (SPI) User's Guide discusses the Serial Port Interface (SPI) in the TMS320DM647/DM648 Digital Signal Processor (DSP). Thisreference guide provides the specifications for a 16-bit configurabl...

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