Page 3 - Contents
Contents Preface .............................................................................................................................. 13 1 Overview ................................................................................................................. 16 1.1 Video Port .............
Page 13 - Read This First; About This Manual; This document uses the following conventions.; Related Documentation From Texas Instruments; . Tip: Enter the literature number in the; SPRUEK5
Preface SPRUEM1 – May 2007 Read This First About This Manual This document describes the video port and VCXO interpolated control (VIC) port in the digital signalprocessors (DSPs). Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h....
Page 15 - SPRUEM2; Trademarks
www.ti.com Related Documentation From Texas Instruments SPRUEM2 — TMS320DM647/DM648 DSP Serial Port Interface (SPI) User's Guide discusses the Serial Port Interface (SPI) in the TMS320DM647/DM648 Digital Signal Processor (DSP). Thisreference guide provides the specifications for a 16-bit configurabl...
Page 16 - Topic
SPRUEM1 – May 2007 Overview This chapter provides an overview of the video port peripheral in the digital signalprocessors (DSPs). An overview of the video port functions, FIFO configurations, andsignal mapping are included. Topic ........................................................................
Page 17 - Video Port; It provides the following functions:
www.ti.com 1.1 Video Port Video Port The video port peripheral can operate as a video capture port, video display port, or transport channelinterface (TCI) capture port. It provides the following functions: • Video capture mode: – Capture rate of up to 80 MHZ. – Two channels of 8-bit digital video i...
Page 19 - Video Port FIFO
www.ti.com 1.2 Video Port FIFO 1.2.1 EDMA Interface Video Port FIFO The video port includes a FIFO to store data coming into or out from the video port. The video portoperates in conjunction with EDMA transfers to move data between the video port FIFO and external oron-chip memory. You can program t...
Page 21 - For 8-bit raw video, the FIFO is split into channel A and B, as shown in
www.ti.com VDIN[19−12] 8 Buffer B (2560 bytes) Capture FIFO B YSRCB 64 VDIN[9−2] 8 Buffer A (2560 bytes) Capture FIFO A YSRCA 64 Video Port FIFO For 8-bit raw video, the FIFO is split into channel A and B, as shown in Figure 1-3 . Each FIFO is clocked independently with the channel A FIFO receiving ...
Page 22 - shows how
www.ti.com VDIN[19−12] Cr Buffer (1280 bytes) Cb Buffer (1280 bytes) 8 8 64 64 CRSRCA CBSRCA Y Buffer (2560 bytes) VDIN[9−2] 8 64 Capture FIFO YSRCA Video Port FIFO For Y/C video capture, the FIFO is configured as a single channel split into separate Y, Cb, and Cr bufferswith separate write pointers...
Page 24 - Figure 1-8. 8-Bit Locked Raw Video Display FIFO Configuration
www.ti.com Buffer A (2560 bytes) YDSTA VDOUT[9−2] 64 8 Display FIFO A Buffer B (2560 bytes) YDSTB VDOUT[19−12] 64 8 Display FIFO B Data Buffer (5120 bytes) YDSTA VDOUT[19−2] 64 16 Display FIFO Video Port FIFO For locked raw video, the FIFO is split into channel A and B. The channels are locked toget...
Page 25 - Video Port Registers
www.ti.com Cr Buffer (1280 bytes) Cb Buffer (1280 bytes) CRDST CBDST 64 64 VDOUT[19−12] 8 8 Y Buffer (2560 bytes) YDSTA 64 VDOUT[9−2] Display FIFO 8 1.3 Video Port Registers Video Port Registers For Y/C video display, the FIFO is configured as a single channel split into separate Y, Cb, and Cr buffe...
Page 26 - Video Port Pin Mapping; . Pin functionality detail for video display mode is listed in
www.ti.com 1.4 Video Port Pin Mapping Video Port Pin Mapping The video port requires 21 external signal pins for full functionality. Pin usage and direction changesdepend on the selected operating mode. Pin functionality detail for video capture mode is listed in Table 1-1 . Pin functionality detail...
Page 27 - Table 1-3. VDIN Data Bus Usage for Capture Modes; Capture Mode
www.ti.com 1.4.1 VDIN Bus Usage for Capture Modes Video Port Pin Mapping The alignment and usage of data on the VDIN bus depends on the capture mode as shown in Table 1-3 . Table 1-3. VDIN Data Bus Usage for Capture Modes (1) Capture Mode BT.656 Y/C Raw Data Data Bus 8-Bit 8-Bit 8-Bit 16-Bit TCI Mod...
Page 28 - VDOUT Data Bus Usage for Display Modes; Video Port Pin Multiplexing; Table 1-4. VDOUT Data Bus Usage for Display Modes; Display Mode
www.ti.com 1.4.2 VDOUT Data Bus Usage for Display Modes 1.5 Video Port Pin Multiplexing 1.6 VideoPort Clocking Video Port Pin Multiplexing The alignment and usage of data on the VDOUT bus depends on the display mode as shown in Table 1-4 . Table 1-4. VDOUT Data Bus Usage for Display Modes (1) Displa...
Page 29 - Reset Operation
SPRUEM1 – May 2007 Video Port This chapter discusses the basic operation of the video port. Included is a discussion ofthe sources and types of resets, interrupt operation, EDMA operation, external clockinputs, video port throughput and latency, and the video port control registers. Topic .............
Page 30 - Clears PEREN bit in PCR to 0.
www.ti.com 2.1 Reset Operation 2.1.1 Power-On Reset 2.1.2 Peripheral Bus Reset 2.1.3 Software Port Reset Reset Operation The video port has several sources and types of resets. The actions performed by these resets and thestate of the port following the resets is described in the following sections....
Page 31 - Interrupt Operation
www.ti.com 2.1.4 Capture Channel Reset 2.1.5 Display Channel Reset 2.2 Interrupt Operation Interrupt Operation Note: The VPRST bit may take several clock cycles to clear to 0. The VPRST bit should bepolled to make sure the bit is cleared prior to writing to the video port registers. Once the port is...
Page 32 - EDMA Operation
www.ti.com 2.3 EDMA Operation 2.3.1 Capture EDMA Event Generation EDMA Operation • Display complete not acknowledged (DCNA) bit is set. • GPIO interrupt (GPIO) bit is set. The interrupt signal is a pulse only and does not hold state. The interrupt pulse is generated only when thenumber of set flags ...
Page 33 - EDMA Size and Threshold Restrictions
www.ti.com 2.3.2 Display EDMA Event Generation 2.3.3 EDMA Size and Threshold Restrictions EDMA Operation Display EDMA events are generated based on the amount of room available in the FIFO. The VDTHRLDnvalue indicates the level at which the FIFO has room to receive another EDMA. If the FIFO has at l...
Page 34 - Video Port Control Registers; The video port control registers are listed in; Offset
www.ti.com 2.3.4 EDMA Interface Operation 2.4 Video Port Control Registers Video Port Control Registers When the video port is configured for capture (or TCI) mode, it only accepts read requests from the EDMAinterface. Write requests are false acknowledged (so the bus does not stall) and the data is...
Page 35 - The video port control register (VPCTL) is shown in; Bit; Value
www.ti.com 2.4.1 Video Port Control Register (VPCTL) Video Port Control Registers The video port control register (VPCTL) determines the basic operation of the video port. Not all combinations of the port control bits are unique. The control bit encoding is shown in Table 2-3 . Additional mode optio...
Page 36 - Table 2-3. Video Port Operating Mode Selection
www.ti.com Video Port Control Registers Table 2-2. Video Port Control Register (VPCTL) Field Descriptions (continued) Bit field (1) symval (1) Value Description 5 VCT2P OF(value) VCTL2 pin polarity bit. Does not affect GPIO operation. DEFAULT 0 Indicates the VCTL2 control signal (input or output) is...
Page 37 - The video port status register (VPSTAT) is shown in
www.ti.com 2.4.2 Video Port Status Register (VPSTAT) Video Port Control Registers The video port status register (VPSTAT) indicates the current condition of the video port. The video port status register (VPSTAT) is shown in Figure 2-2 and described in Table 2-4 . Figure 2-2. Video Port Status Regis...
Page 38 - The video port interrupt enable register (VPIE) is shown in
www.ti.com 2.4.3 Video Port Interrupt Enable Register (VPIE) Video Port Control Registers The video port interrupt enable register (VPIE) enables sources of the video port interrupt to the DSP. The video port interrupt enable register (VPIE) is shown in Figure 2-3 and described in Table 2-5 . Figure...
Page 40 - The video port interrupt status register (VPIS) is shown in
www.ti.com 2.4.4 Video Port Interrupt Status Register (VPIS) Video Port Control Registers Table 2-5. Video Port Interrupt Enable Register (VPIE) Field Descriptions (continued) Bit field (1) symval (1) Value Description 3 SERRA OF(value) Channel A synchronization error interrupt enable bit. DEFAULT 0...
Page 46 - Video Capture Mode Selection; The video capture module operates in one of five modes as listed in; TCI Bit
www.ti.com 3.1 Video Capture Mode Selection 3.2 BT.656 Video Capture Mode 3.2.1 BT.656 Capture Channels 3.2.2 BT.656 Timing Reference Codes Video Capture Mode Selection The video capture module operates in one of five modes as listed in Table 3-1 . The transport channel interface (TCI) selection is ...
Page 47 - BT.656 Video Capture Mode; Data Bit; Line Information Bits; . The - entries indicate detected double bit errors that; Table 3-4. Error Correction by Protection Bits; Received P
www.ti.com BT.656 Video Capture Mode Table 3-2. BT.656 Video Timing Reference Codes Data Bit 1 st Byte (FFh) 2 nd Byte (00h) 3 rd Byte (00h) 4 th Byte (XYh) 9 (MSB) 1 0 0 1 8 1 0 0 F (field) (1) 7 1 0 0 V (vertical blanking) (2) 6 1 0 0 H (horizontal blanking) (3) 5 1 0 0 P3 (protection bit 3) (4) 4...
Page 48 - lines per field, and the number of active pixels per line.
www.ti.com 3.2.3 BT.656 Image Window and Capture Capture Image Ystart Xstart Ystop Xstop Field 1 Capture Image Ystart Xstart Ystop Xstop Field 2 Hcount=0 Ycount=1 Ycount=1 BT.656 Video Capture Mode Table 3-4. Error Correction by Protection Bits (continued) Received F, V, and H Bits Received P 3 -P 0...
Page 49 - Table 3-5. Common Video Source Parameters; Number of Active Lines
www.ti.com 3.2.4 BT.656 Data Sampling 3.2.5 BT.656 FIFO Packing BT.656 Video Capture Mode Table 3-5. Common Video Source Parameters Number of Active Lines Video Source (Field 1/Field 2) Number of Active Pixels Field Rate (Hz) square pixel 240/240 640 60 60 Hz/525 lines BT.601 244/243 720 60 60 Hz/52...
Page 50 - Y/C Video Capture Mode
www.ti.com Cr 1 Cr 9 Cb 1 Cb 9 Y 1 Y 9 Y 17 Y 25 Cr 2 Cr FIFO Little-Endian Packing Cr 6 Cr 14 Cb 6 Cb 14 Y 6 Y 14 Y 22 Y 30 Cb 0 Y 23 Cr 7 Cr 15 63 Cb 7 Cb 15 63 Y 7 Y 15 Cb FIFO Y FIFO 55 56 55 56 Y 31 63 VCLKINA / VCLKINB VDIN[9−2] / VDIN[9−12] 55 56 Cr 4 Cr 12 Cb 4 Cb 12 Y 4 Y 12 Y 20 Y 28 Y 2 Y...
Page 51 - BT.656 and Y/C Mode Field and Frame Operation
www.ti.com 3.3.4 Y/C FIFO Packing Cr 9Cr 1 Cb 9Cb 1 Y 9Y 1 Y 25Y 17 Cb 5 Y 10 Little-Endian Packing Cr 14 Cr 6 Y 0 Cb 0 Cb 14 Cb 6 Y 14 Y 6 Y 30Y 22 Y 23 Cr 15 Cr 7 Cb 15 Cb 7 Y 15 Y 7 Cr FIFO Cb FIFO 63 Y FIFO 63 55 56 55 56 Y 31 63 VDIN[19−12] 55 56 VCLKINA VDIN[9−2] Cr 11 Cr 3 Cb 11 Cb 3 Y 11 Y 3...
Page 52 - Capture Determination and Notification; CON
www.ti.com 3.4.1 Capture Determination and Notification BT.656 and Y/C Mode Field and Frame Operation to which a continuous stream of fields are stored without DSP intervention. In other cases, the DSP mayneed to modify EDMA pointer addresses after each field or frame is captured. In some applicatio...
Page 53 - Table 3-7. Vertical Synchronization Programming; ) and allows the VCYSTARTn bit to be set to 1, but
www.ti.com 3.4.2 Vertical Synchronization BT.656 and Y/C Mode Field and Frame Operation Table 3-6. BT.656 and Y/C Mode Capture Operation (continued) VCxCTL Bit CON FRAME CF2 CF1 Operation 1 0 0 1 Continuous field 1 capture. Capture only field 1. F1C is set after field 1capture and causes CCMPx to be...
Page 55 - Table 3-8. Horizontal Synchronization Programming; for VCTL
www.ti.com 3.4.3 Horizontal Synchronization VDIN[9−2] 80.0 80.0 10.0 FF .C 00.0 00.0 Cb 0 Y 2 Cb 359 Cr 359 Y 719 Y 0 Cr 0 Y 1 Cb 1 One Line XY .0 10.0 80.0 10.0 FF .C 00.0 00.0 XY .0 80.0 80.0 10.0 FF .C 00.0 00.0 XY .0 10.0 855 856 857 0 1 2 718 719 720 721 722 723 720 721 722 723 HCOUNT SAV EAV B...
Page 56 - Table 3-9. Field Identification Programming; EXC
www.ti.com n n n 140 2 60 n 1440 Active Video 124 Y 2 Blanking Data 1 721 779 843 VCOUNT VCOUNT EXC=1 HRST=1 EXC=1 HRST=0 HCOUNT 720 HCOUNT VCOUNT 0 AVID EXC=1 HRST=0 EXC=1 HRST=1 HCOUNT 842 HCOUNT VCOUNT 778 HSYNC 79 799 857 63 n−1 15 735 722 2 736 n−1 16 793 857 844 780 n−1 0 794 136 856 855 800 8...
Page 57 - Video Input Filtering
www.ti.com ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ HSYNC# (VCTL1) VCLKIN VSYNC# (VCTL2) 64 Clocks 64 Clocks 3.4.5 Short and Long Field Detect 3.5 Video Input Filtering Video Input Filtering The field indicator method uses the FID input directly to ...
Page 58 - Cr’; CMODE
www.ti.com 3.5.1 Input Filter Modes 3.5.2 Chrominance Re-sampling Operation YCbCr 4:2:2 co-sited input samples chroma-resampled capture results Luma (Y)sample - Chroma (Cb/Cr)samples a b c d e f g h i j k l Cb’ ef = (-3Cb c + 101Cb e + 33Cb g -3Cb i ) / 128 Cr’ ef = (-3Cr c + 101Cr e + 33Cr g - 3Cr ...
Page 59 - and scaling for chrominance re-sampling is
www.ti.com YCbCr 4:2:2 co-sited input samples 1/2 scaled co-sited capture results Luma (Y)sample Y’ h = (-3Y e + 32Y g + 70Y h + 32Y i - 3Y k ) / 128 - Chroma (Cb/Cr)samples - a b c d e f g h i j k l Y’ f = (-3Y c + 32Y e + 70Y f + 32Y g - 3Y i ) / 128 Cb’ f = (-1Cb c + 17Cb e + 17Cb g - 1Cb i ) / 3...
Page 60 - Ancillary Data Capture; Figure 3-12. Capture Window Not Requiring Edge Pixel Replication
www.ti.com a Luma (Y)sample - Chroma (Cb/Cr)samples - b c d e d c b n - 1 n n - 1 n - 2 n - 3 n - 4 n - 3 n - 2 a b c d e SAV n - 1 n EAV n - 4 n - 3 n - 2 Leading edge replicated pixels Trailing edge replicated pixels Active line a Luma (Y) sample - Chroma (Cb/Cr) samples - b c d e a-4 a-3 a-1 n-1 ...
Page 61 - Raw Data Capture Mode
www.ti.com 3.6.1 Horizontal Ancillary (HANC) Data Capture 3.6.2 Vertical Ancillary (VANC) Data Capture 3.7 Raw Data Capture Mode 3.7.1 Raw Data Capture Notification Raw Data Capture Mode No special provisions are made for the capture of HANC data. HANC data may be captured using thenormal video capt...
Page 62 - Table 3-11. Raw Data Mode Capture Operation
www.ti.com 3.7.2 Raw Data FIFO Packing Raw FIFO VDIN[9−2] / VDIN[19−12] VCLKINA / VCLKINB 63 56 55 48 47 40 39 32 Raw 5 Raw 4 Raw 7 Raw 6 Raw 13 Raw 12 Raw 15 Raw 14 Little-Endian Packing 31 24 23 16 15 8 7 0 Raw 1 Raw 0 Raw 3 Raw 2 Raw 9 Raw 8 Raw 11 Raw 10 Raw Data Capture Mode For channel B opera...
Page 63 - TCI Capture Mode
www.ti.com Raw FIFO VDIN[19−12] / VDIN[9−2] VCLKINA 63 4847 32 Raw 2 Raw 3 Raw 6 Raw 7 Little-Endian Packing 31 1615 0 Raw 0 Raw 1 Raw 4 Raw 5 Raw 10 Raw 11 Raw 8 Raw 9 3.8 TCI Capture Mode 3.8.1 TCI Capture Features 3.8.2 TCI Data Capture TCI Capture Mode Figure 3-14. 16-Bit Raw Data FIFO Packing T...
Page 65 - shows the system time clock counter operation.; Figure 3-17. System Time Clock Counter Operation; VCACTL Bit
www.ti.com 27 MHz Modulo 300 Counter 233 PCR Extension PCR Base CTMODE 0 1 STCLK 90 kHz External VCXO 3.8.5 TCI Data Capture Notification TCI Capture Mode counter counts from 0 to 299 at 27 MHz. Each time the 9-bit counter rolls over to 0, the 33-bit counter isincremented by 1. This is equivalent to...
Page 67 - Capture Line Boundary Conditions; In; Figure 3-20. Capture Line Boundary Example
www.ti.com 3.9 Capture Line Boundary Conditions Y FIFO Cb FIFO VDOUT[9−2] VCLKOUT 63 56 55 48 47 40 39 32 Y 5 Y 4 Y 7 Y 6 Y 69 Y 68 Y 71 Y 70 Y 77 Y 76 Cb 37 Cb 36 Cb 38 Little-Endian Packing Cb 36 Cb 37 Cb 38 CbDEF Cr 36 Cr 37 Cr 38 CrDEF VDOUT[19−12] CbDEF CbDEF CrDEF CrDEF 31 24 23 16 15 8 7 0 Y ...
Page 68 - Capturing Video in Raw Data Mode; Set VCEN bit to enable capture.
www.ti.com 3.10.1 Handling FIFO Overrun in BT.656 or Y/C Mode 3.11 Capturing Video in Raw Data Mode Capturing Video in Raw Data Mode number specified by the threshold fields (VCTHRLDx) in the threshold register, a YEVTx, CbEVTx, andCrEVTx are generated by the video capture module. 7. Configure an ED...
Page 69 - Handling FIFO Overrun Condition in Raw Data Mode; Capturing Data in TCI Capture Mode
www.ti.com 3.11.1 Handling FIFO Overrun Condition in Raw Data Mode 3.12 Capturing Data in TCI Capture Mode Capturing Data in TCI Capture Mode 5. Write to VCxTHRLD to set the capture threshold. The threshold needs to be set in units of double word. One double word is equal to 8 bytes. Every time the ...
Page 70 - Handling FIFO Overrun Condition in TCI Capture Mode; Video Capture Registers; based on STC absolute time.; Table 3-13. Video Capture Control Registers
www.ti.com 3.12.1 Handling FIFO Overrun Condition in TCI Capture Mode 3.13 Video Capture Registers Video Capture Registers 5. Write to TCISTCMPL, TCISTCMPM, TCISTMSKL, and TCISTMSKM if needed to initiate an interrupt, based on STC absolute time. 6. Write to TCITICKS if an interrupt is desired every ...
Page 71 - and
www.ti.com 3.13.1 Video Capture Channel x Status Register (VCASTAT, VCBSTAT) Video Capture Registers Table 3-13. Video Capture Control Registers (continued) Offset Address (1) Acronym Register Name Section 154h VCBSTOP2 Video Capture Channel B Field 2 Stop Register Section 3.13.6 158h VCBVINT Video ...
Page 72 - Description; and described in
www.ti.com 3.13.2 Video Capture Channel A Control Register (VCACTL) Video Capture Registers Table 3-14. Video Capture Channel x Status Register (VCxSTAT) Field Descriptions Description Bit field (1) symval (1) Value BT.656 or Y/C Mode Raw Data Mode TCI Mode 31 FSYNC OF(value) Current frame sync bit....
Page 86 - The TCI system time clock LSB register (TCISTCLKL) is shown in
www.ti.com 3.13.13 TCI Clock Initialization MSB Register (TCICLKINITM) 3.13.14 TCI System Time Clock LSB Register (TCISTCLKL) Video Capture Registers The transport stream interface clock initialization MSB register (TCICLKINITM) is used to initialize thehardware counter to synchronize with the syste...
Page 87 - The TCI system time clock MSB register (TCISTCLKM) is shown in
www.ti.com 3.13.15 TCI System Time Clock MSB Register (TCISTCLKM) Video Capture Registers Figure 3-34. TCI System Time Clock LSB Register (TCISTCLKL) 31 0 PCR R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-27. TCI System Time Clock LSB Register (TCISTCLKL) Field Descri...
Page 88 - and described
www.ti.com 3.13.16 TCI System Time Clock Compare LSB Register (TCISTCMPL) 3.13.17 TCI System Time Clock Compare MSB Register (TCISTCMPM) Video Capture Registers The transport stream interface system time clock compare LSB register (TCISTCMPL) is used to generatean interrupt at some absolute time bas...
Page 91 - Video Capture FIFO Registers; The capture FIFO mapping registers are listed in; Table 3-35. Video Capture FIFO Registers Function
www.ti.com 3.14 Video Capture FIFO Registers Video Capture FIFO Registers The capture FIFO mapping registers are listed in Table 3-34 . These registers provide read access to the capture FIFOs. These pseudo-registers should be mapped into DSP memory space rather thanconfiguration register space in o...
Page 93 - Field 1; Video Display Mode Selection; . The DMODE bits are in; DMODE Bits; compatible) is shown in; Figure 4-1. NTSC Compatible Interlaced Display
www.ti.com 4.1 Video Display Mode Selection 4.1.1 Image Timing Line 20 Line 21 Line 22 Line 261 Line 262 Line 263 Line 282 Line 283 Line 284 Line 523 Line 524 Line 525 Field 1 Field 2 Video Display Mode Selection The video display module operates in one of three modes as listed in Table 4-1 . The DM...
Page 94 - Figure 4-2. SMPTE 296M Compatible Progressive Scan Display
www.ti.com Line 26 Line 28 Line 30 Line 742 Line 744 Field 1 Line 27 Line 29 Line 745 Line 743 Line 741 Video Display Mode Selection Figure 4-2. SMPTE 296M Compatible Progressive Scan Display 94 Video Display Port SPRUEM1 – May 2007 Submit Documentation Feedback
Page 95 - Figure 4-3. Interlaced Blanking Intervals and Video Areas
www.ti.com Field 1 Vertical Blanking Horizontal Blanking Field 1 Image Horiz. Of fset Field 1 Image Vertical Offset Field 1 Image Width Field 1 Image Height Field 1 Active Video Field 1 Frame Field 2 Vertical Blanking Horizontal Blanking Field 2 Image Horiz. Of fset Field 2 Image Vertical Offset Fie...
Page 96 - Figure 4-4. Progressive Blanking Intervals and Video Area
www.ti.com Field 1 Image Width Field 1 Frame Field 1 Image Horizontal Of fset Field 1 Image Height Horizontal Blanking Field 1 Vertical Blanking Field 1 Image Vertical Offset Field 1 Active Video 4.1.2 Video Display Counters Video Display Mode Selection Figure 4-4. Progressive Blanking Intervals and...
Page 97 - Figure 4-5. Horizontal Blanking and Horizontal Sync Timing
www.ti.com 718 FPCOUNT HBLNK HSYNC 719 720 735 736 799 800 857 0 1 FPCOUNT = HBLNKSTART FPCOUNT = HBLNKSTOP FPCOUNT = HSYNCSTOP FPCOUNT = HSYNCSTART FLCOUNT VBLNK VSYNC FLCOUNT = VSYNCYSTOP1 FPCOUNT = VSYNCXSTOP1 263 264 265 18 19 20 5 6 7 266 282 283 284 524 525 1 2 3 4 5 267 268 269 270 FLD FLCOUN...
Page 98 - BT.656 Video Display Mode; Figure 4-7. Video Display Module Synchronization Chain
www.ti.com 4.1.3 Sync Signal Generation 4.1.4 External Sync Operation 4.1.5 Port Sync Operation Video port 0 display Can sync to Video port 1 display Can sync to Video port 2 display 4.2 BT.656 Video Display Mode Cb0 Y0 Cr0 Y1 Cb1 Y2 Cr1 Y3 Cb2 Y4 VDOUT[9−2] VCLKOUT BT.656 Video Display Mode The vid...
Page 99 - The BT.656 line timing is shown in
www.ti.com 4.2.1 Display Timing Reference Codes VDOUT[9−2] 80.0 80.0 10.0 FF .C 00.0 00.0 Cb 0 Y 2 Cb 359 Y 718 Cr 359 Y 719 Y 0 Cr 0 Y 1 Cb 1 One Line XY .0 10.0 80.0 10.0 FF .C 00.0 00.0 XY .0 80.0 80.0 10.0 FF .C 00.0 00.0 XY .0 10.0 855 856 857 0 1 2 718 719 720 721 722 723 720 721 722 723 FPCOU...
Page 100 - The typical values for H, V, and F on different lines are shown in; Line Number; Figure 4-11. Digital Vertical F and V Transitions
www.ti.com Blanking Optional blanking Line 4 Image: Field 1 Blanking Line 266 Optional blanking Image: Field 2 Line 3 H = 1 (EAV) H = 0 (SAV) 1(V = 1) 10 (V = X) 20 (V = 0) 264 (V = 1) 273 (V = X) 283 (V = 0) 525 (V = 0) Blanking Image: Field 1 Blanking Image: Field 2 H = 1 (EAV) H = 0 (SAV) 1(V = 1...
Page 102 - Y/C Video Display Mode
www.ti.com 4.3 Y/C Video Display Mode 4.3.1 Y/C Display Timing Reference Codes VDOUT[9−2] 80.0 80.0 80.0 FF .C 00.0 00.0 Y 0 Y 5 Y 1916 Y 1917 Y 1918 Y 1919 Y 1 Y 2 Y 3 Y 4 One Line XY .0 80.0 10.0 10.0 FF .C 00.0 00.0 XY .0 80.0 80.0 80.0 FF .C 00.0 00.0 XY .0 80.0 FPCOUNT SAV EAV Blanking Data EAV...
Page 103 - Video Output Filtering; VDCTL Bit
www.ti.com 4.3.4 Y/C FIFO Unpacking Y FIFO Cb FIFO Y 2 Y 4 Y 6 Y 1 Y 3 Y 5 Y 7 VDOUT[9−2] VCLKOUT 63 56 55 48 47 40 39 32 Y 21 Y 20 Y 23 Y 22 Y 29 Y 28 Y 31 Y 30 Y 5 Y 4 Y 7 Y 6 Y 13 Y 12 Y 15 Y 14 Cb 5 Cb 4 Cb 7 Cb 6 Cb 13 Cb 12 Cb 15 Cb 14 Cr FIFO Little-Endian Unpacking Y 8 Y 10 Y 9 Y 11 Cb 0 Cb ...
Page 104 - and scaling for interspersed
www.ti.com 4.4.2 Chrominance Re-sampling Operation YCbCr 4:2:2 interspersed source pixels YCbCr 4:2:2 co-sited output results Luma (Y) sample Cb’ f = (-3Cb ab + 33Cb cd + 101Cb ef - 3Cb gh ) / 128 Cr’ f = (-3Cr ab + 33Cr cd + 101Cr ef - 3Cr gh ) / 128 Chroma (Cb/Cr)samples - a b c d e f g h i j k l ...
Page 105 - Figure 4-18. Output Edge Pixel Replication
www.ti.com 2x upscaled YCbCr 4:2:2 co-sited output YCbCr 4:2:2 interspersed source pixels Luma (Y)sample Cb’ d = (-3Cb ab + 101Cb cd + 33Cb ef - 3Cb gh ) / 128 Cr’ d = (-3Cr ab + 101Cr cd + 33Cr ef - 3Cr gh ) / 128 - Chroma (Cb/Cr)samples - a a’ b b’ c c’ d d’ e e’ f f’ a b c d e f g g Y’ a = Y a Cb...
Page 106 - Ancillary Data Display; Figure 4-20. Interspersed Chroma Edge Replication
www.ti.com a a’ b b’ c c’ d w w’ x x’ a b c d w x y y Cb’ a = (-3Cb cd + 33Cb ab + 101Cb ab -3Cb cd )/128 Cr’ a = (-3Cr cd + 33Cr ab + 101Cr ab -3Cr cd )/128 y’ ab cd z Horizontal Image Size Trailing edge replicated chroma samples wx yz z z’ yz wx ab cd Cb’ b = (-3Cb ab + 101Cb ab + 33Cb cd -3Cb ef ...
Page 107 - Raw Data Display Mode; FIFO Unpacking
www.ti.com 4.6.1 Raw Mode RGB Output Support 4.6.2 Raw Data FIFO Unpacking Raw FIFO VDOUT[9−2] VCLKOUT 63 56 55 48 47 40 39 32 Raw 5 Raw 4 Raw 7 Raw 6 Raw 13 Raw 12 Raw 15 Raw 14 Little-Endian Unpacking 31 24 23 16 15 8 7 0 Raw 1 Raw 0 Raw 3 Raw 2 Raw 9 Raw 8 Raw 11 Raw 10 Raw FIFO VDOUT[19−12]/VDOU...
Page 108 - Display Determination and Notification; Video Display Field and Frame Operation
www.ti.com 4.7 Video Display Field and Frame Operation 4.7.1 Display Determination and Notification Video Display Field and Frame Operation As a video source, the video port always outputs entire frames of data and transmits continuous videocontrol signals. Depending on the EDMA structure, however, ...
Page 109 - Display Line Boundary Conditions
www.ti.com 4.7.2 Video Display Event Generation 4.8 Display Line Boundary Conditions Display Line Boundary Conditions Table 4-4. Display Operation (continued) VDCTL Bit CON FRAME DF2 DF1 Operation 0 1 1 1 Single frame display. Display both fields. FRMD is set after field 2 display andcauses DCMPx to...
Page 110 - Display Timing Examples; Figure 4-24. Display Line Boundary Example; The horizontal output timing is shown in
www.ti.com Y FIFO Cb FIFO VDOUT[9−2] VCLKOUT 63 5655 4847 4039 32 Y 5 Y 4 Y 7 Y 6 Y 69 Y 68 Y 71 Y 70 Y 77 Y 76 Cb 37 Cb 36 Cb 38 Little-Endian Packing VDOUT[19−12] 31 2423 1615 8 7 0 Y 1 Y 0 Y 3 Y 2 Y 65 Y 64 Y 67 Y 66 Y 73 Y 72 Y 75 Y 74 31 2423 1615 8 7 0 Cb 33 Cb 32 Cb 35 Cb 34 63 5655 4847 4039...
Page 111 - Figure 4-25. BT.656 Interlaced Display Horizontal Timing Example
www.ti.com 720 721 722 723 735 736 799 800 855 856 857 0 1 7 8 9 10 710 711 712 718 719 720 721 703 703 703 703 703 703 703 703 703 703 703 703 0 1 2 702 703 703 703 703 703 703 n + 1 n FLCOUNT VCLKOUT VCTL1 (HBLNK ) (A)(C) IPCOUNT FPCOUNT VCLKIN VCTL1 (HSYNC) (A)(C) VDOUT[9−2] n − 1 4 268 4 1440 On...
Page 112 - The interlaced BT.656 vertical output timing is shown in
www.ti.com Display Timing Examples The interlaced BT.656 vertical output timing is shown in Figure 4-26 . The BT.656 active field 1 is 244-lines high and active field 2 is 243-lines high. This example shows the 480-line image window centered in thescreen. This results in an IMGVOFFn of 3 lines and a...
Page 113 - Figure 4-26. BT.656 Interlaced Display Vertical Timing Example
www.ti.com 525 2 1 4 3 6 5 19 Field 1 active Field 1 image 20 21 22 23 262 263 264 265 266 267 268 269 282 Field 2 active 283 284 285 286 Field 2 image 524 525 1 Field 1 blanking 1 2 1 2 239 240 240 240 240 240 240 240 240 240 240 240 240 240 240 239 240 240 240 240 240 240 240 240 240 240 240 240 I...
Page 114 - Figure 4-27. Raw Interlaced Display Horizontal Timing Example
www.ti.com É É É É É ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ É É É É É É É É É É É É É É É ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ É É É É É É É É É É ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ É É É É É ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ É É É É É ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ FLCOUNT VDOUT[19−2 ](B) VCLKOUT VCLKIN IPCOUNT VCTL1 (HBLNK) (A)(B) VCTL1 (HSYNC) (A)(B) ...
Page 115 - The vertical output timing for raw mode is shown in; Figure 4-28. Raw Interlaced Display Vertical Timing Example
www.ti.com 525 2 1 4 3 6 5 19 Field 1 active Field 1 image 20 21 22 23 262 263 264 265 266 267 268 269 282 Field 2 active 283 284 285 286 Field 2 image 524 525 1 Field 1 blanking 1 2 1 2 239 240 240 240 240 240 240 240 240 240 240 240 240 240 240 239 240 240 240 240 240 240 240 240 240 240 240 240 I...
Page 117 - Figure 4-29. Y/C Progressive Display Horizontal Timing Example
www.ti.com (B) É É É É É VCLKIN FPCOUNT IPCOUNT VCTL1 (HBLNK) (A)(C) VCTL1 (HSYNC) (A)(C) VCLKOUT VDOUT[9−2] (C) VDOUT[19−2] (C) FLCOUNT n − 1 n + 1 n EAV Blanking Data SAV EAV Blanking Active Video Display Image 4 362 4 1280 One Line Next Line 1 2 8 0 1 2 8 1 1 2 8 2 1 2 8 3 1 2 8 4 1 2 8 5 1 2 8 6...
Page 118 - The vertical output timing is shown in
www.ti.com ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÇÇÇÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇ 5 FLCOUNT 750 716 716 ILCOUNT Field 1 Blanking Field 1 Blanking Field 1 Active 4 3 2 1 716716716716 252627 716716716 745746747748749 716716716716716 2829 Field 1 Image 744 12 716 715 V F 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 ...
Page 120 - Displaying Video in Raw Data Mode
www.ti.com 4.11 Displaying Video in Raw Data Mode Displaying Video in Raw Data Mode 22. Wait for 2 or more frame times, to allow the display counters and control signals to become properly synchronized. 23. Write to VDCTL to clear the BLKDIS bit.24. Display is enabled at the start of the first frame...
Page 121 - by total double words per Y EDMA.
www.ti.com 4.11.1 Handling Under-run Condition of the Display FIFO Displaying Video in Raw Data Mode by total double words per Y EDMA. 20. Write to VPIE to enable under-run (DUND) and display complete (DCMP) interrupts, if desired.21. Write to VDTHRLD to set the display FIFO threshold (VDTHRLD bits)...
Page 122 - Video Display Registers; Table 4-5. Video Display Control Registers; The video display status register (VDSTAT) is shown in
www.ti.com 4.12 Video Display Registers 4.12.1 Video Display Status Register (VDSTAT) Video Display Registers The registers for controlling the video display mode of operation are listed in Table 4-5 . See the device-specific datasheet for the memory address of these registers. Table 4-5. Video Disp...
Page 124 - The video display control register (VDCTL) is shown in
www.ti.com Video Display Registers The video display is controlled by the video display control register (VDCTL). The video display control register (VDCTL) is shown in Figure 4-32 and described in Table 4-7 . Figure 4-32. Video Display Control Register (VDCTL) 31 30 29 28 27 24 RSTCH BLKDIS Reserve...
Page 127 - The video display frame size register (VDFRMSZ) is shown in
www.ti.com 4.12.3 Video Display Frame Size Register (VDFRMSZ) 4.12.4 Video Display Horizontal Blanking Register (VDHBLNK) Video Display Registers The video display frame size register (VDFRMSZ) sets the display channel frame size by setting theending values for the frame line counter (FLCOUNT) and t...
Page 133 - The video display field 1 image size register (VDIMGSZ1) is shown in
www.ti.com 4.12.10 Video Display Field 1 Image Size Register (VDIMGSZ1) Video Display Registers Table 4-14. Video Display Field 1 Image Offset Register (VDIMGOFF1) Field Descriptions (continued) Description Bit field (1) symval (1) Value BT.656 and Y/C Mode Raw Data Mode 11-0 IMGHOFF1 OF(value) 0-FF...
Page 135 - The video display field 2 image size register (VDIMGSZ2) is shown in
www.ti.com 4.12.12 Video Display Field 2 Image Size Register (VDIMGSZ2) 4.12.13 Video Display Field 1 Timing Register (VDFLDT1) Video Display Registers The video display field 2 image size register (VDIMGSZ2) defines the field 2 image area and specifies thesize of the displayed image within the acti...
Page 136 - The video display field 2 timing register (VDFLDT2) is shown in
www.ti.com 4.12.14 Video Display Field 2 Timing Register (VDFLDT2) Video Display Registers Figure 4-43. Video Display Field 1 Timing Register (VDFLDT1) 31 28 27 16 Reserved FLD1YSTART R-0 R/W-0 15 12 11 0 Reserved FLD1XSTART R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset T...
Page 137 - The video display threshold register (VDTHRLD) is shown in
www.ti.com 4.12.15 Video Display Threshold Register (VDTHRLD) Video Display Registers Table 4-19. Video Display Field 2 Timing Register (VDFLDT2) Field Descriptions (continued) Bit field (1) symval (1) Value Description 11-0 FLD2XSTART OF(value) 0-FFFh Specifies the pixel on the first line of field ...
Page 138 - Generation of the horizontal synchronization is shown in; Generation of the vertical synchronization is shown in
www.ti.com 4.12.16 Video Display Horizontal Synchronization Register (VDHSYNC) 4.12.17 Video Display Field 1 Vertical Synchronization Start Register (VDVSYNS1) Video Display Registers Table 4-20. Video Display Threshold Register (VDTHRLD) Field Descriptions (continued) Description Bit field (1) symv...
Page 139 - Descriptions
www.ti.com 4.12.18 Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1) Video Display Registers The video display field 1 vertical synchronization start register (VDVSYNS1) is shown in Figure 4-47 and described in Table 4-22 . Figure 4-47. Video Display Field 1 Vertical Synchroniza...
Page 141 - The video display counter reload register (VDRELOAD) is shown in
www.ti.com 4.12.21 Video Display Counter Reload Register (VDRELOAD) Video Display Registers Figure 4-50. Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2) 31 28 27 16 Reserved VSYNCYSTOP2 R-0 R/W-0 15 12 11 0 Reserved VSYNCXSTOP2 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only...
Page 142 - The video display event register (VDDISPEVET) is shown in; The video display clipping register (VDCLIP) is shown in
www.ti.com 4.12.22 Video Display Event Register (VDDISPEVT) 4.12.23 Video Display Clipping Register (VDCLIP) Video Display Registers The video display event register (VDDISPEVT) is programmed with the number of EDMA events to begenerated for display field 1 and field 2. The video display event regis...
Page 143 - for the raw data mode, and described in
www.ti.com 4.12.24 Video Display Default Display Value Register (VDDEFVAL) Video Display Registers Figure 4-53. Video Display Clipping Register (VDCLIP) 31 24 23 16 CLIPCHIGH CLIPCLOW R/W-1111-0000 R/W-0001-0000 15 8 7 0 CLIPYHIGH CLIPYLOW R/W-1110-1011 R/W-0001-0000 LEGEND: R/W = Read/Write; R = Re...
Page 144 - The video display field bit register (VDVINT) is shown in
www.ti.com 4.12.25 Video Display Vertical Interrupt Register (VDVINT) Video Display Registers Figure 4-54. Video Display Default Display Value Register (VDDEFVAL) 31 24 23 16 CRDEFVAL CBDEFVAL R/W-0 R/W-0 15 8 7 0 Reserved YDEFVAL R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after...
Page 145 - The video display field bit register (VDFBIT) is shown in
www.ti.com 4.12.26 Video Display Field Bit Register (VDFBIT) Video Display Registers Figure 4-56. Video Display Vertical Interrupt Register (VDVINT) 31 30 28 27 16 VIF2 Reserved VINT2 R/W-0 R-0 R/W-0 15 14 12 11 0 VIF1 Reserved VINT1 R/W-0 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = valu...
Page 148 - Video Display Registers Recommended Values; Table 4-34. Video Display Register Recommended Values
www.ti.com 4.13 Video Display Registers Recommended Values Video Display Registers Recommended Values Table 4-33. Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2) Field Descriptions (continued) Description Bit field (1) symval (1) Value BT.656 and Y/C Mode Raw Data Mode 11-0 VBITSET2 O...
Page 149 - Video Display FIFO Registers; The display FIFO mapping registers are listed in; Table 4-36. Video Display FIFO Registers Function
www.ti.com 4.14 Video Display FIFO Registers Video Display FIFO Registers The display FIFO mapping registers are listed in Table 4-35 . These registers provide EDMA write access to the display FIFOs. These pseudo-registers should be mapped into DSP memory space rather thanconfiguration register spac...
Page 150 - GPIO Registers
SPRUEM1 – May 2007 General-Purpose I/O Operation Signals not used for video display or video capture can be used as general-purposeinput/output (GPIO) signals. Topic .................................................................................................. Page 5.1 GPIO Registers ..............
Page 151 - . See the device-specific datasheet for the memory address of; Offset Address
www.ti.com 5.1 GPIO Registers GPIO Registers The GPIO register set includes required registers such as peripheral identification and emulation control.The GPIO registers are listed in Table 5-1 . See the device-specific datasheet for the memory address of these registers. Table 5-1. Video Port Regis...
Page 153 - The video port peripheral control register (PCR) is shown in
www.ti.com 5.1.2 Video Port Peripheral Control Register (PCR) GPIO Registers The video port peripheral control register (PCR) determines operation during emulation. Normal operation is to not halt the port during emulation suspend. This allows a displayed image to remainvisible during suspend. Howev...
Page 154 - The video port pin function register (PFUNC) is shown in
www.ti.com 5.1.3 Video Port Pin Function Register (PFUNC) GPIO Registers The video port pin function register (PFUNC) selects the video port pins as GPIO. Each bit controls eitherone pin or a set of pins. When a bit is set to 1, it enables the pin(s) that map to it as GPIO. The GPIOfeature should no...
Page 156 - The video port pin direction register (PDIR) is shown in; Value Description
www.ti.com 5.1.4 Video Port Pin Direction Register (PDIR) GPIO Registers The PDIR controls the direction of IO pins in the video port for those pins set by PFUNC. If a bit is set to1, the relevant pin or pin group acts as an output. If a bit is cleared to 0, the pin or pin group functions asan input...
Page 158 - The read-only video port pin data input register (PDIN) is shown in
www.ti.com 5.1.5 Video Port Pin Data Input Register (PDIN) GPIO Registers PDIN reflects the state of the video port pins. When read, PDIN returns the value from the pin's inputbuffer (with appropriate synchronization) regardless of the state of the corresponding PFUNC or PDIR bit. The read-only vide...
Page 159 - PDOUT has these aliases:
www.ti.com 5.1.6 Video Port Pin Data Output Register (PDOUT) GPIO Registers The bits of PDOUT determine the value driven on the corresponding GPIO pin, if the pin is configured asan output. Writes do not affect pins not configured as GPIO outputs. The bits in PDOUT are set or clearedby writing to th...
Page 161 - The video port pin data set register (PDSET) is shown in
www.ti.com 5.1.7 Video Port Pin Data Set Register (PDSET) GPIO Registers PDSET is an alias of the video port pin data output register (PDOUT) for writes only and provides analternate means of driving GPIO outputs high. Writing a 1 to a bit of PDSET sets the corresponding bit inPDOUT. Writing a 0 has...
Page 162 - The video port pin data clear register (PDCLR) is shown in
www.ti.com 5.1.8 Video Port Pin Data Clear Register (PDCLR) GPIO Registers PDCLR is an alias of the video port pin data output register (PDOUT) for writes only and provides analternate means of driving GPIO outputs low. Writing a 1 to a bit of PDCLR clears the corresponding bit inPDOUT. Writing a 0 ...
Page 163 - The video port pin interrupt enable register (PIEN) is shown in
www.ti.com 5.1.9 Video Port Pin Interrupt Enable Register (PIEN) GPIO Registers The GPIOs can be used to generate DSP interrupts or EDMA events. The PIEN selects which pins maybe used to generate an interrupt. Only pins whose corresponding bits in PIEN are set may cause theircorresponding PISTAT bit...
Page 164 - The video port pin interrupt polarity register (PIPOL) is shown in
www.ti.com 5.1.10 Video Port Pin Interrupt Polarity Register (PIPOL) GPIO Registers The PIPOL determines the GPIO pin signal polarity that generates an interrupt. The video port pin interrupt polarity register (PIPOL) is shown in Figure 5-10 and described in Table 5-11 . Figure 5-10. Video Port Pin ...
Page 165 - The video port pin interrupt status register (PISTAT) is shown in
www.ti.com 5.1.11 Video Port Pin Interrupt Status Register (PISTAT) GPIO Registers PISTAT is a read-only register that indicates the GPIO pin that has a pending interrupt. A bit in PISTAT is set when the corresponding GPIO pin is configured as an interrupt (the correspondingbit in PIEN is set, the p...
Page 166 - The video port pin interrupt clear register (PICLR) is shown in
www.ti.com 5.1.12 Video Port Pin Interrupt Clear Register (PICLR) GPIO Registers PICLR is an alias of the video port pin interrupt status register (PISTAT) for writes only. Writing a 1 to a bitof PICLR clears the corresponding bit in PISTAT. Writing a 0 has no effect. Register reads return all 0s. T...
Page 168 - The VIC port supports following features:; VIC Port Signal
www.ti.com 6.1 Overview 22 k Ω 100 pF 5V DC 2.2 k Ω 0.1mF VCXO 27 MHz VDAC VIC STCLK VDATA[7−0] (TSI data in) VCLK1 (TSI clock) VCTL1 (CAPENA) VCTL2 (PACSTRT) VCTL3 (PACERR) Satellite/ cable decoder with FEC Video port A DSP 6.2 Interface Overview The VCXO interpolated control (VIC) port provides si...
Page 169 - kf; Operational Details; , where k is determined by the precision; Table 6-2. Example Values for Interpolation Rate
www.ti.com 6.3 Operational Details R + kf k u ( 3 Ǹ ( p 2 (2 b * 1) 2 ) ń 3) Operational Details Synchronization is an important aspect of decoding and presenting data in real-time digital data deliverysystems. This is addressed in the MPEG transport packets by transmitting timing information in the...
Page 170 - Enabling VIC Port; Perform the following steps to enable the VIC port.
www.ti.com 6.4 Enabling VIC Port 6.5 VIC Port Registers Enabling VIC Port Perform the following steps to enable the VIC port. 1. Clear the GO bit in the VIC control register (VICCTL) to 0.2. Set the PRECISION bits in VICCTL to the desired precision.3. Set the VIC clock divider register (VICDIV) bits...
Page 171 - VIC Port Registers; The VIC control register (VICCTL) is shown in
www.ti.com 6.5.1 VIC Control Register (VICCTL) VIC Port Registers The VIC control register (VICCTL) is shown in Figure 6-3 and described in Table 6-4 . Figure 6-3. VIC Control Register (VICCTL) 31 16 Reserved R-0 15 4 3 1 0 Reserved PRECISION GO R-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read onl...
Page 172 - The VIC input register (VICIN) is shown in
www.ti.com 6.5.2 VIC Input Register (VICIN) VIC Port Registers The DSP writes the input bits for VCXO interpolated control in the VIC input register (VICIN). The DSPdecides how often to update VICIN. The DSP can write to VICIN only when the GO bit in the VIC controlregister (VICCTL) is set to 1. The...
Page 173 - The VIC clock divider register (VICDIV) is shown in
www.ti.com 6.5.3 VIC Clock Divider Register (VICDIV) Divider + Round ƪ DCLK ń R ] VIC Port Registers The VIC clock divider register (VICDIV) defines the clock divider for the VIC interpolation frequency. TheVIC interpolation frequency is obtained by dividing the module clock. The divider value writt...
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