Texas Instruments TMS320DM646x - Manual

Texas Instruments TMS320DM646x

Texas Instruments TMS320DM646x – Manual, read for free online in PDF format. We hope this helps you resolve any issues you may have. If you have further questions, please contact us through the contact form.

1 Page 1
2 Page 2
3 Page 3
4 Page 4
5 Page 5
6 Page 6
7 Page 7
8 Page 8
9 Page 9
10 Page 10
11 Page 11
12 Page 12
13 Page 13
14 Page 14
15 Page 15
16 Page 16
17 Page 17
18 Page 18
19 Page 19
20 Page 20
21 Page 21
22 Page 22
23 Page 23
24 Page 24
25 Page 25
26 Page 26
27 Page 27
28 Page 28
29 Page 29
30 Page 30
31 Page 31
32 Page 32
33 Page 33
34 Page 34
35 Page 35
36 Page 36
37 Page 37
38 Page 38
39 Page 39
40 Page 40
41 Page 41
42 Page 42
43 Page 43
44 Page 44
45 Page 45
46 Page 46
47 Page 47
48 Page 48
49 Page 49
50 Page 50
51 Page 51
52 Page 52
53 Page 53
54 Page 54
55 Page 55
56 Page 56
57 Page 57
58 Page 58
59 Page 59
60 Page 60
61 Page 61
62 Page 62
63 Page 63
64 Page 64
65 Page 65
66 Page 66
67 Page 67
68 Page 68
69 Page 69
70 Page 70
71 Page 71
72 Page 72
73 Page 73
74 Page 74
75 Page 75
76 Page 76
77 Page 77
78 Page 78
79 Page 79
80 Page 80
81 Page 81
82 Page 82
83 Page 83
84 Page 84
85 Page 85
86 Page 86
87 Page 87
88 Page 88
89 Page 89
90 Page 90
91 Page 91
92 Page 92
93 Page 93
94 Page 94
95 Page 95
96 Page 96
97 Page 97
98 Page 98
99 Page 99
100 Page 100
101 Page 101
102 Page 102
103 Page 103
104 Page 104
105 Page 105
106 Page 106
107 Page 107
108 Page 108
109 Page 109
110 Page 110
111 Page 111
112 Page 112
113 Page 113
114 Page 114
115 Page 115
116 Page 116
117 Page 117
118 Page 118
119 Page 119
120 Page 120
121 Page 121
122 Page 122
123 Page 123
124 Page 124
125 Page 125
126 Page 126
127 Page 127
128 Page 128
129 Page 129
130 Page 130
131 Page 131
132 Page 132
133 Page 133
134 Page 134
135 Page 135
Page: / 135

Table of Contents:

  • Page 3 – Contents; Preface
  • Page 4 – Ethernet Media Access Controller (EMAC) Registers
  • Page 5 – Appendix A Glossary
  • Page 10 – Read This First; About This Manual; SPRUEP8; — TMS320DM646x DMSoC DSP Subsystem Reference Guide.; SPRUEP9; — TMS320DM646x DMSoC ARM Subsystem Reference Guide.; SPRUEQ0; — TMS320DM646x DMSoC Peripherals Overview Reference Guide.
  • Page 11 – Related Documentation From Texas Instruments; — TMS320C64x+ DSP Megamodule Reference Guide.
  • Page 12 – Introduction; Purpose of the Peripheral
  • Page 13 – Functional Block Diagram; Figure 1. EMAC and MDIO Block Diagram; Figure 1
  • Page 14 – Industry Standard(s) Compliance Statement; Clock Control; MII Clocking; Architecture; for details of interrupt multiplex logic of the EMAC control
  • Page 15 – Media Independent Interface (MII) Connections; 2 bits in size. Data can be written to and; Figure 2. Ethernet Configuration—MII Connections
  • Page 16 – Table 1. EMAC and MDIO Signals for MII Interface
  • Page 17 – Gigabit Media Independent Interface (GMII) Connections; Figure 3; Figure 3. Ethernet Configuration—GMII Connections
  • Page 18 – Table 2. EMAC and MDIO Signals for GMII Interface (continued)
  • Page 19 – Ethernet Protocol Overview; Ethernet Frame Format; Figure 4; Figure 4. Ethernet Frame Format
  • Page 20 – Ethernet’s Multiple Access Protocol; Programming Interface; Packet Buffer Descriptors; the frame in a buffer.; Figure 5. Basic Descriptor Format
  • Page 21 – Table 4. Basic Descriptor Description; Figure 6. Typical Descriptor Linked List
  • Page 22 – Transmit and Receive Descriptor Queues
  • Page 23 – Transmit and Receive EMAC Interrupts
  • Page 24 – Transmit Buffer Descriptor Format; Figure 7; Figure 7. Transmit Buffer Descriptor Format; Example 1. Transmit Buffer Descriptor in C Structure Format
  • Page 25 – The range of legal values for this field is 0 to (Buffer Length – 1).
  • Page 27 – Receive Buffer Descriptor Format; Next Descriptor Pointer; Figure 8; Figure 8. Receive Buffer Descriptor Format
  • Page 28 – Buffer Offset; Example 2. Receive Buffer Descriptor in C Structure Format
  • Page 29 – This 16-bit field is used for two purposes:
  • Page 31 – EMAC Control Module; Internal Memory; The basic functions of the EMAC control module (; Figure 9. EMAC Control Module Block Diagram
  • Page 32 – Interrupt Control; Transmit Pulse Interrupt; Table 5; Table 5. EMAC Control Module Interrupts; . The eight individual
  • Page 33 – Interrupt Pacing; Write the appropriate CPGMAC receive channel
  • Page 34 – MDIO Module; MDIO Module Components; MDIO Clock Generator; ) interfaces to the PHY components through two MDIO pins (MDCLK and; Figure 10. MDIO Module Block Diagram
  • Page 35 – MDIO Module Operational Overview
  • Page 37 – Example of MDIO Register Access Code; Example 3
  • Page 38 – EMAC Module; EMAC Module Components; Receive DMA Engine; Statistics logic; Figure 11. EMAC Module Block Diagram
  • Page 40 – EMAC Module Operational Overview
  • Page 41 – Data Reception; Receive Control; Receive buffer flow control
  • Page 42 – Collision-Based Receive Buffer Flow Control; The EMAC transmits pause frames as described below:
  • Page 43 – Data Transmission; Transmit Control
  • Page 44 – Transmit Flow Control
  • Page 45 – Packet Receive Operation; Receive DMA Host Configuration
  • Page 48 – Promiscuous Receive Mode; Table 6; Table 6. Receive Frame Treatment Summary
  • Page 49 – Receive Overrun; The types of receive overrun are:; Table 7. Middle of Frame Overrun Treatment
  • Page 50 – Packet Transmit Operation; Transmit DMA Host Configuration; Receive and Transmit Latency
  • Page 51 – Software Reset Considerations
  • Page 52 – Reference Guide
  • Page 53 – Example 4. EMAC Control Module Initialization Code
  • Page 54 – MDIO Module Initialization; Example 5
  • Page 55 – EMAC Module Initialization
  • Page 56 – Interrupt Support; EMAC Module Interrupt Events and Requests; Receive Threshold Interrupts; Figure 12. EMAC Control Module Interrupt Logic Diagram
  • Page 57 – completion pointer register (TX
  • Page 59 – MDIO Module Interrupt Events and Requests; Link Change Interrupt; Proper Interrupt Processing
  • Page 60 – TMS320DM646x DMSoC ARM Subsystem Reference Guide; Table 8. Emulation Control
  • Page 61 – EMAC Control Module Registers; Table 9; Table 9. EMAC Control Module Registers; The identification and version register (CMIDVER) is shown in; Field Descriptions
  • Page 62 – The software reset register (CMSOFTRESET) is shown in
  • Page 63 – EMAC Control Module Interrupt Control Register (CMINTCTRL); The interrupt control register (CMINTCTRL) is shown in
  • Page 64 – and
  • Page 65 – The transmit interrupt enable register (CMTXINTEN) is shown in
  • Page 66 – and described in
  • Page 68 – The transmit interrupt status register (CMTXINTSTAT) is shown in
  • Page 71 – MDIO Registers; for the memory address of these registers.
  • Page 72 – The MDIO control register (CONTROL) is shown in
  • Page 73 – The PHY acknowledge status register (ALIVE) is shown in
  • Page 80 – The MDIO user access register 0 (USERACCESS0) is shown in
  • Page 81 – The MDIO user PHY select register 0 (USERPHYSEL0) is shown in
  • Page 82 – The MDIO user access register 1 (USERACCESS1) is shown in
  • Page 83 – The MDIO user PHY select register 1 (USERPHYSEL1) is shown in
  • Page 84 – memory address of these registers.
  • Page 87 – Transmit Identification and Version Register (TXIDVER); Figure 41. Transmit Identification and Version Register (TXIDVER); The transmit control register (TXCONTROL) is shown in
  • Page 88 – The transmit teardown register (TXTEARDOWN) is shown in
  • Page 89 – Receive Identification and Version Register (RXIDVER); Figure 44. Receive Identification and Version Register (RXIDVER); The receive control register (RXCONTROL) is shown in; Table 44. Receive Control Register (RXCONTROL) Field Descriptions
  • Page 90 – The receive teardown register (RXTEARDOWN) is shown in
  • Page 93 – Transmit Interrupt Mask Set Register (TXINTMASKSET); Figure 49. Transmit Interrupt Mask Set Register (TXINTMASKSET)
  • Page 95 – The MAC input vector register (MACINVECTOR) is shown in; Figure 52. MAC End Of Interrupt Vector Register (MACEOIVECTOR)
  • Page 98 – The receive interrupt mask set register (RXINTMASKSET) is shown in; Figure 55. Receive Interrupt Mask Set Register (RXINTMASKSET)
  • Page 99 – Figure 56. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)
  • Page 101 – The MAC interrupt mask set register (MACINTMASKSET) is shown in; Figure 60. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)
  • Page 105 – The receive unicast enable set register (RXUNICASTSET) is shown in; Figure 62. Receive Unicast Enable Set Register (RXUNICASTSET)
  • Page 106 – The receive unicast clear register (RXUNICASTCLEAR) is shown in
  • Page 107 – The receive maximum length register (RXMAXLEN) is shown in
  • Page 108 – The receive channel 0-7 flow control threshold register (RX
  • Page 109 – The receive channel 0-7 free buffer count register (RX
  • Page 110 – The MAC control register (MACCONTROL) is shown in; Table 68. MAC Control Register (MACCONTROL) Field Descriptions
  • Page 112 – The MAC status register (MACSTATUS) is shown in
  • Page 114 – The emulation control register (EMCONTROL) is shown in; Table 71. FIFO Control Register (FIFOCONTROL) Field Descriptions
  • Page 115 – The MAC configuration register (MACCONFIG) is shown in
  • Page 116 – Figure 75. MAC Source Address Low Bytes Register (MACSRCADDRLO); and described; Figure 76. MAC Source Address High Bytes Register (MACSRCADDRHI)
  • Page 117 – The MAC hash address register 1 (MACHASH1) is shown in; Table 76. MAC Hash Address Register 1 (MACHASH1) Field Descriptions; The MAC hash address register 2 (MACHASH2) is shown in; Table 77. MAC Hash Address Register 2 (MACHASH2) Field Descriptions
  • Page 118 – The back off test register (BOFFTEST) is shown in; Table 78. Back Off Test Register (BOFFTEST) Field Descriptions; Figure 80. Transmit Pacing Algorithm Test Register (TPACETEST)
  • Page 119 – The receive pause timer register (RXPAUSE) is shown in
  • Page 121 – The MAC address high bytes register (MACADDRHI) is shown in
  • Page 123 – The transmit channel 0-7 completion pointer register (TX
  • Page 124 – Network Statistics Registers; Good Receive Frames Register (RXGOODFRAMES); Figure 90. Statistics Register
  • Page 130 – Was any length
  • Page 131 – Also counted in this statistic is:
  • Page 133 – Appendix A; A small memory structure that describes a larger block of
  • Page 134 – Link—; Port—; EMAC receives frames that do not match its address.
  • Page 135 – IMPORTANT NOTICE
Loading the manual

TMS320DM646x DMSoC

Ethernet Media Access Controller (EMAC)/

Management Data Input/Output (MDIO)

Module

User's Guide

Literature Number: SPRUEQ6

December 2007

"Loading the manual" means you need to wait until the file loads and becomes available for online reading. Some manuals are very large, and the time they take to appear depends on your internet speed.

Summary

Page 3 - Contents; Preface

Contents Preface .............................................................................................................................. 10 1 Introduction .............................................................................................................. 12 1.1 Purpose of the Perip...

Page 4 - Ethernet Media Access Controller (EMAC) Registers

4.3 PHY Acknowledge Status Register (ALIVE) ................................................................ 73 4.4 PHY Link Status Register (LINK) ............................................................................. 73 4.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) ...

Page 5 - Appendix A Glossary

5.36 MAC Source Address High Bytes Register (MACSRCADDRHI) ....................................... 116 5.37 MAC Hash Address Register 1 (MACHASH1) ............................................................ 117 5.38 MAC Hash Address Register 2 (MACHASH2) ...............................................

Other Texas Instruments Models

All Texas Instruments Other