Texas Instruments TMS320DM646x - Manuals

Preface SPRUEQ6 – December 2007 Read This First About This Manual This document provides a functional description of the Ethernet Media Access Controller (EMAC) andphysical layer (PHY) device Management Data Input/Output (MDIO) module integrated in theTMS320DM646x Digital Media System-on-Chip. Inclu...

www.ti.com Related Documentation From Texas Instruments SPRU871 — TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access(IDMA) controller, the interrupt controller, the power-down ...

1 Introduction 1.1 Purpose of the Peripheral 1.2 Features User's Guide SPRUEQ6 – December 2007 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) This document provides a functional description of the Ethernet Media Access Controller (EMAC) andphysical layer (PHY) device Man...

www.ti.com 1.3 Functional Block Diagram Configuration bus DMA memory transfer controller Peripheral bus EMAC control module EMAC module MDIO module G/MII bus MDIO bus EMAC/MDIO interrupts ARM interrupt controller 4 Introduction • No-chain mode truncates frame to first buffer for network analysis app...

www.ti.com 1.4 Industry Standard(s) Compliance Statement 2 Architecture 2.1 Clock Control 2.1.1 MII Clocking 2.1.2 GMII Clocking Architecture The EMAC and MDIO interrupts are combined within the control module, so only the control moduleinterrupt needs to be monitored by the application software or ...

www.ti.com 2.2 Memory Map 2.3 Signal Descriptions 2.3.1 Media Independent Interface (MII) Connections MTCLK MTXD(7−0) MTXEN MCOL MCRS MRCLK MRXD(7−0) MRXDV MRXER MDCLK MDIO Physical layer device (PHY) System core Transformer 2.5 MHz, 25 MHz or 125 MHz RJ−45 EMAC MDIO Architecture The EMAC peripheral...

www.ti.com Architecture Table 1. EMAC and MDIO Signals for MII Interface Signal Type Description MTCLK I Transmit clock (MTCLK). The transmit clock is a continuous clock that provides the timing referencefor transmit operations. The MTXD and MTXEN signals are tied to this clock. The clock is generat...

www.ti.com 2.3.2 Gigabit Media Independent Interface (GMII) Connections MTCLK MTXD[7−0] MTXEN MCOL MCRS MRCLK MRXD[7−0] MRXDV MRXER MDCLK MDIO Physical layer device (PHY) System core Transformer 2.5 MHz, 25 MHz, RJ−45 EMAC MDIO GMTCLK or 125 MHz RFTCLK Architecture Figure 3 shows a device with integ...

www.ti.com Architecture Table 2. EMAC and MDIO Signals for GMII Interface (continued) Signal Type Description MCRS I Carrier sense (MCRS). The MCRS pin is asserted by the PHY when the network is not idle in eithertransmit or receive. The pin is de-asserted when both transmit and receive are idle. Th...

www.ti.com 2.4 Ethernet Protocol Overview 2.4.1 Ethernet Frame Format Preamble SFD Destination Source Len Data 7 1 6 6 2 46−1500 4 FCS Number of bytes Legend: SFD=Start Frame Delimeter; FCS=Frame Check Sequence (CRC) Architecture Ethernet provides an unreliable, connection-less service to a networki...

www.ti.com 2.4.2 Ethernet’s Multiple Access Protocol 2.5 Programming Interface 2.5.1 Packet Buffer Descriptors Architecture Nodes in an Ethernet Local Area Network are interconnected by a broadcast channel, as a result, whenan EMAC port transmits a frame, all the adapters on the local network receiv...

www.ti.com SOP | EOP 60 0 60 pBuffer pNext Packet A 60 bytes 0 SOP Fragment 1 Packet B 512 1514 pBuffer pNext 512 bytes EOP 0 0 −−− Packet B Fragment 3 500 bytes 502 pBuffer −−− 500 pNext −−− pBuffer pNext Packet B Fragment 2 502 bytes SOP | EOP 0 1514 bytes Packet C 1514 pBuffer pNext (NULL) 1514 A...

www.ti.com 2.5.2 Transmit and Receive Descriptor Queues Architecture The EMAC module processes descriptors in linked list chains as discussed in Section 2.5.1 . The lists controlled by the EMAC are maintained by the application software through the use of the head descriptorpointer registers (HDP). ...

www.ti.com 2.5.3 Transmit and Receive EMAC Interrupts Architecture The EMAC processes descriptors in linked list chains as discussed in Section 2.5.1 , using the linked list queue mechanism discussed in Section 2.5.2 . The EMAC synchronizes descriptor list processing through the use of interrupts to...

www.ti.com 2.5.4 Transmit Buffer Descriptor Format Architecture A transmit (TX) buffer descriptor ( Figure 7 ) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 1 shows the transmit buffer descriptor described by a C st...

www.ti.com 2.5.4.1 Next Descriptor Pointer 2.5.4.2 Buffer Pointer 2.5.4.3 Buffer Offset 2.5.4.4 Buffer Length 2.5.4.5 Packet Length 2.5.4.6 Start of Packet (SOP) Flag Architecture The next descriptor pointer points to the 32-bit word aligned memory address of the next buffer descriptorin the transmi...

www.ti.com 2.5.5 Receive Buffer Descriptor Format 2.5.5.1 Next Descriptor Pointer 2.5.5.2 Buffer Pointer Architecture A receive (RX) buffer descriptor ( Figure 8 ) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 2 sho...

www.ti.com 2.5.5.3 Buffer Offset Architecture Example 2. Receive Buffer Descriptor in C Structure Format /* // EMAC Descriptor // // The following is the format of a single buffer descriptor // on the EMAC. */ typedef struct _EMAC_Desc { struct _EMAC_Desc *pNext; /* Pointer to next descriptor in cha...

www.ti.com 2.5.5.4 Buffer Length 2.5.5.5 Packet Length 2.5.5.6 Start of Packet (SOP) Flag 2.5.5.7 End of Packet (EOP) Flag 2.5.5.8 Ownership (OWNER) Flag 2.5.5.9 End of Queue (EOQ) Flag Architecture This 16-bit field is used for two purposes: • Before the descriptor is first placed on the receive qu...

www.ti.com 2.5.5.21 No Match (NOMATCH) Flag 2.6 EMAC Control Module Arbiter and bus switches CPU DMA Controllers 8K byte descriptor memory Configuration registers Interrupt control and pacing logic EMAC interrupts MDIO interrupts Configuration bus Transmit and Receive 4 interruptsto ARM 2.6.1 Intern...

www.ti.com 2.6.3 Interrupt Control 2.6.3.1 Transmit Pulse Interrupt 2.6.3.2 Receive Pulse Interrupt Architecture The EMAC control module combines multiple interrupt conditions generated by the EMAC and MDIOmodules into four separate interrupt signals ( Table 5 ) that are mapped to a CPU interrupt vi...

www.ti.com 2.6.3.3 Receive Threshold Pulse Interrupt 2.6.3.4 Miscellaneous Pulse Interrupt 2.6.4 Interrupt Pacing Architecture The EMAC control module receives the eight individual receive threshold interrupts originating from theEMAC module, one for each of the eight channels, and combines them int...

www.ti.com 2.7 MDIO Module 2.7.1 MDIO Module Components EMAC control module Control registers and logic PHY monitoring Peripheral clock MDIO clock generator USERINT MDIO interface polling PHY MDCLK MDIO LINKINT Configuration bus 2.7.1.1 MDIO Clock Generator Architecture If the rate of transmit pulse...

www.ti.com 2.7.1.2 Global PHY Detection and Link State Monitoring 2.7.1.3 Active PHY Monitoring 2.7.1.4 PHY Register User Access 2.7.2 MDIO Module Operational Overview Architecture The MDIO module continuously polls all 32 MDIO addresses in order to enumerate the PHY devices in thesystem. The module...

www.ti.com 2.7.2.4 Example of MDIO Register Access Code Architecture The MDIO module uses the MDIO user access register (USERACCESS n ) to access the PHY control registers. Software functions that implement the access process may simply be the following four macros: Start the process of reading a PH...

www.ti.com 2.8 EMAC Module 2.8.1 EMAC Module Components Clock and reset logic Receive DMA engine Interrupt controller Transmit DMA engine Control registers Configuration bus EMAC control module Configuration bus RAM State FIFO Receive FIFO Transmit MAC transmitter Statistics receiver MAC SYNC 2.8.1....

www.ti.com 2.8.2 EMAC Module Operational Overview Architecture After reset, initialization, and configuration, the application software running on the host may initiatetransmit operations. Transmit operations are initiated by host writes to the appropriate transmit channelhead descriptor pointer con...

www.ti.com 2.9 Media Independent Interface (MII) 2.9.1 Data Reception 2.9.1.1 Receive Control 2.9.1.2 Receive Inter-Frame Interval 2.9.1.3 Receive Flow Control Architecture The following sections discuss the operation of the Media Independent Interface (MII) in 10 Mbps and100 Mbps mode. An IEEE 802....

www.ti.com Architecture 2.9.1.3.1 Collision-Based Receive Buffer Flow Control Collision-based receive buffer flow control provides a means of preventing frame reception when theEMAC is operating in half-duplex mode (the FULLDUPLEX bit is cleared in MACCONTROL). Whenreceive flow control is enabled an...

www.ti.com 2.9.2 Data Transmission 2.9.2.1 Transmit Control 2.9.2.2 CRC Insertion 2.9.2.3 Adaptive Performance Optimization (APO) 2.9.2.4 Interpacket-Gap (IPG) Enforcement 2.9.2.5 Back Off Architecture The EMAC passes data to the PHY from the transmit FIFO (when enabled). Data is synchronized to the...

www.ti.com 2.9.2.6 Transmit Flow Control 2.9.2.7 Speed, Duplex, and Pause Frame Support Architecture Incoming pause frames are acted upon, when enabled, to prevent the EMAC from transmitting any furtherframes. Incoming pause frames are only acted upon when the FULLDUPLEX and TXFLOWEN bits in theMAC ...

www.ti.com 2.10 Packet Receive Operation 2.10.1 Receive DMA Host Configuration 2.10.2 Receive Channel Enabling Architecture To configure the receive DMA for operation the host must: • Initialize the receive addresses. • Initialize the receive channel n DMA head descriptor pointer registers (RX n HDP...

www.ti.com 2.10.8 Promiscuous Receive Mode Architecture When the promiscuous receive mode is enabled by setting the RXCAFEN bit in the receivemulticast/broadcast/promiscuous channel enable register (RXMBPENABLE), nonaddress matching framesthat would normally be filtered are transferred to the promis...

www.ti.com 2.10.9 Receive Overrun Architecture Table 6. Receive Frame Treatment Summary (continued) Address Match RXCAFEN RXCEFEN RXCMFEN RXCSFEN Receive Frame Treatment 1 X 1 1 0 Proper/oversize/jabber/code/align/CRC data andcontrol frames transferred to address matchchannel. No undersized/fragment...

www.ti.com 2.11 Packet Transmit Operation 2.11.1 Transmit DMA Host Configuration 2.11.2 Transmit Channel Teardown 2.12 Receive and Transmit Latency Architecture The transmit DMA is an eight channel interface. Priority between the eight queues may be either fixed orround-robin as selected by the TXPT...

www.ti.com 2.13 Transfer Node Priority 2.14 Reset Considerations 2.14.1 Software Reset Considerations Architecture Receive overrun is prevented if the receive memory cell latency is less than the time required to transmit a64-byte cell on the wire (0.512 ms in 1 Gbps mode, 5.12 ms in 100 Mbps mode, ...

www.ti.com 2.14.2 Hardware Reset Considerations 2.15 Initialization 2.15.1 Enabling the EMAC/MDIO Peripheral 2.15.2 EMAC Control Module Initialization Architecture When a hardware reset occurs, the EMAC peripheral has its register values reset and all the componentsreturn to their default state. Aft...

www.ti.com Architecture Example 4. EMAC Control Module Initialization Code Uint32 tmpval ; /* Disable all the EMAC/MDIO interrupts in the control module */EmacControlRegs->CONTROL.C_RX_EN = 0; EmacControlRegs->CONTROL.C_TX_EN = 0; EmacControlRegs->CONTROL.C_RX_THRESH_EN = 0;EmacControlRegs-...

www.ti.com 2.15.3 MDIO Module Initialization Architecture The MDIO module is used to initially configure and monitor one or more external PHY devices. Otherthan initializing the software state machine (details on this state machine can be found in theIEEE 802.3 standard), all that needs to be done f...

www.ti.com 2.15.4 EMAC Module Initialization Architecture The EMAC module is used to send and receive data packets over the network. This is done bymaintaining up to eight transmit and receive descriptor queues. The EMAC module configuration mustalso be kept up-to-date based on PHY negotiation resul...

www.ti.com 2.16 Interrupt Support 2.16.1 EMAC Module Interrupt Events and Requests EMAC core MDIO core RXTHRESHOLDPEND(0..7) Receive threshold interrupt RXPEND(0..7) Receive interrupt TXPEND(0..7) Transmit interrupt STATPEND HOSTPEND MDIO_USER Miscellaneous interrupt MDIO_LINKINT Interrupt control a...

www.ti.com 2.16.1.2 Transmit Packet Completion Interrupts 2.16.1.3 Receive Packet Completion Interrupts Architecture The transmit DMA engine has eight channels, with each channel having a corresponding interrupt(TXPEND n ). The transmit interrupts are level interrupts that remain asserted until clea...

www.ti.com 2.16.2 MDIO Module Interrupt Events and Requests 2.16.2.1 Link Change Interrupt 2.16.2.2 User Access Completion Interrupt 2.16.3 Proper Interrupt Processing 2.16.4 Interrupt Multiplexing Architecture The MDIO module generates two interrupt events: • LINKINT: Serial interface link change i...

www.ti.com 2.17 Power Management 2.18 Emulation Considerations Architecture Each of the three main components of the EMAC peripheral can independently be placed inreduced-power modes to conserve power during periods of low activity. The power management of theEMAC peripheral is controlled by the pro...

www.ti.com 3 EMAC Control Module Registers 3.1 EMAC Control Module Identification and Version Register (CMIDVER) EMAC Control Module Registers Table 9 lists the memory-mapped registers for the EMAC control module. See the device-specific data manual for the memory address of these registers. Table 9...

www.ti.com 3.2 EMAC Control Module Software Reset Register (CMSOFTRESET) 3.3 EMAC Control Module Emulation Control Register (CMEMCONTROL) EMAC Control Module Registers The software reset register (CMSOFTRESET) is shown in Figure 14 and described in Table 11 . Figure 14. EMAC Control Module Software ...

www.ti.com 3.4 EMAC Control Module Interrupt Control Register (CMINTCTRL) EMAC Control Module Registers The interrupt control register (CMINTCTRL) is shown in Figure 16 and described in Table 13 . Figure 16. EMAC Control Module Interrupt Control Register (CMINTCTRL) 31 30 18 17 16 Reserved Reserved ...

www.ti.com 3.5 EMAC Control Module Receive Threshold Interrupt Enable Register 3.6 EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN) EMAC Control Module Registers (CMRXTHRESHINTEN) The receive threshold interrupt enable register (CMRXTHRESHINTEN) is shown in Figure 17 and described i...

www.ti.com 3.7 EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN) EMAC Control Module Registers The transmit interrupt enable register (CMTXINTEN) is shown in Figure 19 and described in Table 16 . Figure 19. EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN) 31 16 Res...

www.ti.com 3.8 EMAC Control Module Miscellaneous Interrupt Enable Register (CMMISCINTEN) EMAC Control Module Registers The miscellaneous interrupt enable register (CMMISCINTEN) is shown in Figure 20 and described in Table 17 . Figure 20. EMAC Control Module Miscellaneous Interrupt Enable Register (C...

www.ti.com 3.11 EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT) EMAC Control Module Registers The transmit interrupt status register (CMTXINTSTAT) is shown in Figure 23 and described in Table 20 . Figure 23. EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT) 31...

www.ti.com 4 MDIO Registers 4.1 MDIO Version Register (VERSION) MDIO Registers Table 24 lists the memory-mapped registers for the MDIO module. See the device-specific data manual for the memory address of these registers. Table 24. Management Data Input/Output (MDIO) Registers Offset Acronym Registe...

www.ti.com 4.2 MDIO Control Register (CONTROL) MDIO Registers The MDIO control register (CONTROL) is shown in Figure 28 and described in Table 26 . Figure 28. MDIO Control Register (CONTROL) 31 30 29 28 24 23 21 20 19 18 17 16 IDLE ENABLE Rsvd HIGHEST_USER_CHANNEL Reserved PREAMBLE FAULT FAULTENB Re...

www.ti.com 4.3 PHY Acknowledge Status Register (ALIVE) 4.4 PHY Link Status Register (LINK) MDIO Registers The PHY acknowledge status register (ALIVE) is shown in Figure 29 and described in Table 27 . Figure 29. PHY Acknowledge Status Register (ALIVE) 31 16 ALIVE R/W1C-0 15 0 ALIVE R/W1C-0 LEGEND: R/...

www.ti.com 4.11 MDIO User Access Register 0 (USERACCESS0) MDIO Registers The MDIO user access register 0 (USERACCESS0) is shown in Figure 37 and described in Table 35 . Figure 37. MDIO User Access Register 0 (USERACCESS0) 31 30 29 28 26 25 21 20 16 GO WRITE ACK Reserved REGADR PHYADR R/W1S-0 R/W-0 R...

www.ti.com 4.12 MDIO User PHY Select Register 0 (USERPHYSEL0) MDIO Registers The MDIO user PHY select register 0 (USERPHYSEL0) is shown in Figure 38 and described in Table 36 . Figure 38. MDIO User PHY Select Register 0 (USERPHYSEL0) 31 16 Reserved R-0 15 8 7 6 5 4 0 Reserved LINKSEL LINKINTENB Rsvd...

www.ti.com 4.13 MDIO User Access Register 1 (USERACCESS1) MDIO Registers The MDIO user access register 1 (USERACCESS1) is shown in Figure 39 and described in Table 37 . Figure 39. MDIO User Access Register 1 (USERACCESS1) 31 30 29 28 26 25 21 20 16 GO WRITE ACK Reserved REGADR PHYADR R/W1S-0 R/W-0 R...

www.ti.com 4.14 MDIO User PHY Select Register 1 (USERPHYSEL1) MDIO Registers The MDIO user PHY select register 1 (USERPHYSEL1) is shown in Figure 40 and described in Table 38 . Figure 40. MDIO User PHY Select Register 1 (USERPHYSEL1) 31 16 Reserved R-0 15 8 7 6 5 4 0 Reserved LINKSEL LINKINTENB Rsvd...

www.ti.com 5 Ethernet Media Access Controller (EMAC) Registers Ethernet Media Access Controller (EMAC) Registers Table 39 lists the memory-mapped registers for the EMAC. See the device-specific data manual for the memory address of these registers. Table 39. Ethernet Media Access Controller (EMAC) R...

www.ti.com 5.1 Transmit Identification and Version Register (TXIDVER) 5.2 Transmit Control Register (TXCONTROL) Ethernet Media Access Controller (EMAC) Registers The transmit identification and version register (TXIDVER) is shown in Figure 41 and described in Table 40 . Figure 41. Transmit Identific...

www.ti.com 5.3 Transmit Teardown Register (TXTEARDOWN) Ethernet Media Access Controller (EMAC) Registers The transmit teardown register (TXTEARDOWN) is shown in Figure 43 and described in Table 42 . Figure 43. Transmit Teardown Register (TXTEARDOWN) 31 16 Reserved R-0 15 3 2 0 Reserved TXTDNCH R-0 R...

www.ti.com 5.4 Receive Identification and Version Register (RXIDVER) 5.5 Receive Control Register (RXCONTROL) Ethernet Media Access Controller (EMAC) Registers The receive identification and version register (RXIDVER) is shown in Figure 44 and described in Table 43 . Figure 44. Receive Identificatio...

www.ti.com 5.6 Receive Teardown Register (RXTEARDOWN) Ethernet Media Access Controller (EMAC) Registers The receive teardown register (RXTEARDOWN) is shown in Figure 46 and described in Table 45 . Figure 46. Receive Teardown Register (RXTEARDOWN) 31 16 Reserved R-0 15 3 2 0 Reserved RXTDNCH R-0 R/W-...

www.ti.com 5.9 Transmit Interrupt Mask Set Register (TXINTMASKSET) Ethernet Media Access Controller (EMAC) Registers The transmit interrupt mask set register (TXINTMASKSET) is shown in Figure 49 and described in Table 48 . Figure 49. Transmit Interrupt Mask Set Register (TXINTMASKSET) 31 16 Reserved...

www.ti.com 5.11 MAC Input Vector Register (MACINVECTOR) 5.12 MAC End Of Interrupt Vector Register (MACEOIVECTOR) Ethernet Media Access Controller (EMAC) Registers The MAC input vector register (MACINVECTOR) is shown in Figure 51 and described in Table 50 . Figure 51. MAC Input Vector Register (MACIN...

www.ti.com 5.15 Receive Interrupt Mask Set Register (RXINTMASKSET) Ethernet Media Access Controller (EMAC) Registers The receive interrupt mask set register (RXINTMASKSET) is shown in Figure 55 and described in Table 54 . Figure 55. Receive Interrupt Mask Set Register (RXINTMASKSET) 31 16 Reserved R...

www.ti.com 5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Ethernet Media Access Controller (EMAC) Registers The receive interrupt mask clear register (RXINTMASKCLEAR) is shown in Figure 56 and described in Table 55 . Figure 56. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) 31 1...

www.ti.com 5.19 MAC Interrupt Mask Set Register (MACINTMASKSET) 5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Ethernet Media Access Controller (EMAC) Registers The MAC interrupt mask set register (MACINTMASKSET) is shown in Figure 59 and described in Table 58 . Figure 59. MAC Interrupt Ma...

www.ti.com 5.22 Receive Unicast Enable Set Register (RXUNICASTSET) Ethernet Media Access Controller (EMAC) Registers The receive unicast enable set register (RXUNICASTSET) is shown in Figure 62 and described in Table 61 . Figure 62. Receive Unicast Enable Set Register (RXUNICASTSET) 31 16 Reserved R...

www.ti.com 5.23 Receive Unicast Clear Register (RXUNICASTCLEAR) Ethernet Media Access Controller (EMAC) Registers The receive unicast clear register (RXUNICASTCLEAR) is shown in Figure 63 and described in Table 62 . Figure 63. Receive Unicast Clear Register (RXUNICASTCLEAR) 31 16 Reserved R-0 15 8 R...

www.ti.com 5.24 Receive Maximum Length Register (RXMAXLEN) 5.25 Receive Buffer Offset Register (RXBUFFEROFFSET) Ethernet Media Access Controller (EMAC) Registers The receive maximum length register (RXMAXLEN) is shown in Figure 64 and described in Table 63 . Figure 64. Receive Maximum Length Registe...

www.ti.com 5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) 5.27 Receive Channel 0-7 Flow Control Threshold Register (RXnFLOWTHRESH) Ethernet Media Access Controller (EMAC) Registers The receive filter low priority frame threshold register (RXFILTERLOWTHRESH) is shown in...

www.ti.com 5.28 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER) Ethernet Media Access Controller (EMAC) Registers The receive channel 0-7 free buffer count register (RX n FREEBUFFER) is shown in Figure 68 and described in Table 67 . Figure 68. Receive Channel n Free Buffer Count Regis...

www.ti.com 5.29 MAC Control Register (MACCONTROL) Ethernet Media Access Controller (EMAC) Registers The MAC control register (MACCONTROL) is shown in Figure 69 and described in Table 68 . Figure 69. MAC Control Register (MACCONTROL) 31 18 17 16 Reserved GIGFORCE Reserved R-0 R/W-0 R-0 15 14 13 12 11...

www.ti.com 5.30 MAC Status Register (MACSTATUS) Ethernet Media Access Controller (EMAC) Registers The MAC status register (MACSTATUS) is shown in Figure 70 and described in Table 69 . Figure 70. MAC Status Register (MACSTATUS) 31 30 24 23 20 19 18 16 IDLE Reserved TXERRCODE Rsvd TXERRCH R-0 R-0 R-0 ...

www.ti.com 5.31 Emulation Control Register (EMCONTROL) 5.32 FIFO Control Register (FIFOCONTROL) Ethernet Media Access Controller (EMAC) Registers The emulation control register (EMCONTROL) is shown in Figure 71 and described in Table 70 . Figure 71. Emulation Control Register (EMCONTROL) 31 16 Reser...

www.ti.com 5.33 MAC Configuration Register (MACCONFIG) 5.34 Soft Reset Register (SOFTRESET) Ethernet Media Access Controller (EMAC) Registers The MAC configuration register (MACCONFIG) is shown in Figure 73 and described in Table 72 . Figure 73. MAC Configuration Register (MACCONFIG) 31 24 23 16 TXC...

www.ti.com 5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) 5.36 MAC Source Address High Bytes Register (MACSRCADDRHI) Ethernet Media Access Controller (EMAC) Registers The MAC source address low bytes register (MACSRCADDRLO) is shown in Figure 75 and described in Table 74 . Figure 75. MAC ...

www.ti.com 5.37 MAC Hash Address Register 1 (MACHASH1) 5.38 MAC Hash Address Register 2 (MACHASH2) Ethernet Media Access Controller (EMAC) Registers The MAC hash registers allow group addressed frames to be accepted on the basis of a hash functionof the address. The hash function creates a 6-bit dat...

www.ti.com 5.39 Back Off Test Register (BOFFTEST) 5.40 Transmit Pacing Algorithm Test Register (TPACETEST) Ethernet Media Access Controller (EMAC) Registers The back off test register (BOFFTEST) is shown in Figure 79 and described in Table 78 . Figure 79. Back Off Random Number Generator Test Regist...

www.ti.com 5.41 Receive Pause Timer Register (RXPAUSE) 5.42 Transmit Pause Timer Register (TXPAUSE) Ethernet Media Access Controller (EMAC) Registers The receive pause timer register (RXPAUSE) is shown in Figure 81 and described in Table 80 . Figure 81. Receive Pause Timer Register (RXPAUSE) 31 16 R...

www.ti.com 5.44 MAC Address High Bytes Register (MACADDRHI) 5.45 MAC Index Register (MACINDEX) Ethernet Media Access Controller (EMAC) Registers The MAC address high bytes register (MACADDRHI) is shown in Figure 84 and described in Table 83 . Figure 84. MAC Address High Bytes Register (MACADDRHI) 31...

www.ti.com 5.48 Transmit Channel 0-7 Completion Pointer Register (TXnCP) 5.49 Receive Channel 0-7 Completion Pointer Register (RXnCP) Ethernet Media Access Controller (EMAC) Registers The transmit channel 0-7 completion pointer register (TX n CP) is shown in Figure 88 and described in Table 87 . Fig...

www.ti.com 5.50 Network Statistics Registers 5.50.1 Good Receive Frames Register (RXGOODFRAMES) 5.50.2 Broadcast Receive Frames Register (RXBCASTFRAMES) 5.50.3 Multicast Receive Frames Register (RXMCASTFRAMES) Ethernet Media Access Controller (EMAC) Registers The EMAC has a set of statistics that re...

www.ti.com 5.50.26 Transmit Octet Frames Register (TXOCTETS) 5.50.27 Transmit and Receive 64 Octet Frames Register (FRAME64) 5.50.28 Transmit and Receive 65 to 127 Octet Frames Register (FRAME65T127) 5.50.29 Transmit and Receive 128 to 255 Octet Frames Register (FRAME128T255) 5.50.30 Transmit and Re...

www.ti.com 5.50.31 Transmit and Receive 512 to 1023 Octet Frames Register (FRAME512T1023) 5.50.32 Transmit and Receive 1024 to RXMAXLEN Octet Frames Register (FRAME1024TUP) 5.50.33 Network Octet Frames Register (NETOCTETS) 5.50.34 Receive FIFO or DMA Start of Frame Overruns Register (RXSOFOVERRUNS) ...

www.ti.com Appendix A Glossary Appendix A Broadcast MAC Address— A special Ethernet MAC address used to send data to all Ethernet devices on the local network. The broadcast address is FFh-FFh-FFh-FFh-FFh-FFh. The LSB of the firstbyte is odd, qualifying it as a group address; however, its value is r...

www.ti.com Appendix A Link— The transmission path between any two instances of generic cabling. Multicast MAC Address— A class of MAC address that sends a packet to potentially more than one recipient. A group address is specified by setting the LSB of the first MAC address byte to 1.Thus, 01h-02h-0...

IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.Customers should obtain the l...