Texas Instruments TMS320C645x DSP - Manual

Texas Instruments TMS320C645x DSP

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Table of Contents:

  • Page 3 – Contents; Preface
  • Page 4 – EMAC Port Registers
  • Page 5 – Network Statistics Registers; Appendix A Glossary
  • Page 10 – Read This First; About This Manual; TMS320C6455 Technical Reference (literature number; Trademarks
  • Page 11 – Introduction; Purpose of the Peripheral
  • Page 12 – Functional Block Diagram; Figure 1. EMAC and MDIO Block Diagram; Figure 1
  • Page 13 – Industry Standard(s) Compliance Statement
  • Page 14 – Clock Control; MII Clocking; EMAC Functional Architecture
  • Page 15 – RGMII Clocking; Memory Map
  • Page 16 – System Level Connections; Media Independent Interface (MII) Connections; Table 1; Table 1. Interface Selection Pins; Figure 2; Figure 2. Ethernet Configuration with MII Interface
  • Page 17 – Table 2; Table 2. EMAC and MDIO Signals for MII Interface
  • Page 18 – Reduced Media Independent Interface (RMII) Connections; Figure 3; Figure 3. Ethernet Configuration with RMII Interface
  • Page 19 – Table 3; Table 3. EMAC and MDIO Signals for RMII Interface
  • Page 20 – Gigabit Media Independent Interface (GMII) Connections; Figure 4; Figure 4. Ethernet Configuration with GMII Interface
  • Page 21 – Table 4; Table 4. EMAC and MDIO Signals for GMII Interface
  • Page 22 – Reduced Gigabit Media Independent Interface (RGMII) Connections; Figure 5; Figure 5. Ethernet Configuration with RGMII Interface; MRXDV signal (multiplexed in the RXCTL signal) is true
  • Page 23 – Table 5; Table 5. EMAC and MDIO Signals for RGMII Interface
  • Page 24 – Ethernet Protocol Overview; Ethernet Frame Format; Figure 6; Figure 6. Ethernet Frame
  • Page 25 – Multiple Access Protocol
  • Page 26 – Programming Interface; Packet Buffer Descriptors; The basic descriptor format is shown in; Figure 7. Basic Descriptor Format
  • Page 27 – Figure 8; Figure 8. Typical Descriptor Linked List
  • Page 28 – Transmit and Receive Descriptor Queues; The EMAC module processes descriptors in linked list chains (
  • Page 29 – Transmit and Receive EMAC Interrupts; The EMAC processes descriptors in linked list chains (
  • Page 30 – Transmit Buffer Descriptor Format; Figure 9; Figure 9. Transmit Descriptor Format; Example 1. Transmit Descriptor in C Structure Format
  • Page 31 – The range of legal values for this field is 0 to (Buffer Length – 1).
  • Page 33 – Receive Buffer Descriptor Format; ) is a contiguous block of four 32-bit data words aligned on a; Figure 10. Receive Descriptor Format; Example 2. Receive Descriptor in C Structure Format
  • Page 37 – EMAC Control Module; Internal Memory; The EMAC control module (; Figure 11. EMAC Control Module Block Diagram
  • Page 38 – ) interfaces to PHY components through two MDIO pins (MDCLK and
  • Page 39 – Figure 12. MDIO Module Block Diagram
  • Page 40 – MDIO Module Operational Overview; Initializing the MDIO Module; register can determine which of those (if any) already have a link.
  • Page 41 – desired PHY and PHY register.
  • Page 42 – Example 3
  • Page 43 – EMAC Module; EMAC Module Components; Receive DMA Engine; Figure 13. EMAC Module Block Diagram
  • Page 45 – Clock and Reset Logic; EMAC Module Operational Overview
  • Page 46 – Media Independent Interfaces; Data Reception; Receive Control; Receive buffer flow control
  • Page 47 – The EMAC transmits pause frames as described below:
  • Page 48 – Data Transmission; Transmit Control
  • Page 49 – Transmit Flow Control
  • Page 50 – Packet Receive Operation; Receive DMA Host Configuration; Initialize the receive addresses
  • Page 52 – Any current frame in reception completes normally.
  • Page 53 – Promiscuous Receive Mode; Table 8; Table 8. Receive Frame Treatment Summary
  • Page 54 – Receive Overrun; Table 9; Table 9. Middle of Frame Overrun Treatment
  • Page 55 – Packet Transmit Operation; Transmit DMA Host Configuration; Receive and Transmit Latency; Initialize the TXnHDP registers to zero.
  • Page 56 – Software Reset Considerations
  • Page 57 – Setting the interrupt pace count (using EWINTTCNT)
  • Page 58 – MDIO Module Initialization; Example 4. EMAC Control Module Initialization Code; Example 5
  • Page 59 – EMAC Module Initialization; want to allow to be received.
  • Page 60 – Interrupt Support; EMAC Module Interrupt Events and Requests; Transmit Packet Completion Interrupts; STATPEND: Statistics interrupt
  • Page 62 – Host Error Interrupt; MDIO Module Interrupt Events and Requests; Link Change Interrupt
  • Page 63 – Power Management; Table 10. Emulation Control
  • Page 64 – EMAC Control Module Registers; manual for the memory address of these registers.; Table 11. EMAC Control Module Registers; and described in; Figure 14. EMAC Control Module Interrupt Control Register (EWCTL)
  • Page 65 – EMAC Control Module Interrupt Timer Count Register (EWINTTCNT); and
  • Page 66 – MDIO Registers
  • Page 67 – The MDIO version register (VERSION) is shown in
  • Page 68 – The MDIO control register (CONTROL) is shown in
  • Page 69 – The PHY acknowledge status register (ALIVE) is shown in
  • Page 70 – The PHY link status register (LINK) is shown in
  • Page 71 – Descriptions
  • Page 76 – Field Descriptions
  • Page 77 – The MDIO user access register 0 (USERACCESS0) is shown in
  • Page 78 – The MDIO user PHY select register 0 (USERPHYSEL0) is shown in
  • Page 79 – The MDIO user access register 1 (USERACCESS1) is shown in
  • Page 80 – The MDIO user PHY select register 1 (USERPHYSEL1) is shown in
  • Page 85 – Transmit Identification and Version Register (TXIDVER); Figure 30. Transmit Identification and Version Register (TXIDVER)
  • Page 86 – The transmit control register (TXCONTROL) is shown in
  • Page 87 – The transmit teardown register (TXTEARDOWN) is shown in
  • Page 88 – Receive Identification and Version Register (RXIDVER); Figure 33. Receive Identification and Version Register (RXIDVER)
  • Page 89 – The receive control register (RXCONTROL) is shown in; Table 34. Receive Control Register (RXCONTROL) Field Descriptions
  • Page 90 – The receive teardown register (RXTEARDOWN) is shown in
  • Page 91 – and described
  • Page 93 – Figure 38. Transmit Interrupt Mask Set Register (TXINTMASKSET)
  • Page 95 – The MAC input vector register (MACINVECTOR) is shown in
  • Page 98 – The receive interrupt mask set register (RXINTMASKSET) is shown in; Figure 43. Receive Interrupt Mask Set Register (RXINTMASKSET)
  • Page 99 – Figure 44. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)
  • Page 102 – The MAC interrupt mask set register (MACINTMASKSET) is shown in
  • Page 103 – Figure 48. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)
  • Page 106 – The receive unicast enable set register (RXUNICASTSET) is shown in; Figure 50. Receive Unicast Enable Set Register (RXUNICASTSET)
  • Page 107 – The receive unicast clear register (RXUNICASTCLEAR) is shown in
  • Page 108 – The receive maximum length register (RXMAXLEN) is shown in
  • Page 109 – The receive buffer offset register (RXBUFFEROFFSET) is shown in
  • Page 113 – The MAC control register (MACCONTROL) is shown in; Table 57. MAC Control Register (MACCONTROL) Field Descriptions
  • Page 115 – The MAC status register (MACSTATUS) is shown in
  • Page 117 – The emulation control register (EMCONTROL) is shown in
  • Page 118 – The FIFO control register (FIFOCONTROL) is shown in; Table 60. FIFO Control Register (FIFOCONTROL) Field Descriptions
  • Page 119 – The MAC configuration register (MACCONFIG) is shown in
  • Page 120 – The Soft Reset Register (SOFTRESET) is shown in
  • Page 121 – Figure 63. MAC Source Address Low Bytes Register (MACSRCADDRLO)
  • Page 122 – Figure 64. MAC Source Address High Bytes Register (MACSRCADDRHI)
  • Page 123 – The MAC hash address register 1 (MACHASH1) is shown in; Table 65. MAC Hash Address Register 1 (MACHASH1) Field Descriptions
  • Page 124 – The MAC hash address register 2 (MACHASH2) is shown in; Table 66. MAC Hash Address Register 2 (MACHASH2) Field Descriptions
  • Page 125 – The back off test register (BOFFTEST) is shown in; Table 67. Back Off Test Register (BOFFTEST) Field Descriptions
  • Page 126 – Figure 68. Transmit Pacing Algorithm Test Register (TPACETEST)
  • Page 127 – The receive pause timer register (RXPAUSE) is shown in
  • Page 128 – The Transmit Pause Timer Register (TXPAUSE) is shown in
  • Page 129 – The MAC address low bytes register (MACADDRLO) is shown in
  • Page 130 – The MAC address high bytes register (MACADDRHI) is shown in
  • Page 131 – The MAC index register (MACINDEX) is shown in
  • Page 136 – Network Statistics Registers; Good Receive Frames Register (RXGOODFRAMES); Figure 78. Statistics Register; Table 78. Statistics Register Field Descriptions
  • Page 142 – Was any size
  • Page 143 – Also counted in this statistic is:
  • Page 145 – Appendix A; of a single Ethernet frame on the wire.
  • Page 146 – Port — Ethernet device.
  • Page 147 – Appendix B Revision History; Appendix B
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TMS320C645x DSP

Ethernet Media Access Controller (EMAC)/

Management Data Input/Output (MDIO)

User's Guide

Literature Number: SPRU975B

August 2006

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Summary

Page 3 - Contents; Preface

Contents Preface .............................................................................................................................. 10 1 Introduction .............................................................................................................. 11 1.1 Purpose of the Perip...

Page 4 - EMAC Port Registers

4.15 MDIO User PHY Select Register 1 (USERPHYSEL1) .................................................... 80 5 EMAC Port Registers ................................................................................................. 81 5.1 Introduction ........................................................

Page 5 - Network Statistics Registers; Appendix A Glossary

5.48 Transmit Channel 0-7 Completion Pointer Register (TXnCP) ........................................... 134 5.49 Receive Channel 0-7 Completion Pointer Register (RXnCP) ........................................... 135 5.50 Network Statistics Registers ..................................................

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