Page 3 - Contents; Preface
Contents Preface .............................................................................................................................. 10 1 Introduction .............................................................................................................. 11 1.1 Purpose of the Perip...
Page 4 - EMAC Port Registers
4.15 MDIO User PHY Select Register 1 (USERPHYSEL1) .................................................... 80 5 EMAC Port Registers ................................................................................................. 81 5.1 Introduction ........................................................
Page 5 - Network Statistics Registers; Appendix A Glossary
5.48 Transmit Channel 0-7 Completion Pointer Register (TXnCP) ........................................... 134 5.49 Receive Channel 0-7 Completion Pointer Register (RXnCP) ........................................... 135 5.50 Network Statistics Registers ..................................................
Page 10 - Read This First; About This Manual; TMS320C6455 Technical Reference (literature number; Trademarks
Preface SPRU975B – August 2006 Read This First About This Manual This document provides a functional description of the Ethernet Media Access Controller (EMAC) andPhysical layer (PHY) device Management Data Input/Output (MDIO) module integrated withTMS320C645x devices. Notational Conventions This do...
Page 11 - Introduction; Purpose of the Peripheral
1 Introduction 1.1 Purpose of the Peripheral 1.2 Features User's Guide SPRU975B – August 2006 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) This document provides a functional description of the Ethernet Media Access Controller (EMAC) andPhysical layer (PHY) device Mana...
Page 12 - Functional Block Diagram; Figure 1. EMAC and MDIO Block Diagram; Figure 1
www.ti.com 1.3 Functional Block Diagram Configuration bus DMA memory transfer controller Peripheral bus EMAC control module EMAC module MDIO module MII MDIO bus EMAC/MDIO interrupt Interrupt controller RMII GMII RGMII Introduction Figure 1 shows the three main functional modules of the EMAC/MDIO per...
Page 13 - Industry Standard(s) Compliance Statement
www.ti.com 1.4 Industry Standard(s) Compliance Statement Introduction The EMAC peripheral conforms to the IEEE 802.3 standard, describing the “Carrier Sense Multiple Accesswith Collision Detection (CSMA/CD) Access Method and Physical Layer” specifications. ISO / IEC hasalso adopted the IEEE 802.3 st...
Page 14 - Clock Control; MII Clocking; EMAC Functional Architecture
www.ti.com 2 EMAC Functional Architecture 2.1 Clock Control 2.1.1 MII Clocking 2.1.2 RMII Clocking 2.1.3 GMII Clocking EMAC Functional Architecture This chapter discusses the architecture and basic function of the EMAC peripheral. The frequencies for the transmit and receive clocks are fixed by the ...
Page 15 - RGMII Clocking; Memory Map
www.ti.com 2.1.4 RGMII Clocking 2.2 Memory Map EMAC Functional Architecture For timing purposes, data in 10/100 mode is transmitted and received with reference to MTCLK andMRCLK, respectively. For 1000 Mbps mode, receive timing is the same, but transmit is relative toGMTCLK. When the RGMII interface...
Page 16 - System Level Connections; Media Independent Interface (MII) Connections; Table 1; Table 1. Interface Selection Pins; Figure 2; Figure 2. Ethernet Configuration with MII Interface
www.ti.com 2.3 System Level Connections 2.3.1 Media Independent Interface (MII) Connections MTCLK MTXD[3−0] MTXEN MCOL MCRS MRCLK MRXD[3−0] MRXDV MRXER MDCLK MDIO Physical layer device (PHY) System core Transformer 2.5 MHz or 25 MHz RJ−45 EMAC MDIO EMAC Functional Architecture The C645x device suppo...
Page 17 - Table 2; Table 2. EMAC and MDIO Signals for MII Interface
www.ti.com EMAC Functional Architecture Table 2 summarizes the individual EMAC and MDIO signals for the MII interface. For more information, refer to either the IEEE 802.3 standard or ISO/IEC 8802-3:2000(E). The EMAC module does not include a transmit error (MTXER) pin. If a transmit error occurs, C...
Page 18 - Reduced Media Independent Interface (RMII) Connections; Figure 3; Figure 3. Ethernet Configuration with RMII Interface
www.ti.com 2.3.2 Reduced Media Independent Interface (RMII) Connections MTXD[1−0] MTXEN MCRSDV MREFCLK MRXD[1−0] MRXER MDCLK MDIO Physical layer device (PHY) System core Transformer RJ−45 EMAC MDIO EMAC Functional Architecture Figure 3 shows a device with integrated EMAC and MDIO interfaced via a RM...
Page 19 - Table 3; Table 3. EMAC and MDIO Signals for RMII Interface
www.ti.com EMAC Functional Architecture The RMII interface has the same functionality as the MII, but it does so with a reduced number of pins,thus lowering the total cost for an application. In devices incorporating many PHY interfaces such asswitches, the number of pins can add significant cost as...
Page 20 - Gigabit Media Independent Interface (GMII) Connections; Figure 4; Figure 4. Ethernet Configuration with GMII Interface
www.ti.com 2.3.3 Gigabit Media Independent Interface (GMII) Connections MTCLK MTXD[7−0] MTXEN MCOL MCRS MRCLK MRXD[7−0] MRXDV MRXER MDCLK MDIO Physical layer device (PHY) System core Transformer 2.5 MHz, 25 MHz, RJ−45 EMAC MDIO GMTCLK or 125 MHz EMAC Functional Architecture Figure 4 shows a device w...
Page 21 - Table 4; Table 4. EMAC and MDIO Signals for GMII Interface
www.ti.com EMAC Functional Architecture Table 4 summarizes the individual EMAC and MDIO signals for the GMII interface. Table 4. EMAC and MDIO Signals for GMII Interface Signal Name I/O Description MTCLK I Transmit clock (MTCLK). The transmit clock is a continuous clock that provides the timingrefer...
Page 22 - Reduced Gigabit Media Independent Interface (RGMII) Connections; Figure 5; Figure 5. Ethernet Configuration with RGMII Interface; MRXDV signal (multiplexed in the RXCTL signal) is true
www.ti.com 2.3.4 Reduced Gigabit Media Independent Interface (RGMII) Connections TXC TXD[3−0] TXCTL REFCLK RXC RXD[3−0] RXCTL MDCLK MDIO Physical layer device (PHY) System core Transformer 2.5 MHz25 MHz, or 125 MHz RJ−45 EMAC MDIO EMAC Functional Architecture Figure 5 shows a device with integrated ...
Page 23 - Table 5; Table 5. EMAC and MDIO Signals for RGMII Interface
www.ti.com EMAC Functional Architecture Table 5 summarizes the individual EMAC and MDIO signals for the RGMII interface. Table 5. EMAC and MDIO Signals for RGMII Interface Signal Name I/O Description TXC O Transmit clock (TXC). The transmit clock is a continuous clock that provides the timingreferen...
Page 24 - Ethernet Protocol Overview; Ethernet Frame Format; Figure 6; Figure 6. Ethernet Frame
www.ti.com 2.4 Ethernet Protocol Overview 2.4.1 Ethernet Frame Format Preamble SFD Destination Source Len Data 7 1 6 6 2 46 − (RXMAXLEN - 18) 4 FCS Number of bytes Legend: SFD=Start Frame Delimiter; FCS=Frame Check Sequence (CRC) EMAC Functional Architecture Ethernet provides an unreliable, connecti...
Page 25 - Multiple Access Protocol
www.ti.com 2.4.2 Multiple Access Protocol EMAC Functional Architecture Nodes in an ethernet local area network are interconnected by a broadcast channel. As a result, when anEMAC port transmits a frame, all of the adapters on the local network receive the frame. Carrier sensemultiple access with col...
Page 26 - Programming Interface; Packet Buffer Descriptors; The basic descriptor format is shown in; Figure 7. Basic Descriptor Format
www.ti.com 2.5 Programming Interface 2.5.1 Packet Buffer Descriptors EMAC Functional Architecture The buffer descriptor is a central part of the EMAC module. It determines how the application softwaredescribes ethernet packets to be sent and empty buffers to be filled with incoming packet data. The ...
Page 27 - Figure 8; Figure 8. Typical Descriptor Linked List
www.ti.com SOP | EOP 60 0 60 pBuffer pNext Packet A 60 bytes 0 SOP Fragment 1 Packet B 512 1514 pBuffer pNext 512 bytes EOP 0 0 −−− Packet B Fragment 3 500 bytes 502 pBuffer −−− 500 pNext −−− pBuffer pNext Packet B Fragment 2 502 bytes SOP | EOP 0 1514 bytes Packet C 1514 pBuffer pNext (NULL) 1514 E...
Page 28 - Transmit and Receive Descriptor Queues; The EMAC module processes descriptors in linked list chains (
www.ti.com 2.5.2 Transmit and Receive Descriptor Queues EMAC Functional Architecture The EMAC module processes descriptors in linked list chains ( Section 2.5.1 ). The lists controlled by the EMAC are maintained by the application software via the head descriptor pointer (HDP) registers. Sincethe EM...
Page 29 - Transmit and Receive EMAC Interrupts; The EMAC processes descriptors in linked list chains (
www.ti.com 2.5.3 Transmit and Receive EMAC Interrupts EMAC Functional Architecture The EMAC processes descriptors in linked list chains ( Section 2.5.1 ), using the linked list queue mechanism ( Section 2.5.2 ). The EMAC synchronizes the descriptor list processing by using interrupts to the software...
Page 30 - Transmit Buffer Descriptor Format; Figure 9; Figure 9. Transmit Descriptor Format; Example 1. Transmit Descriptor in C Structure Format
www.ti.com 2.5.4 Transmit Buffer Descriptor Format EMAC Functional Architecture A transmit (TX) buffer descriptor ( Figure 9 ) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 1 shows the transmit buffer descriptor des...
Page 31 - The range of legal values for this field is 0 to (Buffer Length – 1).
www.ti.com 2.5.4.1 Next Descriptor Pointer 2.5.4.2 Buffer Pointer 2.5.4.3 Buffer Offset 2.5.4.4 Buffer Length 2.5.4.5 Packet Length 2.5.4.6 Start of Packet (SOP) Flag EMAC Functional Architecture The next descriptor pointer indicates the 32-bit word aligned memory address of the next buffer descript...
Page 33 - Receive Buffer Descriptor Format; ) is a contiguous block of four 32-bit data words aligned on a; Figure 10. Receive Descriptor Format; Example 2. Receive Descriptor in C Structure Format
www.ti.com 2.5.5 Receive Buffer Descriptor Format EMAC Functional Architecture A receive (RX) buffer descriptor ( Figure 10 ) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 2 shows the receive descriptor described by...
Page 37 - EMAC Control Module; Internal Memory; The EMAC control module (; Figure 11. EMAC Control Module Block Diagram
www.ti.com 2.6 EMAC Control Module Arbiter and bus switches CPU DMA Controllers 8K byte descriptor memory Configuration registers Interrupt logic Single interruptto CPU EMAC interrupts MDIO interrupts Configuration bus Transmit and Receive 2.6.1 Internal Memory 2.6.2 Bus Arbiter EMAC Functional Arch...
Page 38 - ) interfaces to PHY components through two MDIO pins (MDCLK and
www.ti.com 2.6.3 Interrupt Control 2.7 Management Data Input/Output (MDIO) Module 2.7.1 MDIO Module Components EMAC Functional Architecture The EMAC control module combines the multiple interrupt conditions generated by the EMAC and MDIOmodules into a single interrupt signal that is mapped to a CPU ...
Page 39 - Figure 12. MDIO Module Block Diagram
www.ti.com EMAC control module Control registers and logic PHY monitoring Peripheral clock MDIO clock generator USERINT MDIO interface polling PHY MDCLK MDIO LINKINT Configuration bus 2.7.1.1 MDIO Clock Generator 2.7.1.2 Global PHY Detection and Link State Monitoring 2.7.1.3 Active PHY Monitoring 2....
Page 40 - MDIO Module Operational Overview; Initializing the MDIO Module; register can determine which of those (if any) already have a link.
www.ti.com 2.7.2 MDIO Module Operational Overview 2.7.2.1 Initializing the MDIO Module EMAC Functional Architecture The MDIO module implements the 802.3 serial management interface to simultaneously interrogate andcontrol up to two Ethernet PHYs, using a shared two-wired bus. It separately performs ...
Page 41 - desired PHY and PHY register.
www.ti.com 2.7.2.2 Writing Data to a PHY Register 2.7.2.3 Reading Data From a PHY Register 2.7.2.4 Example of MDIO Register Access Code EMAC Functional Architecture The MDIO module includes a user access register (USERACCESSn) to directly access a specified PHYdevice. To write a PHY register, perfor...
Page 42 - Example 3
www.ti.com EMAC Functional Architecture The implementation of these macros using the register layer Chip Support Library (CSL) is shown in Example 3 (USERACCESS0 is assumed). Note that this implementation does not check the ACK bit on PHY register reads; in other words, it doesnot follow the procedu...
Page 43 - EMAC Module; EMAC Module Components; Receive DMA Engine; Figure 13. EMAC Module Block Diagram
www.ti.com 2.8 EMAC Module 2.8.1 EMAC Module Components Clock and reset logic Receive DMA engine Interrupt controller Transmit DMA engine Control registers Configuration bus EMAC control module Configuration bus RAM State FIFO Receive FIFO Transmit MAC transmitter Statistics receiver MAC SYNC MII RM...
Page 45 - Clock and Reset Logic; EMAC Module Operational Overview
www.ti.com 2.8.1.12 Clock and Reset Logic 2.8.2 EMAC Module Operational Overview EMAC Functional Architecture The clock and reset sub-module generates all the clocks and resets for the EMAC peripheral. After reset, initialization, and configuration of the EMAC, the application software running on th...
Page 46 - Media Independent Interfaces; Data Reception; Receive Control; Receive buffer flow control
www.ti.com 2.9 Media Independent Interfaces 2.9.1 Data Reception 2.9.1.1 Receive Control 2.9.1.2 Receive Inter-Frame Interval 2.9.1.3 Receive Flow Control EMAC Functional Architecture The EMAC supports four physical interfaces to external devices: Media Independent Interface (MII),Reduced Media Inde...
Page 47 - The EMAC transmits pause frames as described below:
www.ti.com 2.9.1.4 Collision-Based Receive Buffer Flow Control 2.9.1.5 IEEE 802.3X Based Receive Buffer Flow Control EMAC Functional Architecture Collision-based receive buffer flow control provides a means of preventing frame reception when theEMAC is operating in half-duplex mode (FULLDUPLEX bit i...
Page 48 - Data Transmission; Transmit Control
www.ti.com 2.9.2 Data Transmission 2.9.2.1 Transmit Control 2.9.2.2 CRC Insertion 2.9.2.3 Adaptive Performance Optimization (APO) 2.9.2.4 Interpacket-Gap (IPG) Enforcement 2.9.2.5 Back Off EMAC Functional Architecture The EMAC passes data to the PHY from the transmit FIFO (when enabled). Data is syn...
Page 49 - Transmit Flow Control
www.ti.com 2.9.2.6 Transmit Flow Control 2.9.2.7 Speed, Duplex, and Pause Frame Support EMAC Functional Architecture When enabled, incoming pause frames are acted upon to prevent the EMAC from transmitting any furtherframes. Incoming pause frames are only acted upon when the FULLDUPLEX and TXFLOWEN ...
Page 50 - Packet Receive Operation; Receive DMA Host Configuration; Initialize the receive addresses
www.ti.com 2.10 Packet Receive Operation 2.10.1 Receive DMA Host Configuration 2.10.2 Receive Channel Enabling EMAC Functional Architecture To configure the receive DMA for operation, the host must perform the following actions: • Initialize the receive addresses • Initialize the RXnHDP registers to...
Page 52 - Any current frame in reception completes normally.
www.ti.com 2.10.5 Host Free Buffer Tracking 2.10.6 Receive Channel Teardown 2.10.7 Receive Frame Classification EMAC Functional Architecture The host must track free buffers for each enabled channel (including unicast, multicast, broadcast, andpromiscuous) if receive QOS or receive flow control is u...
Page 53 - Promiscuous Receive Mode; Table 8; Table 8. Receive Frame Treatment Summary
www.ti.com 2.10.8 Promiscuous Receive Mode EMAC Functional Architecture When the promiscuous receive mode is enabled by setting the RXCAFEN bit in the RXMBPENABLEregister, non-address matching frames that would normally be filtered are transferred to the promiscuouschannel. Address matching frames t...
Page 54 - Receive Overrun; Table 9; Table 9. Middle of Frame Overrun Treatment
www.ti.com 2.10.9 Receive Overrun EMAC Functional Architecture Table 8. Receive Frame Treatment Summary (continued) RXMBPENABLE Bits ADDRESS MATCH RXCAFEN RXCEFEN RXCMFEN RXCSFEN Frame treatment 1 X 1 0 1 Proper/oversize/jabber/fragment/undersized/code/align/CRC data frames transferred to addressmat...
Page 55 - Packet Transmit Operation; Transmit DMA Host Configuration; Receive and Transmit Latency; Initialize the TXnHDP registers to zero.
www.ti.com 2.11 Packet Transmit Operation 2.11.1 Transmit DMA Host Configuration 2.11.2 Transmit Channel Teardown 2.12 Receive and Transmit Latency EMAC Functional Architecture The transmit DMA is an eight channel interface. Priority between the eight queues may be either fixed orround robin as sele...
Page 56 - Software Reset Considerations
www.ti.com 2.13 Transfer Node Priority 2.14 Reset Considerations 2.14.1 Software Reset Considerations 2.14.2 Hardware Reset Considerations EMAC Functional Architecture Latency to system’s internal and external RAM can be controlled through the use of the transfer nodepriority allocation register in ...
Page 57 - Setting the interrupt pace count (using EWINTTCNT)
www.ti.com 2.15 Initialization 2.15.1 Enabling the EMAC/MDIO Peripheral 2.15.2 EMAC Control Module Initialization EMAC Functional Architecture When the device is powered on, the EMAC peripheral is disabled. Prior to EMAC-specific initialization, theEMAC must be enabled; otherwise its registers canno...
Page 58 - MDIO Module Initialization; Example 4. EMAC Control Module Initialization Code; Example 5
www.ti.com 2.15.3 MDIO Module Initialization EMAC Functional Architecture Example 4. EMAC Control Module Initialization Code Uint32 tmpval; /* // Globally disable EMAC/MDIO interrupts in the control module /* CSL_FINST(ECTL_REGS->EWCTL, ECTL_EWCTL_INTEN, DISABLE ); /* Wait about 100 cycles */ for...
Page 59 - EMAC Module Initialization; want to allow to be received.
www.ti.com 2.15.4 EMAC Module Initialization EMAC Functional Architecture The EMAC module sends and receives data packets over the network by maintaining up to 8 transmit andreceive descriptor queues. The EMAC module configuration must also be kept current based on the PHYnegotiation results returne...
Page 60 - Interrupt Support; EMAC Module Interrupt Events and Requests; Transmit Packet Completion Interrupts; STATPEND: Statistics interrupt
www.ti.com 2.16 Interrupt Support 2.16.1 EMAC Module Interrupt Events and Requests 2.16.1.1 Transmit Packet Completion Interrupts EMAC Functional Architecture The EMAC/MDIO generates 18 interrupt events, as follows: • TXPENDn: Transmit packet completion interrupt for transmit channels 7 through 0 • ...
Page 62 - Host Error Interrupt; MDIO Module Interrupt Events and Requests; Link Change Interrupt
www.ti.com 2.16.1.4 Host Error Interrupt 2.16.2 MDIO Module Interrupt Events and Requests 2.16.2.1 Link Change Interrupt 2.16.2.2 User Access Completion Interrupt EMAC Functional Architecture The host error interrupt (HOSTPEND) is issued, if enabled, under error conditions due to the handling ofbuff...
Page 63 - Power Management; Table 10. Emulation Control
www.ti.com 2.16.3 Proper Interrupt Processing 2.16.4 Interrupt Multiplexing 2.17 Power Management 2.18 Emulation Considerations EMAC Functional Architecture All the interrupts signaled from the EMAC and MDIO modules are level-driven. If they remain active, theirlevel remains constant. However, the C...
Page 64 - EMAC Control Module Registers; manual for the memory address of these registers.; Table 11. EMAC Control Module Registers; and described in; Figure 14. EMAC Control Module Interrupt Control Register (EWCTL)
www.ti.com 3 EMAC Control Module Registers 3.1 Introduction 3.2 EMAC Control Module Interrupt Control Register (EWCTL) EMAC Control Module Registers Table 11 lists the memory-mapped registers for the EMAC Control Module. See the device-specific data manual for the memory address of these registers. ...
Page 65 - EMAC Control Module Interrupt Timer Count Register (EWINTTCNT); and
www.ti.com 3.3 EMAC Control Module Interrupt Timer Count Register (EWINTTCNT) EMAC Control Module Registers The EMAC control module interrupt timer count register (EWINTTCNT) is used to control the generation ofback-to-back interrupts from the EMAC and MDIO modules. The value of this timer count is ...
Page 66 - MDIO Registers
www.ti.com 4 MDIO Registers 4.1 Introduction MDIO Registers Table 14 lists the memory-mapped registers for the Management Data Input/Output (MDIO). See the device-specific data manual for the memory address of these registers. Table 14. Management Data Input/Output (MDIO) Registers Offset Acronym Re...
Page 67 - The MDIO version register (VERSION) is shown in
www.ti.com 4.2 MDIO Version Register (VERSION) MDIO Registers The MDIO version register (VERSION) is shown in Figure 16 and described in Table 15 . Figure 16. MDIO Version Register (VERSION) 31 16 MODID R-7 15 8 7 0 REVMAJ REVMIN R-1 R-3 LEGEND: R = Read only; R/W = Read/Write; -n = value after rese...
Page 68 - The MDIO control register (CONTROL) is shown in
www.ti.com 4.3 MDIO Control Register (CONTROL) MDIO Registers The MDIO control register (CONTROL) is shown in Figure 17 and described in Table 16 . Figure 17. MDIO Control Register (CONTROL) 31 30 29 28 24 23 21 20 19 18 17 16 IDLE ENABLE Reserved HIGHEST_USER_CHANNEL Reserved PREAMBLE FAULT FAULT R...
Page 69 - The PHY acknowledge status register (ALIVE) is shown in
www.ti.com 4.4 PHY Acknowledge Status Register (ALIVE) MDIO Registers The PHY acknowledge status register (ALIVE) is shown in Figure 18 and described in Table 17 . Figure 18. PHY Acknowledge Status Register (ALIVE) 31 16 ALIVE R/WC-0 15 0 ALIVE R/WC-0 LEGEND: R/W = Read/Write; R/WC = Read/Write 1 to...
Page 70 - The PHY link status register (LINK) is shown in
www.ti.com 4.5 PHY Link Status Register (LINK) MDIO Registers The PHY link status register (LINK) is shown in Figure 19 and described in Table 18 . Figure 19. PHY Link Status Register (LINK) 31 16 LINK R-0 15 0 LINK R-0 LEGEND: R = Read only; -n = value after reset Table 18. PHY Link Status Register...
Page 71 - Descriptions
www.ti.com 4.6 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) MDIO Registers The MDIO link status change interrupt (unmasked) register (LINKINTRAW) is shown in Figure 20 and described in Table 19 . Figure 20. MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) 31 1...
Page 76 - Field Descriptions
www.ti.com 4.11 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) MDIO Registers The MDIO user command complete interrupt mask clear register (USERINTMASKCLEAR) is shown in Figure 25 and described in Table 24 . Figure 25. MDIO User Command Complete Interrupt Mask Clear Regi...
Page 77 - The MDIO user access register 0 (USERACCESS0) is shown in
www.ti.com 4.12 MDIO User Access Register 0 (USERACCESS0) MDIO Registers The MDIO user access register 0 (USERACCESS0) is shown in Figure 26 and described in Table 25 . Figure 26. MDIO User Access Register 0 (USERACCESS0) 31 30 29 28 26 25 21 20 16 GO WRITE ACK Reserved REGADR PHYADR R/WS-0 R/W-0 R/...
Page 78 - The MDIO user PHY select register 0 (USERPHYSEL0) is shown in
www.ti.com 4.13 MDIO User PHY Select Register 0 (USERPHYSEL0) MDIO Registers The MDIO user PHY select register 0 (USERPHYSEL0) is shown in Figure 27 and described in Table 26 . Figure 27. MDIO User PHY Select Register 0 (USERPHYSEL0) 31 16 Reserved R-0 15 8 7 6 5 4 0 Reserved LINKSEL LINKINTENB Rese...
Page 79 - The MDIO user access register 1 (USERACCESS1) is shown in
www.ti.com 4.14 MDIO User Access Register 1 (USERACCESS1) MDIO Registers The MDIO user access register 1 (USERACCESS1) is shown in Figure 28 and described in Table 27 . Figure 28. MDIO User Access Register 1 (USERACCESS1) 31 30 29 28 26 25 21 20 16 GO WRITE ACK Reserved REGADR PHYADR R/WS-0 R/W-0 R/...
Page 80 - The MDIO user PHY select register 1 (USERPHYSEL1) is shown in
www.ti.com 4.15 MDIO User PHY Select Register 1 (USERPHYSEL1) MDIO Registers The MDIO user PHY select register 1 (USERPHYSEL1) is shown in Figure 29 and described in Table 28 . Figure 29. MDIO User PHY Select Register 1 (USERPHYSEL1) 31 16 Reserved R-0 15 8 7 6 5 4 0 Reserved LINKSEL LINKINTENB Rese...
Page 85 - Transmit Identification and Version Register (TXIDVER); Figure 30. Transmit Identification and Version Register (TXIDVER)
www.ti.com 5.2 Transmit Identification and Version Register (TXIDVER) EMAC Port Registers The transmit identification and version register (TXIDVER) is shown in Figure 30 and described in Table 30 . Figure 30. Transmit Identification and Version Register (TXIDVER) 31 16 TXIDENT R-12 15 8 7 0 TXMAJOR...
Page 86 - The transmit control register (TXCONTROL) is shown in
www.ti.com 5.3 Transmit Control Register (TXCONTROL) EMAC Port Registers The transmit control register (TXCONTROL) is shown in Figure 31 and described in Table 31 . Figure 31. Transmit Control Register (TXCONTROL) 31 16 Reserved R-0 15 1 0 Reserved TXEN R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read o...
Page 87 - The transmit teardown register (TXTEARDOWN) is shown in
www.ti.com 5.4 Transmit Teardown Register (TXTEARDOWN) EMAC Port Registers The transmit teardown register (TXTEARDOWN) is shown in Figure 32 and described in Table 32 . Figure 32. Transmit Teardown Register (TXTEARDOWN) 31 16 Reserved R-0 15 3 2 0 Reserved TXTDNCH R-0 R/W-0 LEGEND: R/W = Read/Write;...
Page 88 - Receive Identification and Version Register (RXIDVER); Figure 33. Receive Identification and Version Register (RXIDVER)
www.ti.com 5.5 Receive Identification and Version Register (RXIDVER) EMAC Port Registers The receive identification and version register (RXIDVER) is shown in Figure 33 and described in Table 33 . Figure 33. Receive Identification and Version Register (RXIDVER) 31 16 RXIDENT R-12 15 8 7 0 RXMAJORVER...
Page 89 - The receive control register (RXCONTROL) is shown in; Table 34. Receive Control Register (RXCONTROL) Field Descriptions
www.ti.com 5.6 Receive Control Register (RXCONTROL) EMAC Port Registers The receive control register (RXCONTROL) is shown in Figure 34 and described in Table 34 . Figure 34. Receive Control Register (RXCONTROL) 31 16 Reserved R-0 15 1 0 Reserved RXEN R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only...
Page 90 - The receive teardown register (RXTEARDOWN) is shown in
www.ti.com 5.7 Receive Teardown Register (RXTEARDOWN) EMAC Port Registers The receive teardown register (RXTEARDOWN) is shown in Figure 35 and described in Table 35 . Figure 35. Receive Teardown Register (RXTEARDOWN) 31 16 Reserved R-0 15 3 2 0 Reserved RXTDNCH R-0 R/W-0 LEGEND: R/W = Read/Write; R ...
Page 91 - and described
www.ti.com 5.8 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) EMAC Port Registers The transmit interrupt status (unmasked) register (TXINTSTATRAW) is shown in Figure 36 and described in Table 36 . Figure 36. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) 31 16 Reserved R-...
Page 93 - Figure 38. Transmit Interrupt Mask Set Register (TXINTMASKSET)
www.ti.com 5.10 Transmit Interrupt Mask Set Register (TXINTMASKSET) EMAC Port Registers The transmit interrupt mask set register (TXINTMASKSET) is shown in Figure 38 and described in Table 38 . Figure 38. Transmit Interrupt Mask Set Register (TXINTMASKSET) 31 16 Reserved R-0 15 8 7 6 5 4 3 2 1 0 Res...
Page 95 - The MAC input vector register (MACINVECTOR) is shown in
www.ti.com 5.12 MAC Input Vector Register (MACINVECTOR) EMAC Port Registers The MAC input vector register (MACINVECTOR) is shown in Figure 40 and described in Table 40 . Figure 40. MAC Input Vector Register (MACINVECTOR) 31 30 29 18 17 16 USER LINK Reserved HOST STAT INT INT PEND PEND R-0 R-0 R-0 R-...
Page 98 - The receive interrupt mask set register (RXINTMASKSET) is shown in; Figure 43. Receive Interrupt Mask Set Register (RXINTMASKSET)
www.ti.com 5.15 Receive Interrupt Mask Set Register (RXINTMASKSET) EMAC Port Registers The receive interrupt mask set register (RXINTMASKSET) is shown in Figure 43 and described in Table 43 . Figure 43. Receive Interrupt Mask Set Register (RXINTMASKSET) 31 16 Reserved R-0 15 8 7 6 5 4 3 2 1 0 Reserv...
Page 99 - Figure 44. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)
www.ti.com 5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) EMAC Port Registers The receive interrupt mask clear register (RXINTMASKCLEAR) is shown in Figure 44 and described in Table 44 . Figure 44. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) 31 16 Reserved R-0 15 8 7 6 5 4 3 ...
Page 102 - The MAC interrupt mask set register (MACINTMASKSET) is shown in
www.ti.com 5.19 MAC Interrupt Mask Set Register (MACINTMASKSET) EMAC Port Registers The MAC interrupt mask set register (MACINTMASKSET) is shown in Figure 47 and described in Table 47 . Figure 47. MAC Interrupt Mask Set Register (MACINTMASKSET) 31 16 Reserved R-0 15 2 1 0 Reserved HOST STAT MASK MAS...
Page 103 - Figure 48. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)
www.ti.com 5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) EMAC Port Registers The MAC interrupt mask clear register (MACINTMASKCLEAR) is shown in Figure 48 and described in Table 48 . Figure 48. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) 31 16 Reserved R-0 15 2 1 0 Reserved HOST S...
Page 106 - The receive unicast enable set register (RXUNICASTSET) is shown in; Figure 50. Receive Unicast Enable Set Register (RXUNICASTSET)
www.ti.com 5.22 Receive Unicast Enable Set Register (RXUNICASTSET) EMAC Port Registers Table 49. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions (continued) Bit Field Value Description 2-0 RXMULTCH 0-3h Receive multicast channel select 0 Select channe...
Page 107 - The receive unicast clear register (RXUNICASTCLEAR) is shown in
www.ti.com 5.23 Receive Unicast Clear Register (RXUNICASTCLEAR) EMAC Port Registers The receive unicast clear register (RXUNICASTCLEAR) is shown in Figure 51 and described in Table 51 . Figure 51. Receive Unicast Clear Register (RXUNICASTCLEAR) 31 16 Reserved R-0 15 8 7 6 5 4 3 2 1 0 Reserved RXCH7E...
Page 108 - The receive maximum length register (RXMAXLEN) is shown in
www.ti.com 5.24 Receive Maximum Length Register (RXMAXLEN) EMAC Port Registers The receive maximum length register (RXMAXLEN) is shown in Figure 52 and described in Table 52 . Figure 52. Receive Maximum Length Register (RXMAXLEN) 31 16 Reserved R-0 15 0 RXMAXLEN R/W-1518 LEGEND: R/W = Read/Write; R ...
Page 109 - The receive buffer offset register (RXBUFFEROFFSET) is shown in
www.ti.com 5.25 Receive Buffer Offset Register (RXBUFFEROFFSET) EMAC Port Registers The receive buffer offset register (RXBUFFEROFFSET) is shown in Figure 53 and described in Table 53 . Figure 53. Receive Buffer Offset Register (RXBUFFEROFFSET) 31 16 Reserved R-0 15 0 RXBUFFEROFFSET R/W-0 LEGEND: R/...
Page 113 - The MAC control register (MACCONTROL) is shown in; Table 57. MAC Control Register (MACCONTROL) Field Descriptions
www.ti.com 5.29 MAC Control Register (MACCONTROL) EMAC Port Registers The MAC control register (MACCONTROL) is shown in Figure 57 and described in Table 57 . Figure 57. MAC Control Register (MACCONTROL) 31 24 Reserved R-0 23 19 18 17 16 Reserved RGMIIEN GIGFORCE RMIIDUPLEX- MODE R-0 R/W-0 R/W-0 R/W-...
Page 115 - The MAC status register (MACSTATUS) is shown in
www.ti.com 5.30 MAC Status Register (MACSTATUS) EMAC Port Registers The MAC status register (MACSTATUS) is shown in Figure 58 and described in Table 58 . Figure 58. MAC Status Register (MACSTATUS) 31 30 24 IDLE Reserved R-0 R-0 23 20 19 18 16 TXERRCODE Reserved TXERRCH R-0 R-0 R-0 15 12 11 10 8 RXER...
Page 117 - The emulation control register (EMCONTROL) is shown in
www.ti.com 5.31 Emulation Control Register (EMCONTROL) EMAC Port Registers The emulation control register (EMCONTROL) is shown in Figure 59 and described in Table 59 . Figure 59. Emulation Control Register (EMCONTROL) 31 16 Reserved R-0 15 2 1 0 Reserved SOFT FREE R-0 R/W-0 R/W-0 LEGEND: R/W = Read/...
Page 118 - The FIFO control register (FIFOCONTROL) is shown in; Table 60. FIFO Control Register (FIFOCONTROL) Field Descriptions
www.ti.com 5.32 FIFO Control Register (FIFOCONTROL) EMAC Port Registers The FIFO control register (FIFOCONTROL) is shown in Figure 60 and described in Table 60 . Figure 60. FIFO Control Register (FIFOCONTROL) 31 23 22 16 Reserved RXFIFOFLOWTHRESH R-0 R/W-2 15 5 4 0 Reserved TXCELLTHRESH R-0 R/W-24 L...
Page 119 - The MAC configuration register (MACCONFIG) is shown in
www.ti.com 5.33 MAC Configuration Register (MACCONFIG) EMAC Port Registers The MAC configuration register (MACCONFIG) is shown in Figure 61 and described in Table 61 . Figure 61. MAC Configuration Register (MACCONFIG) 31 24 23 16 TXCELLDEPTH RXCELLDEPTH R-24 R-68 15 8 7 0 ADDRESSTYPE MACCFIG R-2 R-3...
Page 120 - The Soft Reset Register (SOFTRESET) is shown in
www.ti.com 5.34 Soft Reset Register (SOFTRESET) EMAC Port Registers The Soft Reset Register (SOFTRESET) is shown in Figure 62 and described in Table 62 . Figure 62. Soft Reset Register (SOFTRESET) 31 16 Reserved R-0 15 1 0 Reserved SOFTRESET R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = va...
Page 121 - Figure 63. MAC Source Address Low Bytes Register (MACSRCADDRLO)
www.ti.com 5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) EMAC Port Registers The MAC source address low bytes register (MACSRCADDRLO) is shown in Figure 63 and described in Table 63 . Figure 63. MAC Source Address Low Bytes Register (MACSRCADDRLO) 31 16 Reserved R-0 15 8 7 0 MACSRCADDR0 ...
Page 122 - Figure 64. MAC Source Address High Bytes Register (MACSRCADDRHI)
www.ti.com 5.36 MAC Source Address High Bytes Register (MACSRCADDRHI) EMAC Port Registers The MAC Source Address High Bytes Register (MACSRCADDRHI) is shown in Figure 64 and described in Table 64 . Figure 64. MAC Source Address High Bytes Register (MACSRCADDRHI) 31 24 23 16 MACSRCADDR2 MACSRCADDR3 R...
Page 123 - The MAC hash address register 1 (MACHASH1) is shown in; Table 65. MAC Hash Address Register 1 (MACHASH1) Field Descriptions
www.ti.com 5.37 MAC Hash Address Register 1 (MACHASH1) EMAC Port Registers The MAC hash registers allow group addressed frames to be accepted on the basis of a hash function ofthe address. The hash function creates a 6-bit data value (hash_fun) from the 48-bit destination address(DA) as follows: Has...
Page 124 - The MAC hash address register 2 (MACHASH2) is shown in; Table 66. MAC Hash Address Register 2 (MACHASH2) Field Descriptions
www.ti.com 5.38 MAC Hash Address Register 2 (MACHASH2) EMAC Port Registers The MAC hash address register 2 (MACHASH2) is shown in Figure 66 and described in Table 66 . Figure 66. MAC Hash Address Register 2 (MACHASH2) 31 16 MACHASH2 R/W-0 15 0 MACHASH2 R/W-0 LEGEND: R/W = Read/Write; -n = value afte...
Page 125 - The back off test register (BOFFTEST) is shown in; Table 67. Back Off Test Register (BOFFTEST) Field Descriptions
www.ti.com 5.39 Back Off Test Register (BOFFTEST) EMAC Port Registers The back off test register (BOFFTEST) is shown in Figure 67 and described in Table 67 . Figure 67. Back Off Random Number Generator Test Register (BOFFTEST) 31 26 25 16 Reserved RNDNUM R-0 R-0 15 12 11 10 9 0 COLLCOUNT Reserved TX...
Page 126 - Figure 68. Transmit Pacing Algorithm Test Register (TPACETEST)
www.ti.com 5.40 Transmit Pacing Algorithm Test Register (TPACETEST) EMAC Port Registers The Transmit Pacing Algorithm Test Register (TPACETEST) is shown in Figure 68 and described in Table 68 . Figure 68. Transmit Pacing Algorithm Test Register (TPACETEST) 31 16 Reserved R-0 15 5 4 0 Reserved PACEVA...
Page 127 - The receive pause timer register (RXPAUSE) is shown in
www.ti.com 5.41 Receive Pause Timer Register (RXPAUSE) EMAC Port Registers The receive pause timer register (RXPAUSE) is shown in Figure 69 and described in Table 69 . Figure 69. Receive Pause Timer Register (RXPAUSE) 31 16 Reserved R-0 15 0 PAUSETIMER R-0 LEGEND: R = Read only; -n = value after res...
Page 128 - The Transmit Pause Timer Register (TXPAUSE) is shown in
www.ti.com 5.42 Transmit Pause Timer Register (TXPAUSE) EMAC Port Registers The Transmit Pause Timer Register (TXPAUSE) is shown in Figure 70 and described in Table 70 . Figure 70. Transmit Pause Timer Register (TXPAUSE) 31 16 Reserved R-0 15 0 PAUSETIMER R-0 LEGEND: R = Read only; -n = value after ...
Page 129 - The MAC address low bytes register (MACADDRLO) is shown in
www.ti.com 5.43 MAC Address Low Bytes Register (MACADDRLO) EMAC Port Registers The MAC address low bytes register (MACADDRLO) is shown in Figure 71 and described in Table 71 . Figure 71. MAC Address Low Bytes Register (MACADDRLO) 31 21 20 19 18 16 Reserved VALID MATCH CHANNEL FILT R-0 R/W-x R/W-x R/...
Page 130 - The MAC address high bytes register (MACADDRHI) is shown in
www.ti.com 5.44 MAC Address High Bytes Register (MACADDRHI) EMAC Port Registers The MAC address high bytes register (MACADDRHI) is shown in Figure 72 and described in Table 72 . Figure 72. MAC Address High Bytes Register (MACADDRHI) 31 24 23 16 MACADDR2 MACADDR3 R/W-0 R/W-0 15 8 7 0 MACADDR4 MACADDR...
Page 131 - The MAC index register (MACINDEX) is shown in
www.ti.com 5.45 MAC Index Register (MACINDEX) EMAC Port Registers The MAC index register (MACINDEX) is shown in Figure 73 and described in Table 73 . Figure 73. MAC Index Register (MACINDEX) 31 16 Reserved R-0 15 5 4 0 Reserved MACINDEX R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value a...
Page 136 - Network Statistics Registers; Good Receive Frames Register (RXGOODFRAMES); Figure 78. Statistics Register; Table 78. Statistics Register Field Descriptions
www.ti.com 5.50 Network Statistics Registers 5.50.1 Good Receive Frames Register (RXGOODFRAMES) 5.50.2 Broadcast Receive Frames Register (RXBCASTFRAMES) EMAC Port Registers The EMAC has a set of statistics that record events associated with frame traffic. The statistics values arecleared to zero 38 ...
Page 142 - Was any size
www.ti.com 5.50.25 Transmit Carrier Sense Errors Register (TXCARRIERSENSE) 5.50.26 Transmit Octet Frames Register (TXOCTETS) 5.50.27 Transmit and Receive 64 Octet Frames Register (FRAME64) 5.50.28 Transmit and Receive 65 to 127 Octet Frames Register (FRAME65T127) 5.50.29 Transmit and Receive 128 to ...
Page 143 - Also counted in this statistic is:
www.ti.com 5.50.30 Transmit and Receive 256 to 511 Octet Frames Register (FRAME256T511) 5.50.31 Transmit and Receive 512 to 1023 Octet Frames Register (FRAME512T1023) 5.50.32 Transmit and Receive 1024 to RXMAXLEN Octet Frames Register (FRAME1024TUP) 5.50.33 Network Octet Frames Register (NETOCTETS) ...
Page 145 - Appendix A; of a single Ethernet frame on the wire.
www.ti.com Appendix A Glossary Appendix A Broadcast MAC Address — A special Ethernet MAC address used to send data to all Ethernet devices on the local network. The broadcast address is FFh-FFh-FFh-FFh-FFh-FFh. The LSB of the firstbyte is odd, qualifying it as a group address; however, its value is ...
Page 146 - Port — Ethernet device.
www.ti.com Appendix A Jumbo Packets — Jumbo frames are defined as those packets whose length exceeds the standard Ethernet MTU, which is 1500 kbytes. For the C64x+ devices, it is recommended not to use packetsexceeding 35K in length. The PHY that you use can place additional limits on to the length ...
Page 147 - Appendix B Revision History; Appendix B
www.ti.com Appendix B Revision History Appendix B Table B-1 lists the changes made since the previous version of this document. Table B-1. Document Revision History Reference Additions/Modifications/Deletions Section 2.1 Changed Section 2.1 . Section 2.1.2 Changed Section 2.1.2 . Section 2.15.4 Chan...
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