Texas Instruments SM320C6455-EP - Manual

Texas Instruments SM320C6455-EP

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Table of Contents:

  • Page 2 – FIXED-POINT DIGITAL SIGNAL PROCESSOR; Data Manual
  • Page 3 – Features
  • Page 4 – C64x+ Peripheral Information and Electrical Specifications
  • Page 8 – Description; System PLL and PLL Controller
  • Page 10 – Functional Block Diagram; shows the functional block diagram of the C6455 device.
  • Page 11 – Device Overview; Device Characteristics; Table 2-1. Characteristics of the C6455 Processor; HARDWARE FEATURES
  • Page 13 – Other new features include:; SPLOOP; - As noted above, there are new instructions such as 32 bit; Exception Handling; free-running time-stamp counter is implemented in the CPU which is
  • Page 15 – Memory Map Summary; MEMORY BLOCK DESCRIPTION
  • Page 17 – Boot Sequence; Boot Modes Supported; Reset Controller
  • Page 19 – nd-Level Bootloaders; The SRIO boot is a software boot mode.
  • Page 20 – Pin Assignments; Pin Map; through
  • Page 24 – Signal Groups Description
  • Page 30 – Terminal Functions; The terminal functions table (
  • Page 31 – SIGNAL
  • Page 44 – RESERVED FOR TEST
  • Page 50 – GROUND PINS
  • Page 55 – Development; Development Support; Code Composer StudioTM Integrated Development Environment (IDE):
  • Page 56 – Documentation Support; TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide.
  • Page 57 – TMS320C645x DSP DDR2 Memory Controller User's Guide.
  • Page 59 – Device Configuration at Device Reset; NOTE; CONFIGURATION
  • Page 61 – Peripheral Configuration at Device Reset
  • Page 62 – describes the
  • Page 63 – Peripheral Selection After Device Reset; PERIPHERALS THAT CAN BE
  • Page 64 – Figure 3-1. Peripheral Transitions Between States
  • Page 65 – Device State Control Registers; and described in the next sections.; Table 3-5. Device State Control Registers; HEX ADDRESS RANGE
  • Page 66 – Peripheral Lock Register Description; Bit
  • Page 67 – Peripheral Configuration Register 0 Description
  • Page 69 – Peripheral Configuration Register 1 Description
  • Page 70 – Peripheral Status Registers Description
  • Page 73 – EMAC Configuration Register (EMACCFG) Description
  • Page 74 – Emulator Buffer Powerdown Register (EMUBUFPD) Description
  • Page 75 – Device Status Register Description; and
  • Page 78 – Device Configuration Pins
  • Page 81 – System Interconnect; Internal Buses, Bridges, and Switch Fabrics; Bridges perform a variety of functions:
  • Page 82 – Data Switch Fabric Connections
  • Page 83 – Figure 4-1. Switched Central Resource Block Diagram
  • Page 84 – Configuration Switch Fabric
  • Page 86 – Bus Priorities; . The priority levels should be tuned to obtain; Table 4-2. C6455 Default Bus Master Priorities; DEFAULT
  • Page 87 – Memory Architecture; shows a block diagram of the C64x+ Megamodule.
  • Page 89 – Guide
  • Page 90 – Table 5-1. Available Memory Page Protection Schemes; AID0 Bit; Reference Guide
  • Page 91 – Megamodule Resets; TMS320C64x+ Megamodule Reference Guide; Megamodule Reference Guide
  • Page 92 – Megamodule Revision; and described in
  • Page 93 – Table 5-4. Megamodule Interrupt Registers
  • Page 94 – Table 5-5. Megamodule Powerdown Control Registers
  • Page 95 – Table 5-8. Megamodule Cache Configuration Registers
  • Page 100 – Table 5-10. CPU Megamodule Bandwidth Management Registers
  • Page 101 – Device Operating Conditions; MIN
  • Page 102 – Recommended Operating Conditions (continued)
  • Page 103 – Operating Case Temperature (Unless Otherwise Noted)
  • Page 105 – Parameter Information; Tester Pin Electronics; Figure 7-1. Test Load Circuit for AC Timing Measurements; MIN for input clocks,; MAX and V; MIN for output clocks.; Figure 7-3. Rise and Fall Transition Time Voltage Reference Levels
  • Page 106 – Timing Parameters and Board Routing Analysis; The timing parameter values specified in this data sheet do; DESCRIPTION
  • Page 107 – Power-Supply Sequencing; Power-Supply Decoupling; must; UNIT
  • Page 109 – Enhanced Direct Memory Access (EDMA3) Controller; lists the device resources that can be accessed by each of the
  • Page 110 – Controller User's Guide; Table 7-3. C6455 EDMA3 Channel Synchronization Events; EDMA
  • Page 111 – Table 7-4. EDMA3 Channel Controller Registers
  • Page 118 – Table 7-6. EDMA3 Transfer Controller 0 Registers
  • Page 119 – Table 7-7. EDMA3 Transfer Controller 1 Registers
  • Page 120 – Table 7-8. EDMA3 Transfer Controller 2 Registers
  • Page 122 – Table 7-9. EDMA3 Transfer Controller 3 Registers
  • Page 124 – Interrupts; Interrupt Sources and Interrupt Controller; shows the mapping of system events. For more; EVENT NUMBER
  • Page 127 – External Interrupts Electrical Data/Timing; Table 7-11. Timing Requirements for External Interrupts
  • Page 128 – Reset Electrical Data/Timing; TYPE; The following sequence must be followed during a Power-on Reset:
  • Page 129 – all the system clocks are invalid at this point.; The following sequence must be followed during a Warm Reset:
  • Page 131 – Reset Priority; Maximum Reset
  • Page 132 – Reset Controller Register
  • Page 133 – Table 7-14. Timing Requirements for Reset; For
  • Page 135 – Figure 7-9. Warm Reset and Max Reset Timing
  • Page 136 – PLL1 and PLL1 Controller; As shown in; DSP
  • Page 137 – PLL1 Controller Device-Specific Information
  • Page 138 – There; CLOCK SIGNAL
  • Page 139 – PLL1 Controller Memory Map; The memory map of the PLL1 controller is shown in
  • Page 140 – PLL1 Controller Register Descriptions
  • Page 141 – The PLL multiplier control register (PLLM) is shown in
  • Page 143 – The PLL controller divider 4 register (PLLDIV4) is shown in
  • Page 149 – shown in
  • Page 150 – PLL1 Controller Input and Output Clock Electrical Data/Timing; Table 7-29. Timing Requirements for CLKIN1 Devices
  • Page 151 – PLL2 and PLL2 Controller
  • Page 152 – PLL2 Controller Device-Specific Information
  • Page 153 – The memory map of the PLL2 controller is shown in
  • Page 158 – Table 7-38. SYSCLK Status Register Field Descriptions
  • Page 159 – PLL2 Controller Input Clock Electrical Data/Timing; Table 7-39. Timing Requirements for CLKIN2
  • Page 160 – DDR2 Memory Controller; DDR2 Memory Controller Device-Specific Information; Implementing DDR2 PCB Layout on
  • Page 161 – Table 7-40. DDR2 Memory Controller Registers; The
  • Page 164 – Table 7-42. Timing Requirements for AECLKIN for EMIFA
  • Page 165 – Asynchronous Memory Timing; EMIFA Module; Figure 7-32. AECLKOUT Timing for the EMIFA Module
  • Page 166 – PARAMETER; Figure 7-33. Asynchronous Memory Read Timing for EMIFA
  • Page 167 – Figure 7-34. Asynchronous Memory Write Timing for EMIFA
  • Page 171 – Cycles for EMIFA Module
  • Page 172 – for EMIFA Module (see
  • Page 176 – Table 7-52. Timing Requirements for I2C Timings
  • Page 177 – Table 7-53. Switching Characteristics for I2C Timings
  • Page 193 – Multichannel Buffered Serial Port (McBSP) Timing; Table 7-59. Timing Requirements for McBSP
  • Page 201 – Interface Modes
  • Page 202 – Using the RMII Mode of the EMAC
  • Page 203 – Interface Mode Clocking
  • Page 207 – Table 7-73. EMAC Control Module Registers
  • Page 208 – EMAC MII and GMII Electrical Data/Timing
  • Page 215 – Transmit
  • Page 219 – Table 7-94. Timing Requirements for Timer Inputs
  • Page 223 – Section 4; Table 7-98. Default Values for PCI Configuration
  • Page 225 – Table 7-100. PCI Back End Configuration Registers; DSP ACCESS
  • Page 227 – Table 7-102. PCI Hook Configuration Registers
  • Page 230 – For more detailed information on the UTOPIA peripheral, see the
  • Page 231 – Table 7-106. Timing Requirements for UXCLK; Table 7-107. Timing Requirements for URCLK
  • Page 232 – Table 7-108. Timing Requirements for UTOPIA Slave Transmit (see
  • Page 233 – Table 7-110. Timing Requirements for UTOPIA Slave Receive (see
  • Page 247 – Table 7-114. Timing Requirements for GPIO Inputs
  • Page 248 – Emulation Features and Capability; Hardware Program Breakpoints:
  • Page 250 – Revision History; have been incorporated.; SEE
  • Page 251 – Mechanical Data; Thermal Data; AIR FLOW
  • Page 252 – PACKAGING INFORMATION; PACKAGE OPTION ADDENDUM
  • Page 254 – IMPORTANT NOTICE; Products
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SM320C6455-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR

Data Manual

JANUARY 2008

SPRS462B

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Summary

Page 2 - FIXED-POINT DIGITAL SIGNAL PROCESSOR; Data Manual

SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR Data Manual Literature Number: SPRS462B SEPTEMBER 2007 – Revised JANUARY 2008 PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of the TexasInstruments standard warranty. Production proces...

Page 3 - Features

Contents SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 1 Features .............................................................................................................................. 7 1.1 ZTZ/GTZ BGA Package (Bottom View) ................

Page 4 - C64x+ Peripheral Information and Electrical Specifications

SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 6.2 Recommended Operating Conditions .................................................................................. 101 6.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and ...

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