Page 5 - Preface; Read This First; About This Manual; Designing with the TL5001C PWM Controller Application Report
Related Documentation From Texas Instruments iii Read This First Preface Read This First About This Manual This user’s guide is a reference manual for the SLVP089 Synchronous BuckConverter Evaluation Module used to evaluate the performance of the TL5001PWM Controller. This document provides informat...
Page 6 - FCC Warning; TI is a trademark of Texas Instruments Incorporated.
If You Need Assistance iv If You Need Assistance . . . If you want to . . . Contact Texas Instruments at . . . Visit TI online World Wide Web: http://www.ti.com Request more information World Wide Web: http://www.ti.com/sc/docs/pic/home.htm about Texas InstrumentsMixed Signal Products(MSP) Call the ...
Page 7 - Contents; Hardware
Running Title—Attribute Reference v Chapter Title—Attribute Reference Contents 1 Hardware 1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Introduction 1-2 . . . . . . . . . . . . . . . . . . . . . ....
Page 8 - Figures
Running Title—Attribute Reference vi Figures 1–1 Typical Synchronous Buck Converter 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Schematic Diagram 1-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 9 - Topic; Chapter 1
1-1 Chapter Title—Attribute Reference Hardware The SLVP089 Synchronous Buck Converter Evaluation Module (SLVP089)provides a method for evaluating the performance of the TL5001 pulse-width-modulation (PWM) controller. The device contains all of the circuitry necessaryto control a switch-mode power su...
Page 10 - Introduction; Figure 1–1. Typical Synchronous Buck Converter
Introduction 1-2 1.1 Introduction Synchronous buck converters provide the smaller size and higher efficiencyrequired by electronic equipment, particularly portable battery-operatedequipment. The synchronous buck converter reduces power lossesassociated with a standard buck converter by substituting ...
Page 11 - Schematic; Figure 1–2. Schematic Diagram
Schematic 1-3 Hardware 1.2 Schematic Figure 1–2. Schematic Diagram DTC COMP R9 RT OUT SCP GND V CC 6 3 4 7 R9 1 5 FB + C1 µ 1 F R2 C30.0022 µ F C2 0.033 µ F R8 C9 0.22 µ F C15 µ 1.0 F R6 2 8 U1 TL5001 1IN 2OUT GND V CC 2 4 5 7 2IN 3 1OUT V DD REG 8 6 1 R10 R13 IRF7201 NMOS Q2 U2TPS2812 C14 0.1 µ F C...
Page 12 - Input/Output Connections; Figure 1–3 shows the input/output connections to the SLVP089.
Input/Output Connections 1-4 1.3 Input/Output Connections Figure 1–3 shows the input/output connections to the SLVP089. Figure 1–3. Input/Output Connections C5 Q1 Q2 TL5001 +3.3V, 3 AMP SYNC. RECT BUCK U2 R5 R7 R13 C6 C11 C10 L1 J1 J2 R12 CR3 CR2 R11 C14 R6 R10 JMP1 C12 C8 C13 TEXAS INSTRUMENTS C15 ...
Page 13 - Board Layout; Figure 1–4 shows the SLVP089 board layout.; Figure 1–4. Board Layout
Board Layout 1-5 Hardware 1.4 Board Layout Figure 1–4 shows the SLVP089 board layout. Figure 1–4. Board Layout C5 Q1 Q2 TL5001 +3.3V, 3 AMP SYNC. RECT BUCK U2 R5 R7 R13 C6 C11 C10 L1 J1 J2 R12 CR3 CR2 R11 C14 R6 R10 JMP1 C12 C8 C13 TEXAS INSTRUMENTS C15 R4 R3 C4 C3 R1 R9 R8 C9 C1 SLVP089EVAL BOARDRE...
Page 14 - Bill of Materials; Table 1–1 lists materials required for the SLVP089.; Table 1–1. Bill of Materials
Bill of Materials 1-6 1.5 Bill of Materials Table 1–1 lists materials required for the SLVP089. Table 1–1. Bill of Materials Qty Reference Part Number Mfr Description 1 C1 ECS-T1CY105R Panasonic Capacitor, Tant, 1 m F, 20%, A Case 1 C11 Standard Capacitor, Cer, 0.47 m F, 10%, X7R, 1210 1 C13 C3225Y5...
Page 15 - Test Results; Figure 1–5. Efficiency Vs Load
Test Results 1-7 Hardware 1.6 Test Results Tables 1–2 and 1–3, along with Figures 1–5 through 1–8, show the test resultsfor the SLVP089. Table 1–2. Line/Load Regulation, 3.3-V (Total Variation) Line/Load 0.3 A 0.9 A 1.5 A 3.0 A 5.0 A Load Reg. 5.5 V Vo(V) 3.330 3.329 3.328 3.324 3.320 0.18% 6.0 V Vo...
Page 16 - Figure 1–6. Power Switch Turn-On and Delay from Q2 Off
Test Results 1-8 Figure 1–6. Power Switch Turn-On and Delay from Q2 Off VCC = 12 VIO = 1.5 A Q1 DRAIN5 V/DIV Q2 GATE5 V/DIV 20 ns/Div 1 2 Figure 1–7. Power Switch Turn-Off and Delay to Q2 On VCC = 12 VIO = 1.5 A Q1 Drain 5 V/Div Q2 Gate 5 V/Div 1 2 20 ns/Div
Page 17 - Figure 1–8. Inductor and Output Ripple
Test Results 1-9 Hardware Figure 1–8. Inductor and Output Ripple VCC = 12 VIO = 1.5 A InductorRipple1 A/Div OutputRipple20 mV/Div 2 µ s/Div 1–DC 2–AC
Page 19 - Design Procedure; Chapter 2
2-1 Chapter Title—Attribute Reference Design Procedure There are many possible ways to proceed when designing power supplies.This chapter shows the procedure used in the design of the SLVP089. Thechapter includes the following topics: Topic Page 2.1 Introduction 2-2 . . . . . . . . . . . . . . . . ....
Page 21 - Operating Specifications; Table 2–1 lists the operating specifications for the SLVP089.; Table 2–1. Operating Specifications
Operating Specifications 2-3 Design Procedure 2.2 Operating Specifications Table 2–1 lists the operating specifications for the SLVP089. Table 2–1. Operating Specifications Specification Min Typ Max Units Input Voltage Range 5.5 12 V Output Voltage Range 3.10 3.30 3.50 V Output Current Range 0 3 A O...
Page 22 - Design Procedures; Duty Cycle Estimate; Output Filter; The inductor value is:; ESR; Power Switch; Based on the preliminary estimate, r
Design Procedures 2-4 2.3 Design Procedures Detailed steps in the design of a buck-mode converter may be found inDesigning With the TL5001C PWM Controller (literature number SLVA034)from TI. This section shows the basic steps involved in this design. 2.3.1 Duty Cycle Estimate The duty cycle for a co...
Page 23 - Assuming total switching time, t; Synchronous Switch and Rectifier; should be less than 0.012 V; Snubber Network
Design Procedures 2-5 Design Procedure The power dissipation (conduction + switching losses) can be approximatedas: P D + ǒ I 2O r DS(ON) D Ǔ ) ǒ 0.5 V I I O t r ) f f Ǔ Assuming total switching time, t r+f , = 100 ns, a 55 ° C maximum ambient tem- perature, and r DS(ON) adjustment factor = 1.6, the...
Page 24 - Controller Functions; W å; Loop Compensation; resistor for the bottom of the divider gives a divid-
Design Procedures 2-6 2.3.6 Controller Functions The controller functions, oscillator frequency, soft-start, dead-time-control,short-circuit protection, and sense-divider-network are discussed in this sec-tion. The oscillator frequency is set by selecting the resistance value from the graphin figure...
Page 25 - LC; Figure 2–1. Power Stage Bode Plot
Design Procedures 2-7 Design Procedure Calculating the pulse-width-modulator gain as the change in output voltagedivided by the change in PWM input voltage gives: A PWM + D V O D V COMP + 9 – 0 1.3 – 0.65 + 13.85 å 22.8 db The LC filter has a double pole at: 1 2 p LC Ǹ + 1 2 p 21.6 m H 168 m F Ǹ + 2...
Page 26 - Figure 2–2. Compensation Network; Ǔǒ
Design Procedures 2-8 Figure 2–2. Compensation Network _ + C4 R3 R4 C3 C2 R2 V ref V O V I The transfer function for this circuit is: V O V I + [1 ) sR2(C2 ) C3)] [1 ) sC4(R3 ) R4)] sC2R4 [1 ) sC3R2] [1 ) sC4R3] + ǒ f Z1 Ǔǒ f Z2 Ǔ ǒ f P1 Ǔǒ f P2 Ǔ ǒ f P3 Ǔ The desired output regulation is ± 6 percen...
Page 27 - Figure 2–3 shows the bode plot for the compensation network.; Figure 2–3. Bode Plot; Figure 2–4. Output Response
Design Procedures 2-9 Design Procedure Figure 2–3 shows the bode plot for the compensation network. Figure 2–3. Bode Plot 25 20 10 0 Gain – dB (Solid) 30 40 Frequency – Hz 45 35 15 90 70 50 30 10 –10 –30 –50 –90 Phase – Degrees (Dashed) 10 102 103 104 105 5 –70 Note from the output response shown in...
