Texas Instruments SM320F2812-HT - Manual

Texas Instruments SM320F2812-HT

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Table of Contents:

  • Page 2 – Features
  • Page 4 – Mechanical Data
  • Page 9 – Minimum Required Wait-States at Different Frequencies
  • Page 11 – Digital Signal Processor; xxx
  • Page 12 – SUPPORTS EXTREME TEMPERATURE APPLICATIONS
  • Page 13 – Introduction; Description
  • Page 14 – Device Summary; provides a summary of the device features.; FEATURE
  • Page 15 – Die Layout; for a description of each pad's
  • Page 16 – Pin Assignments; See
  • Page 17 – Signal Descriptions
  • Page 26 – NOTE
  • Page 28 – Memory Map
  • Page 29 – Table 3-1. Addresses of Flash Sectors in F2812; ADDRESS RANGE
  • Page 30 – I/O space is not supported on the F2812 XINTF.; AREA
  • Page 31 – Brief Descriptions; Data Writes; Peripheral Bus
  • Page 32 – Flash; Boot ROM; shows the
  • Page 33 – BOOT MODE SELECTED; Security
  • Page 36 – Register Map
  • Page 39 – Device Emulation Registers; NAME; External Interface, XINTF; shows the F2812 XINTF signals.
  • Page 40 – Figure 3-3. External Interface Block Diagram
  • Page 41 – Table 3-8. XINTF Configuration and Control Register Mappings; Timing Registers; Table 3-9. XREVISION Register Bit Definitions
  • Page 42 – MUX; Interrupts
  • Page 43 – Figure 3-5. Multiplexing of Interrupts Using the PIE Block; PIE INTERRUPTS
  • Page 44 – Table 3-11. PIE Configuration and Control Registers
  • Page 45 – External Interrupts; Table 3-12. External Interrupts Registers
  • Page 46 – See Note A; System Control
  • Page 48 – OSC and PLL Block; shows the OSC and PLL block on the F2812.; Table 3-14. PLLCR Register Bit Definitions
  • Page 49 – External Clock Signal; Crystal; Loss of Input Clock; PLL-Based Clock Module; The PLL-based clock module provides two modes of operation:; Table 3-15. Possible PLL Configuration Modes; PLL MODE; External Reference Oscillator Clock Option; Fundamental mode, parallel resonant
  • Page 50 – shows the various functional blocks within the watchdog module.
  • Page 51 – MODE; The various low-power modes operate as follows:
  • Page 52 – Enhanced controller area network (eCAN) module
  • Page 55 – Table 4-2. Module and Signal Names for EVA and EVB
  • Page 58 – Programmable Deadband Generator
  • Page 60 – The digital value of the input analog voltage is derived by:
  • Page 61 – Figure 4-4. Block Diagram of the F2812 ADC Module; shows the ADC pin connections for the; signals is as follows:
  • Page 62 – shows the ADC pin-biasing for internal reference and
  • Page 63 – Figure 4-6. ADC Pin Connections With External Reference
  • Page 65 – Enhanced Controller Area Network (eCAN) Module
  • Page 66 – Figure 4-7. eCAN Block Diagram and Interface Circuit
  • Page 68 – REGISTER NAME
  • Page 69 – Multichannel Buffered Serial Port (McBSP) Module
  • Page 71 – provides a summary of the McBSP registers.
  • Page 73 – Serial Communications Interface (SCI) Module; Both pins can be used as GPIO if not used for SCI.
  • Page 74 – Auto baud-detect hardware logic
  • Page 75 – shows the SCI module block diagram.
  • Page 76 – All four pins can be used as GPIO, if the SPI module is not used.
  • Page 77 – Delayed transmit control
  • Page 78 – is a block diagram of the SPI in slave mode.
  • Page 79 – GPIO MUX; lists the GPIO Mux Registers.; lists the GPIO Data Registers. For more information, see the
  • Page 82 – Software Development Tools; Device and Development Support Tool Nomenclature; TMS/SM—Fully qualified production device
  • Page 83 – Documentation Support
  • Page 85 – Absolute Maximum Ratings; VALUE
  • Page 86 – Recommended Operating Conditions; Electrical Characteristics; Over recommended operating conditions (unless otherwise noted)
  • Page 87 – Hour
  • Page 88 – HALT and STANDBY modes cannot be used when the PLL is disabled.
  • Page 89 – Current Consumption Graphs; Figure 6-2. Typical Current Consumption Over Frequency
  • Page 90 – Reducing Current Consumption; the clocks to various peripherals.; PERIPHERAL MODULE; Power Sequencing Requirements; and V
  • Page 91 – The GPIO pins are undefined until V; Signal Transition Levels
  • Page 92 – Timing Parameter Symbology
  • Page 93 – Transmission Line; Tester Pin Electronics; Data Sheet Timing Reference Point; General Notes on Timing Parameters
  • Page 94 – Device Clock Table; lists the cycle times of various clocks.; Clock Requirements and Characteristics
  • Page 96 – MIN
  • Page 100 – is also the IDLE Mode Wake-Up Timing Requirements table.; Table 6-10. IDLE Mode Switching Characteristics
  • Page 101 – is also the STANDBY Mode Wake-Up Timing Requirements table.; Table 6-11. STANDBY Mode Switching Characteristics
  • Page 102 – Figure 6-14. STANDBY Entry and Exit Timing
  • Page 103 – Table 6-12. HALT Mode Switching Characteristics; PARAMETER
  • Page 104 – Event Manager Interface; PWM refers to all PWM outputs on EVA and EVB.
  • Page 105 – Table 6-13. PWM Switching Characteristics
  • Page 106 – Table 6-17. Interrupt Switching Characteristics
  • Page 107 – Table 6-18. Interrupt Timing Requirements
  • Page 108 – Figure 6-22. GPIO Input Qualifier – Example Diagram for QUALPRD = 1
  • Page 109 – SPI Master Mode Timing
  • Page 113 – SPI Slave Mode Timing
  • Page 117 – Table 6-26. XTIMING Register Configuration Restrictions
  • Page 118 – LR; Restriction does not include external hardware wait states
  • Page 119 – or; Table 6-31. XTIMING Register Configuration Restrictions
  • Page 120 – The relationship between SYSCLKOUT and XTIMCLK is shown in; Figure 6-28. Relationship Between XTIMCLK and SYSCLKOUT
  • Page 121 – XINTF Signal Alignment to XCLKOUT
  • Page 122 – External Interface Read Timing; Table 6-35. External Memory Interface Read Timing Requirements
  • Page 123 – XTIMING register parameters used for this example:; External Interface Write Timing
  • Page 126 – Figure 6-31. Example Read With Synchronous XREADY Access
  • Page 127 – Figure 6-32. Example Read With Asynchronous XREADY Access
  • Page 129 – Figure 6-33. Write With Synchronous XREADY Access
  • Page 130 – Figure 6-34. Write With Asynchronous XREADY Access
  • Page 131 – XHOLD and XHOLDA
  • Page 132 – Figure 6-35. External Interface Hold Waveform
  • Page 137 – Figure 6-37. ADC Analog Input Impedance Model
  • Page 139 – Table 6-50. Sequential Sampling Mode Timing; SAMPLE n
  • Page 141 – Table 6-51. Simultaneous Sampling Mode Timing; Definitions of Specifications and Terminology
  • Page 143 – Table 6-53. McBSP Switching Characteristics
  • Page 145 – McBSP as SPI Master or Slave Timing
  • Page 149 – Table 6-64. Minimum Required Wait-States at Different Frequencies
  • Page 150 – RANDOM WAIT STATE
  • Page 152 – PACKAGE OPTION ADDENDUM; PACKAGING INFORMATION
  • Page 154 – IMPORTANT NOTICE; Products
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SM320F2812-HT

Digital Signal Processor

Data Manual

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Literature Number: SGUS062A

June 2009 – Revised April 2010

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Summary

Page 2 - Features

SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Contents 1 Features ........................................................................................................................... 11 1.1 SUPPORTS EXTREME TEMPERATURE APPLICATIONS ...........................................

Page 4 - Mechanical Data

SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 6.20 SPI Slave Mode Timing ................................................................................................. 113 6.21 External Interface (XINTF) Timing ....................................................................

Page 9 - Minimum Required Wait-States at Different Frequencies

SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 6-64 Minimum Required Wait-States at Different Frequencies ................................................................ 149 Copyright © 2009–2010, Texas Instruments Incorporated List of Tables 9

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