Intel 8XC196MD - Manual

vii CONTENTS 7.4.5 Determining Serial Port Status ................................................................................ 7-15 CHAPTER 8 FREQUENCY GENERATOR 8.1 FUNCTIONAL OVERVIEW............................................................................................ 8-1 8.2 PROGRAMMIN...

8XC196MC, MD, MH USER’S MANUAL viii 10.5.2 Reading the Current Value of the Down-counter .................................................... 10-7 10.5.3 Enabling the PWM Outputs ..................................................................................... 10-8 10.5.4 Generating Analog Outpu...

ix CONTENTS 12.6.1.4 Using Mixed Analog and Digital Inputs ............................................................12-13 12.6.2 Understanding A/D Conversion Errors ..................................................................12-13 CHAPTER 13 MINIMUM HARDWARE CONSIDERATIONS 13.1 MINIMUM CONN...

8XC196MC, MD, MH USER’S MANUAL x 15.4 WAIT STATES (READY CONTROL)......................................................................... 15-17 15.5 BUS-CONTROL MODES........................................................................................... 15-21 15.5.1 Standard Bus-control Mode .....

xi CONTENTS APPENDIX A INSTRUCTION SET REFERENCE APPENDIX B SIGNAL DESCRIPTIONS B.1 SIGNAL NAME CHANGES........................................................................................... B-1 B.2 FUNCTIONAL GROUPINGS OF SIGNALS ....................................................................

8XC196MC, MD, MH USER’S MANUAL xii FIGURES Figure Page 2-1 8XC196M x Block Diagram ........................................................................................... 2-3 2-2 Block Diagram of the Core ..............................................................................................

xiii CONTENTS FIGURES Figure Page 7-5 Serial Port Frames in Mode 2 and 3 ............................................................................. 7-9 7-6 Serial Port Control (SP x _CON) Register .................................................................... 7-10 7-7 Serial Port x Baud Rat...

8XC196MC, MD, MH USER’S MANUAL xiv FIGURES Figure Page 12-3 A/D Result (AD_RESULT) Register — Write Format ................................................. 12-6 12-4 A/D Time (AD_TIME) Register ................................................................................... 12-7 12-5 A/D Command...

xv CONTENTS FIGURES Figure Page 15-21 16-bit System with RAM ...........................................................................................15-31 15-22 System Bus Timing ..................................................................................................15-32 16-1 Unerasabl...

8XC196MC, MD, MH USER’S MANUAL xvi TABLES Table Page 1-1 Handbooks and Product Information ............................................................................ 1-6 1-2 Application Notes, Application Briefs, and Article Reprints .......................................... 1-6 1-3 MCS ® 96 Micr...

xvii CONTENTS TABLES Table Page 6-8 Control Register Values for Each Configuration ......................................................... 6-11 6-9 Port Configuration Example ....................................................................................... 6-11 6-10 Port Pin States After Res...

8XC196MC, MD, MH USER’S MANUAL xviii TABLES Table Page 16-1 87C196M x OTPROM Memory Map .......................................................................... 16-3 16-2 Memory Protection for Normal Operating Mode ......................................................... 16-4 16-3 Memory Protecti...

1-1 CHAPTER 1 GUIDE TO THIS MANUAL This manual describes the 8XC196MC, 8XC196MD, and 8XC196MH embedded microcontrol-lers. It is intended for use by both software and hardware designers familiar with the principlesof microcontrollers. This chapter describes what you’ll find in this manual, lists othe...

1-3 GUIDE TO THIS MANUAL Appendix C — Registers — provides a compilation of all device special-function registers(SFRs) arranged alphabetically by register mnemonic. It also includes tables that list the win-dowed direct addresses for all SFRs in each possible window. Glossary — defines terms with s...

1-5 GUIDE TO THIS MANUAL units of measure The following abbreviations are used to represent units of measure: A amps, amperes DCV direct current volts Kbytes kilobytes kHz kilohertz k Ω kilo-ohms mA milliamps, milliamperes Mbytes megabytes MHz megahertz ms milliseconds mW milliwatts ns nanoseconds p...

8XC196MC, MD, MH USER’S MANUAL 1-6 Table 1-1. Handbooks and Product Information Title and Description Order Number Intel Embedded Quick Reference Guide 272439 Solutions for Embedded Applications Guide 240691 Data on Demand fact sheet 240952 Data on Demand annual subscription (6 issues; Windows* vers...

8XC196MC, MD, MH USER’S MANUAL 1-8 This Page Left Intentionally Blank

1-11 GUIDE TO THIS MANUAL 1.4.4 World Wide Web We offer a variety of information through the World Wide Web (URL:http://www.intel.com/). Se-lect “Embedded Design Products” from the Intel home page. 1.5 TECHNICAL SUPPORT In the U.S. and Canada, technical support representatives are available to answe...

2-1 CHAPTER 2 ARCHITECTURAL OVERVIEW The 16-bit 8XC196MC, 8XC196MD, and 8XC196MH CHMOS microcontrollers are designedto handle high-speed calculations and fast input/output (I/O) operations. They share a commonarchitecture and instruction set with other members of the MCS ® 96 microcontroller family....

8XC196MC, MD, MH USER’S MANUAL 2-2 2.3 FUNCTIONAL OVERVIEW Figure 2-1 shows the major blocks within the microcontroller. The core of the microcontroller(Figure 2-2) consists of the central processing unit (CPU) and memory controller. The CPU con-tains the register file and the register arithmetic-lo...

8XC196MC, MD, MH USER’S MANUAL 2-6 2.3.4 Memory Interface Unit The RALU communicates with all memory, except the register file and peripheral SFRs, throughthe memory controller. (It communicates with the upper register file through the memory control-ler except when windowing is used; see Chapter 4,...

2-7 ARCHITECTURAL OVERVIEW 2.4 INTERNAL TIMING The clock circuitry (Figure 2-3) receives an input clock signal on XTAL1 provided by an externalcrystal or oscillator and divides the frequency by two. The clock generators accept the dividedinput frequency from the divide-by-two circuit and produce two...

8XC196MC, MD, MH USER’S MANUAL 2-8 Figure 2-4. Internal Clock Phases The combined period of phase 1 and phase 2 of the internal CLKOUT signal defines the basictime unit known as a state time or state. Table 2-2 lists state time durations at various frequencies. The following formulas calculate the f...

2-11 ARCHITECTURAL OVERVIEW 2.5.7 Analog-to-digital Converter The analog-to-digital (A/D) converter converts an analog input voltage to a digital equivalent.Resolution is either 8 or 10 bits; sample and convert times are programmable. Conversions canbe performed on the analog ground and reference vo...

8XC196MC, MD, MH USER’S MANUAL 2-12 2.6.3 Programming the Nonvolatile Memory MCS 96 microcontrollers that have internal OTPROM provide several programming options: • Slave programming allows a master EPROM programmer to program and verify one ormore slave MCS 96 microcontrollers. Programming vendors...

3-1 CHAPTER 3 PROGRAMMING CONSIDERATIONS This section provides an overview of the instruction set of the MCS ® 96 microcontrollers and of- fers guidelines for program development. For detailed information about specific instructions,see Appendix A. 3.1 OVERVIEW OF THE INSTRUCTION SET The instruction...

8XC196MC, MD, MH USER’S MANUAL 3-2 Table 3-2 lists the equivalent operand-type names for both C programming and assembly lan-guage. 3.1.1 BIT Operands A BIT is a single-bit variable that can have the Boolean values, “true” and “false.” The architec-ture requires that BITs be addressed as components ...

3-3 PROGRAMMING CONSIDERATIONS WORDs must be aligned at even byte boundaries in the address space. The least-significant byteof the WORD is in the even byte address, and the most-significant byte is in the next higher (odd)address. The address of a WORD is that of its least-significant byte (the eve...

3-5 PROGRAMMING CONSIDERATIONS 3.2 ADDRESSING MODES The instruction set uses four basic addressing modes: • direct • immediate • indirect (with or without autoincrement) • indexed (short-, long-, or zero-indexed) The stack pointer can be used with indirect addressing to access the top of the stack, ...

8XC196MC, MD, MH USER’S MANUAL 3-6 3.2.1 Direct Addressing Direct addressing directly accesses a location in the 256-byte lower register file, without involv-ing the memory controller. Windowing allows you to remap other sections of memory into thelower register file for direct access (see Chapter 4...

3-7 PROGRAMMING CONSIDERATIONS ADDB AL,BL,[CX] ; AL ← BL + MEM_BYTE(CX) POP [AX] ; MEM_WORD(AX) ← MEM_WORD(SP) ; SP ← SP + 2 3.2.3.1 Indirect Addressing with Autoincrement You can choose to automatically increment the indirect address after the current access. You spec-ify autoincrementing by adding...

8XC196MC, MD, MH USER’S MANUAL 3-8 The instruction LD AX,12H[BX] loads AX with the contents of the memory location that residesat address BX+12H. That is, the instruction adds the constant 12H (the offset) to the contents ofBX (the base address), then loads AX with the contents of the resulting addr...

3-9 PROGRAMMING CONSIDERATIONS 3.3 ASSEMBLY LANGUAGE ADDRESSING MODE SELECTIONS The assembly language simplifies the choice of addressing modes. Use these features whereverpossible. 3.3.1 Direct Addressing The assembly language chooses between direct and zero-indexed addressing depending on thememor...

8XC196MC, MD, MH USER’S MANUAL 3-10 To use these registers effectively, you must have some overall strategy for allocating them. TheC programming language adopts a simple, effective strategy. It allocates the eight bytes beginningat address 1CH as temporary storage and treats the remaining area in t...

3-11 PROGRAMMING CONSIDERATIONS If a procedure returns a value to the calling code (as opposed to modifying more global variables),the result is returned in the temporary storage space (TMPREG0, in this example) starting at 1CH.TMPREG0 is viewed as either an 8-, 16-, or 32bit variable, depending on ...

4-1 CHAPTER 4 MEMORY PARTITIONS This chapter describes the address space, its major partitions, and a windowing technique for ac-cessing the upper register file and peripheral SFRs with register-direct instructions. 4.1 MEMORY PARTITIONS Table 4-1 is a memory map of the 8XC196Mx devices. The remaind...

8XC196MC, MD, MH USER’S MANUAL 4-2 4.1.3 Program Memory Program memory occupies a memory partition beginning at 2080H. (See Table 4-1 for the endingaddress for each device.) This entire partition is available for storing executable code and data.The EA# signal controls access to program memory. Acce...

4-3 MEMORY PARTITIONS 4.1.4 Special-purpose Memory Special-purpose memory resides in locations 2000–207FH (Table 4-2). It contains several re-served memory locations, the chip configuration bytes (CCBs), and vectors for both peripheraltransaction server (PTS) and standard interrupts. Accesses to thi...

8XC196MC, MD, MH USER’S MANUAL 4-6 Table 4-4. Peripheral SFRs — 8XC196MC Port 2 SFRs EPA and Timer SFRs Address High (Odd) Byte Low (Even) Byte Address High (Odd) Byte Low (Even) Byte 1FDEH Reserved Reserved † 1F7EH TIMER2 (H) TIMER2 (L) • • • • • • • • • 1F7CH Reserved T2CONTROL 1FD6H Reserved P2_P...

4-7 MEMORY PARTITIONS Table 4-5. Peripheral SFRs — 8XC196MD Ports 2 and 7 SFRs EPA and Timer SFRs Address High (Odd) Byte Low (Even) Byte Address High (Odd) Byte Low (Even) Byte 1FDEH Reserved Reserved † 1F7EH TIMER2 (H) TIMER2 (L) 1FDCH Reserved Reserved 1F7CH Reserved T2CONTROL 1FDAH Reserved Rese...

4-9 MEMORY PARTITIONS 4.1.6 Register File The register file (Figure 4-1) is divided into an upper register file and a lower register file. Theupper register file consists of general-purpose register RAM. The lower register file contains gen-eral-purpose register RAM along with the stack pointer (SP)...

8XC196MC, MD, MH USER’S MANUAL 4-10 4.1.6.1 General-purpose Register RAM The lower register file contains general-purpose register RAM. The stack pointer locations canalso be used as general-purpose register RAM when stack operations are not being performed.The RALU can access this memory directly, ...

8XC196MC, MD, MH USER’S MANUAL 4-12 4.2 WINDOWING Windowing expands the amount of memory that is accessible with register-direct addressing.Register-direct addressing can access the lower register file with short, fast-executing instruc-tions. With windowing, register-direct addressing can also acce...

4-13 MEMORY PARTITIONS 4.2.1 Selecting a Window The window selection register (Figure 4-3) selects a window to be mapped into the top of the low-er register file. Table 4-9 provides a quick reference of WSR values for windowing the peripheral SFRs. Table4-10 on page 4-14 lists the WSR values for win...

8XC196MC, MD, MH USER’S MANUAL 4-14 4.2.2 Addressing a Location Through a Window After you have selected the desired window, you need to know the windowed direct address ofthe memory location (the address in the lower register file). Calculate the windowed direct ad-dress as follows: 1. Subtract the...

8XC196MC, MD, MH USER’S MANUAL 4-18 ldb wsr, #?WSR ;Prolog code for wsr add var1, var2, var3 ; ; ; ldb wsr, [sp] ;Epilog code for wsr add sp, #2 ;Epilog code for wsr retend****************************** The following is an example of a linker invocation to link and locate the modules and to deter-mi...

4-19 MEMORY PARTITIONS The C compiler can also take advantage of this feature if the “windows” switch is enabled. Fordetails, see the MCS 96 microcontroller architecture software products in the Development ToolsHandbook. 4.2.3 Windowing and Addressing Modes Once windowing is enabled, the windowed l...

5-1 CHAPTER 5 STANDARD AND PTS INTERRUPTS This chapter describes the interrupt control circuitry, priority scheme, and timing for standard andperipheral transaction server (PTS) interrupts. It discusses the three special interrupts and the sev-en PTS modes, four of which are used with the EPA to pro...

8XC196MC, MD, MH USER’S MANUAL 5-2 Figure 5-1. Flow Diagram for PTS and Standard Interrupts No No PTS Enabled? PTSSEL. x Bit = 1? Yes Yes No Interrupt Pending or PTSSRV Bit Set NMI Pending ? Interrupts Enabled ? Yes No Return INT_MASK. x = 1? No Return Yes Return Reset INT_PEND. x Bit Reset PTSSRV. ...

5-3 STANDARD AND PTS INTERRUPTS Figure 5-1 illustrates the interrupt processing flow. In this flow diagram, “INT_MASK” repre-sents both the INT_MASK and INT_MASK1 registers, and “INT_PEND” represents both theINT_PEND and INT_PEND1 registers. 5.2 INTERRUPT SIGNALS AND REGISTERS Table 5-1 describes th...

8XC196MC, MD, MH USER’S MANUAL 5-4 5.3 INTERRUPT SOURCES AND PRIORITIES Table 5-3 lists the interrupts sources, their default priorities (30 is highest and 0 is lowest), andtheir vector addresses. The unimplemented opcode and software trap interrupts are not priori-tized; they go directly to the int...

5-5 STANDARD AND PTS INTERRUPTS Table 5-3. Interrupt Sources, Vectors, and Priorities Interrupt Source Mnemonic Interrupt Controller Service PTS Service Na m e Ve c to r Pri o rity Na m e Ve c to r Pri o rity Nonmaskable Interrupt NMI INT15 203EH 30 — — — EXTINT Pin EXTINT INT14 203CH 14 PTS14 205CH...

8XC196MC, MD, MH USER’S MANUAL 5-6 5.3.1 Special Interrupts This microcontroller has three special interrupt sources that are always enabled: unimplementedopcode, software trap, and NMI. These interrupts are not affected by the EI (enable interrupts)and DI (disable interrupts) instructions, and they...

5-7 STANDARD AND PTS INTERRUPTS When the level-sensitive event is selected, the external interrupt signal must remain asserted forat least 24 T XTAL 1 (24/F XTAL 1 ) to be recognized as a valid interrupt. When the signal is asserted, the level sampler samples the level of the signal three times duri...

8XC196MC, MD, MH USER’S MANUAL 5-8 The interrupt service routine should read the PI_PEND (Figure 5-12 on page 5-23) register to de-termine the source of the interrupt. Before executing the return instruction, the interrupt serviceroutine should check to see if any of the other interrupt sources are ...

5-9 STANDARD AND PTS INTERRUPTS 5.3.4 End-of-PTS Interrupts When the PTSCOUNT register decrements to zero at the end of a single transfer, block transfer,A/D scan, or serial I/O routine, hardware clears the corresponding bit in the PTSSEL register,(Figure 5-6 on page 5-14) which disables PTS service...

8XC196MC, MD, MH USER’S MANUAL 5-10 Each PTS cycle within a PTS routine cannot be interrupted. A PTS cycle is the entire PTS re-sponse to a single interrupt request. In block transfer mode, a PTS cycle consists of the transferof an entire block of bytes or words. This means a worst-case latency of 5...

8XC196MC, MD, MH USER’S MANUAL 5-12 5.5 PROGRAMMING THE INTERRUPTS The PTS select register (PTSSEL) selects either PTS service or a standard software interrupt ser-vice routine for each of the maskable interrupt requests (see Figure 5-6). The bits in the interruptmask registers, INT_MASK and INT_MAS...

5-17 STANDARD AND PTS INTERRUPTS PI_MASK Address: Reset State: 1FBCH AAH The peripheral interrupt mask (PI_MASK) register enables or disables (masks) interrupt requests associated with the peripheral interrupt (PI), the serial port interrupt (SPI), and the overflow/underflow timer interrupt (OVRTM)....

8XC196MC, MD, MH USER’S MANUAL 5-18 5.5.1 Modifying Interrupt Priorities Your software can modify the default priorities of maskable interrupts by controlling the interruptmask registers (INT_MASK and INT_MASK1). For example, you can specify which interrupts,if any, can interrupt an interrupt servic...

8XC196MC, MD, MH USER’S MANUAL 5-20 5.5.2 Determining the Source of an Interrupt When hardware detects an interrupt, it sets the corresponding bit in the INT_PEND orINT_PEND1 register (Figures 5-10 and 5-11 ). It sets the bit even if the individual interrupt isdisabled (masked). Hardware clears the ...

8XC196MC, MD, MH USER’S MANUAL 5-24 5.6 INITIALIZING THE PTS CONTROL BLOCKS Each PTS interrupt requires a block of data, in register RAM, called the PTS control block(PTSCB). The PTSCB identifies which PTS microcode routine will be invoked and sets up thespecific parameters for the routine. You must...

5-25 STANDARD AND PTS INTERRUPTS The address of the first (lowest) PTSCB byte is stored in the PTS vector table in special-purposememory (see “Special-purpose Memory” on page 4-3). Figure 5-13 shows the PTSCB for eachPTS mode. Unused PTSCB bytes can be used as extra RAM. NOTE The PTSCB must be locat...

5-27 STANDARD AND PTS INTERRUPTS 5.6.2 Selecting the PTS Mode The second byte of each PTSCB is always an 8-bit value called PTSCON. Bits 5–7 select the PTSmode (Figure 5-15). The function of bits 0–4 differ for each PTS mode. Refer to the sections thatdescribe each mode in detail to see the function...

8XC196MC, MD, MH USER’S MANUAL 5-28 PTS Single Transfer Mode Control Block In single transfer mode, the PTS control block contains a source and destination address (PTSSRC and PTSDST), a control register (PTSCON), and a transfer count (PTSCOUNT). 7 0 Unused 0 0 0 0 0 0 0 0 7 0 Unused 0 0 0 0 0 0 0 0...

5-29 STANDARD AND PTS INTERRUPTS The PTSCB in Table 5-5 defines nine PTS cycles. Each cycle moves a single word from location20H to an external memory location. The PTS transfers the first word to location 6000H. Then itincrements and updates the destination address and decrements the PTSCOUNT regis...

8XC196MC, MD, MH USER’S MANUAL 5-30 5.6.4 Block Transfer Mode In block transfer mode, an interrupt causes the PTS to move a block of bytes or words from onememory location to another. See AP-483, Application Examples Using the 8XC196MC/MD Mi-crocontroller, for application examples with code. Figure ...

5-31 STANDARD AND PTS INTERRUPTS PTS Block Transfer Mode Control Block In block transfer mode, the PTS control block contains a block size (PTSBLOCK), a source and destination address (PTSSRC and PTSDST), a control register (PTSCON), and a transfer count (PTSCOUNT). 7 0 Unused 0 0 0 0 0 0 0 0 7 0 PT...

5-33 STANDARD AND PTS INTERRUPTS PTS A/D Scan Mode Control Block In A/D scan mode, the PTS causes the A/D converter to perform multiple conversions on one or more channels and then stores the results. The control block contains pointers to both the AD_RESULT register (PTSPTR1) and a table of A/D con...

5-45 STANDARD AND PTS INTERRUPTS 7. Enable EPA0 interrupt. — Set INT_MASK.2. 8. Load the number of bytes to transmit into the user_defined transmit count register(T_COUNT) and clear the user-defined transfer-done flag (TXDDONE). — LD T_COUNT, #16 — CLRB TXDDONE 9. Select PTS service for EPA0. — Set ...

8XC196MC, MD, MH USER’S MANUAL 5-46 time into the event-time register. If this toggle occurs, the clock polarity will changebecause of the odd number of toggles and erroneous data may be output. The interruptservice routine should also load the next data byte, reload the PTSCOUNT and PTSCON1register...

5-49 STANDARD AND PTS INTERRUPTS 8. Select PTS service for EPA0. — Set PTSSEL.2. 9. Set-up EPA0 to capture on both rising and falling edges. — Set EPA0_CON bits 4 and 5 (Figure 11-10 on page 11-19). 10. Enable the PTS and conventional interrupts. — Use the EI instruction to enable all standard inter...

8XC196MC, MD, MH USER’S MANUAL 5-50 Figure 5-24. Synchronous SIO Receive Mode — End-of-PTS Interrupt Routine Flowchart 5.6.6.3 Asynchronous SIO Transmit Mode Example In asynchronous serial I/O (ASIO) transmit mode, an EPA channel controls the transmission baudrate by generating an interrupt whenever...

5-51 STANDARD AND PTS INTERRUPTS Figure 5-25. Asynchronous SIO Transmit Timing The first PTS cycle must be started manually by generating a start bit and then setting up the tim-ing for the first EPA interrupt. • Initialize the TXD port pin to one before starting a transmission. • Write a zero to th...

5-55 STANDARD AND PTS INTERRUPTS 5.6.6.4 Asynchronous SIO Receive Mode Example In asynchronous serial I/O (ASIO) receive mode, an EPA channel is set up to capture the fallingedge when the data start bit toggles on a port pin that is configured to function as the Receive Datasignal (RXD). When the ca...

5-57 STANDARD AND PTS INTERRUPTS 11. Enable the PTS and conventional interrupts. — Use the EI instruction to enable all standard interrupts and the EPTS instruction to enable the PTS. 12. Toggle the RXD input to start the reception. The EPA will generate a conventional interrupt. This interrupt serv...

6-1 CHAPTER 6 I/O PORTS I/O ports provide a mechanism to transfer information between the device and the surroundingsystem circuitry. They can read system status, monitor system operation, output device status,configure system options, generate control signals, provide serial communication, and so o...

6-3 I/O PORTS 6.2.1 Standard Input-only Port Operation Figure 6-1 is a schematic of an input-only port pin. Transistors Q1 and Q2 serve as electrostaticdischarge (ESD) protection devices; they are referenced to V REF and ANGND. Transistor Q3 is an additional ESD protection device; it is referenced t...

8XC196MC, MD, MH USER’S MANUAL 6-4 6.2.2 Standard Input-only Port Considerations Port 0 and 1 pins are unique in that they may individually be used as digital inputs and analoginputs at the same time. However, reading the port induces noise into the A/D converter, decreas-ing the accuracy of any con...

8XC196MC, MD, MH USER’S MANUAL 6-6 Table 6-5 lists the registers associated with the bidirectional ports. Each port has three control reg-isters (Px_MODE, Px_DIR, and Px_REG); they can be both read and written. The Px_PIN regis-ter is a status register that returns the logic level present on the pin...

6-7 I/O PORTS In I/O mode (selected by clearing Px_MODE.y), Px_REG and Px_DIR are input to the multiplex-ers. These signals combine to drive the gates of Q1 and Q2 so that the output is high, low, or highimpedance. Table 6-6 is a logic table for I/O operation of these ports. In special-function mode...

8XC196MC, MD, MH USER’S MANUAL 6-8 Figure 6-2. Bidirectional Port Structure Vcc Q2 Q1 Px_REG Px_DIR Sample Latch PH1 Clock Internal Bus SFDATA SFDIR Px_MODE Px_PIN D Q 0 1 0 1 Vcc Vcc Q R S Any Write to Px_MODE WeakPullup MediumPullup RESET# RESET# Q3 Q4 Vss Read Port LE 300ns Delay I/O Pin A0238-04...

6-9 I/O PORTS 6.3.2 Bidirectional Port Pin Configurations Each bidirectional port pin can be individually configured to operate either as an I/O pin or as apin for a special-function signal. In the special-function configuration, the signal is controlled byan on-chip peripheral or an off-chip compon...

6-11 I/O PORTS 6.3.3 Bidirectional Port Pin Configuration Example Assume that you wish to configure the pins of a bidirectional port as shown in Table 6-9. To do so, you could use the following example code segment. Table 6-10 shows the state of eachpin after reset and after execution of each line o...

8XC196MC, MD, MH USER’S MANUAL 6-12 6.3.4 Bidirectional Port Considerations This section outlines special considerations for using the pins of these ports. Port 1 (8XC196MH) After reset, your software must configure the device to match theexternal system. This is accomplished by writing appropriate ...

6-13 I/O PORTS P5.0/ALE If EA# is high on reset (internal access), the pin is weakly held highuntil your software writes to P5_MODE. If EA# is low on reset(external access), either ALE or ADV# is activated as a systemcontrol pin, depending on the ALE bit of CCR0. In either case, thepin becomes a tru...

8XC196MC, MD, MH USER’S MANUAL 6-14 6.4 BIDIRECTIONAL PORTS 3 AND 4 (ADDRESS/DATA BUS) Ports 3 and 4 are eight-bit, bidirectional, memory-mapped I/O ports. They can be addressed onlywith indirect or indexed addressing and cannot be windowed. Ports 3 and 4 provide the multi-plexed address/data bus. I...

6-15 I/O PORTS 6.4.1 Bidirectional Ports 3 and 4 (Address/Data Bus) Operation Figure 6-3 shows the ports 3 and 4 logic. During reset, the active-low level of RESET# turns offQ1 and Q2 and turns on transistor Q3, which weakly pulls the pin high. (Q1 can source at least –3 mA at V CC –0.7 volts; Q2 ca...

8XC196MC, MD, MH USER’S MANUAL 6-16 6.4.2 Using Ports 3 and 4 as I/O To use a port pin as an output, write the output data to the corresponding Px_REG bit. When thedevice requires access to external memory, it takes control of the port and drives the address/databit onto the pin. The address/data bi...

6-17 I/O PORTS 6.5.1 Output-only Port Operation Figure 6-4 shows a simplified circuit schematic for port 6. Port 6 has a single configuration andcontrol register, WG_OUTPUT. Transistor Q1 can source at least –200 µA at V CC –0.3 volts. For pins P6.0–P6.5, transistor Q2 can sink at least 10 mA at 0.4...

7-1 CHAPTER 7 SERIAL I/O (SIO) PORT A serial input/output (SIO) port provides a means for the system to communicate with externaldevices. The 8XC196MH device has a two-channel serial I/O port that shares pins with ports 1and 2. (The 8XC196MC and 8XC196MD devices do not have serial I/O ports.) This c...

8XC196MC, MD, MH USER’S MANUAL 7-2 An independent, 15-bit baud-rate generator controls the baud rate of the serial port. Either XTAL1or BCLKx can provide the clock signal for modes 0–3. In mode 4, the internal shift clock is outputon SCLKx# or an external shift clock is input on SCLKx# (in which cas...

8XC196MC, MD, MH USER’S MANUAL 7-4 7.3 SERIAL PORT MODES The serial port has both synchronous and asynchronous operating modes for transmission and re-ception. This section describes the operation of each mode. PI_MASK 1FBCH Peripheral Interrupt Mask This register enables and disables multiplexed pe...

7-5 SERIAL I/O (SIO) PORT 7.3.1 Synchronous Modes (Modes 0 and 4) The 8XC196MH serial port has two synchronous modes, mode 0 and mode 4. Mode 0 is the syn-chronous mode available on all the 8XC196 devices that have serial ports. Mode 4 is an enhanced,full-duplex synchronous mode. 7.3.1.1 Mode 0 The ...

8XC196MC, MD, MH USER’S MANUAL 7-8 Figure 7-4. Serial Port Frames for Mode 1 The transmit and receive functions are controlled by separate shift clocks. The transmit shiftclock starts when the baud-rate generator is initialized. The receive shift clock is reset when a startbit (high-to-low transitio...

8XC196MC, MD, MH USER’S MANUAL 7-12 7.4.3 Programming the Baud Rate and Clock Source The SPx_BAUD register (Figure 7-7) selects the clock input for the baud-rate generator and de-fines the baud rate for all serial I/O modes. (For mode 4 with SCLKx# configured for input, thebaud-rate generator is not...

8XC196MC, MD, MH USER’S MANUAL 7-14 CAUTION For mode 0 receptions, the BAUD_VALUE must be 0002H or greater. Otherwise, the resulting data in the receive shift register will be incorrect. The reason for this restriction is that the receive shift register is clocked from an internal signal rather than...

7-15 SERIAL I/O (SIO) PORT 7.4.5 Determining Serial Port Status You can read the SPx_STATUS register (Figure 7-8) to determine the status of the serial port.Reading SPx_STATUS clears all bits except TXE. For this reason, we recommend that you copythe contents of the SPx_STATUS register into a shadow...

8-1 CHAPTER 8 FREQUENCY GENERATOR The 8XC196MD has a peripheral not found on other 8XC196Mx devices — the frequency gen-erator. This peripheral produces a waveform with a fixed duty cycle (50%) and a programmablefrequency (ranging from 4 kHz to 1 MHz with a 16-MHz input clock). One application for t...

8XC196MC, MD, MH USER’S MANUAL 8-2 The frequency register (FREQ_GEN) controls the output frequency. The frequency generatorloads the FREQ_GEN value into the counter. The counter counts down until it reaches zero, atwhich time the value is reloaded from the FREQ_GEN register. Each load toggles the D ...

8-3 FREQUENCY GENERATOR 8.2 PROGRAMMING THE FREQUENCY GENERATOR This section explains how to configure the frequency generator and determine its status. 8.2.1 Configuring the Output The frequency generator’s output is multiplexed with P7.7, so you must configure it as a special-function output signa...

8-5 FREQUENCY GENERATOR Figure 8-4. Infrared Remote Control Application Block Diagram Figure 8-5. Data Encoding Example This program example was designed to run on an 8XC196MD demo board. It uses an EPA timer (timer 1) and compare channel (COMP3) to provide the timebase for the ones and zeros. $debu...

9-1 CHAPTER 9 WAVEFORM GENERATOR A waveform generator simplifies the task of generating synchronized, pulse-width modulated(PWM) outputs. This waveform generator is optimized for motion control applications such asdriving 3-phase AC induction motors, 3-phase DC brushless motors, or 4-phase stepping ...

8XC196MC, MD, MH USER’S MANUAL 9-2 Figure 9-1. Waveform Generator Block Diagram A2637-01 Timebase Generator Phase DriverOne of Three Channels WG_RELOAD Buffer WG_RELOAD Update WG_RELOAD WG_COUNTER = 1WG InterruptWG_COUNTER = WG_RELOAD WG_COUNTER Phase Comparator Reload Comparator Dead-time & Out...

9-3 WAVEFORM GENERATOR 9.2 WAVEFORM GENERATOR SIGNALS AND REGISTERS Table 9-1 describes the waveform generator ’s signals, and Table 9-2 briefly describes the controland status registers. . Table 9-1. Waveform Generator Signals Port Pin WaveformGenerator Signal Type Description P6.0 WG1# O Waveform ...

9-5 WAVEFORM GENERATOR 9.3.2 Phase Driver Channels The phase driver channels determine the duty cycle of the outputs. You specify the duty cycle bywriting a value to each phase’s compare register (WG_COMPx). In all operating modes, the out-puts are initially asserted, and they remain asserted until ...

8XC196MC, MD, MH USER’S MANUAL 9-6 The protection circuitry (Figure 9-3) monitors the EXTINT pin. When it detects a valid event onthe input, it simultaneously disables the outputs and generates an EXTINT interrupt request. Soft-ware can also disable the outputs by clearing the enable outputs (EO) bi...

9-7 WAVEFORM GENERATOR The WG_RELOAD register is updated when the counter value reaches the reload value. TheWG_COUNTER register is loaded with the updated WG_RELOAD value, so a new reload valuetakes effect for the next cycle. In mode 3 (and mode 4 for the 8XC196MH), the WG_RELOADregister can be upd...

8XC196MC, MD, MH USER’S MANUAL 9-8 The main differences between the center-aligned modes and among the edge-aligned modes arethe events that control register updates. Table 9-4 lists the events that can cause register updatesand the registers that are updated in each mode. Table 9-3. Operation in Ce...

8XC196MC, MD, MH USER’S MANUAL 9-16 9.4.3 Specifying the Carrier Period and Duty Cycle The reload register (WG_RELOAD) and the phase compare registers (WG_COMPx) control thecarrier period and duty cycle. Write a value to the reload register (Figure 9-10) to establish thecarrier period. Write a value...

9-19 WAVEFORM GENERATOR 9.5 DETERMINING THE WAVEFORM GENERATOR’S STATUS Read WG_CONTROL (Figure 9-12 on page 9-18) to determine the current dead-time value,counter status, count direction, and operating mode. Read WG_COUNTER (Figure 9-13) to de-termine the current counter value. 9.6 ENABLING THE WAV...

8XC196MC, MD, MH USER’S MANUAL 9-20 To enable the interrupts, set the corresponding mask bits in the mask register (see Table 9-2 onpage 9-3) and execute the EI instruction to enable interrupt servicing. You can read the interruptpending register to determine whether there are any pending interrupts...

9-21 WAVEFORM GENERATOR 9.7.2 EXTINT Interrupts and Protection Circuitry The protection register contains two bits, disable protection (DP) and enable output (EO), that to- gether enable and disable the waveform generator’s outputs. The EXTINT event generates a sin- gle short pulse that clears the E...

10-1 CHAPTER 10 PULSE-WIDTH MODULATOR The pulse-width modulator (PWM) module has two output pins, each of which can output aPWM signal with a fixed, programmable frequency and a variable duty cycle. These outputs canbe used to drive motors that require an unfiltered PWM waveform for optimal efficien...

8XC196MC, MD, MH USER’S MANUAL 10-2 Figure 10-1. PWM Block Diagram 10.2 PWM SIGNALS AND REGISTERS Table 10-1 describes the PWM’s signals and Table 10-2 briefly describes the control and statusregisters. Table 10-1. PWM Signals Port Pin PWM Signal PWM Signal Type Description P6.6 PWM0 O Pulse-width m...

10-3 PULSE-WIDTH MODULATOR 10.3 PWM OPERATION The period register (PWM_PERIOD) controls the output frequency of both PWM outputs. Eachcontrol register (PWMx_CONTROL) controls the duty cycle (the pulsewidth stated as a percent-age of the period) of the corresponding PWM output. Each control register ...

8XC196MC, MD, MH USER’S MANUAL 10-4 The counter counts down to 00H, at which time the PWM output is driven high, the counter valueis reloaded from the PWM_PERIOD register, and the contents of the control registers are loadedinto the buffers. The PWM output remains high until the counter value matche...

8XC196MC, MD, MH USER’S MANUAL 10-6 10.5 PROGRAMMING THE DUTY CYCLE The values written to the PWMx_CONTROL and PWM_PERIOD registers control the width ofthe high pulse, effectively controlling the duty cycle. The 8-bit value written to the control regis-ter is loaded into a buffer, and this value is ...

10-7 PULSE-WIDTH MODULATOR 10.5.1 Sample Calculations For example, assume that F XTAL 1 equals 16 MHz and the value written to the PWM_PERIOD reg- ister is FFH, thus the desired period of the PWM output waveform is 8.19 ms. IfPWMx_CONTROL equals 8AH (138 decimal), the pulsewidth is held high for 4.4...

8XC196MC, MD, MH USER’S MANUAL 10-8 10.5.3 Enabling the PWM Outputs Each PWM output is multiplexed with a port pin, so you must configure it as a special-functionoutput signal before using the PWM function. To determine whether the corresponding pin func-tions as a standard I/O port pin or as a PWM ...

8XC196MC, MD, MH USER’S MANUAL 10-10 10.5.4 Generating Analog Outputs PWM modules can generate a rectangular pulse train that varies in duty cycle and period. Filter-ing this output will create a smooth analog signal. To make a signal swing over the desired analogrange, first buffer the signal and t...

11-1 CHAPTER 11 EVENT PROCESSOR ARRAY (EPA) Control applications often require high-speed event control. For example, the controller may needto periodically generate pulse-width modulated outputs or an interrupt. In another application, thecontroller may monitor an input signal to determine the stat...

8XC196MC, MD, MH USER’S MANUAL 11-2 Figure 11-1. EPA Block Diagram 11.2 EPA AND TIMER/COUNTER SIGNALS AND REGISTERS Table 11-2 describes the EPA and timer/counter input and output signals. Each signal is multi-plexed with a port pin as shown in the first column. Table 11-3 briefly describes the regi...

11-3 EVENT PROCESSOR ARRAY (EPA) P2.4P2.5P2.6P2.7 —— P2.4P2.5P2.6P2.7P7.2P7.3 P2.4P2.5P2.6P2.3 —— COMP0COMP1COMP2COMP3COMP4COMP5 O Output of the compare-only channels. Table 11-3. EPA Control and Status Registers Mnemonic Address Description MC MD MH COMP0_CONCOMP1_CONCOMP2_CONCOMP3_CONCOMP4_CONCOMP...

11-9 EVENT PROCESSOR ARRAY (EPA) Figure 11-4. Quadrature Mode Timing and Count 11.4 EPA CHANNEL FUNCTIONAL OVERVIEW The EPA has both programmable capture/compare and compare-only channels. Each cap-ture/compare channel can perform the following tasks. (The compare-only channels have thesame function...

8XC196MC, MD, MH USER’S MANUAL 11-12 An input capture event does not set the interrupt pending bit until the captured time value actuallymoves from the capture buffer into the EPAx_TIME register. If the buffer contains data and thePTS is used to service the interrupts, then two PTS interrupts occur ...

11-13 EVENT PROCESSOR ARRAY (EPA) 11.4.1.2 Preventing EPA Overruns Any one of the following methods can be used to prevent or recover from an EPA overrun situa-tion. • Clear EPAx_CON.0 When the overwrite bit (EPAx_CON.0) is zero, the EPA does not consider the capturededge until the EPAx_TIME registe...

8XC196MC, MD, MH USER’S MANUAL 11-14 The maximum output frequency depends upon the total interrupt latency and the interrupt-serviceexecution times used by your system. As additional EPA channels and the other functions of themicrocontroller are used, the maximum PWM frequency decreases because the ...

11-15 EVENT PROCESSOR ARRAY (EPA) With this method, the resolution of the EPA (selected by the TxCONTROL registers; see Figure11-8 on page 11-16 and Figure 11-9 on page 11-17) determines the maximum PWM output fre-quency. (Resolution is the minimum time required between consecutive captures or compa...

11-23 EVENT PROCESSOR ARRAY (EPA) 11.6 ENABLING THE EPA INTERRUPTS To enable the interrupts, set the corresponding bits in the INT_MASK register (Figure 5-7 onpage 5-15). To enable the individual sources of the multiplexed PI (MC, MD), SPI (MH), andOVRTM (Mx) interrupts, set the corresponding bits i...

8XC196MC, MD, MH USER’S MANUAL 11-24 11.7 DETERMINING EVENT STATUS In compare mode, an interrupt pending bit is set each time a match occurs on an enabled event(even if the interrupt is specifically masked in the mask register). In capture mode, an interruptpending bit is set each time a programmed ...

8XC196MC, MD, MH USER’S MANUAL 12-4 Once the A/D converter receives the command to start a conversion, a delay time elapses beforesampling begins. (EPA-initiated conversions begin after the capture/compare event. Immediateconversions, those initiated directly by a write to AD_COMMAND, begin within t...

8XC196MC, MD, MH USER’S MANUAL 12-6 12.4.3 Programming the A/D Time Register Two parameters, sample time and conversion time, control the time required for an A/D conver-sion. The sample time is the length of time that the analog input voltage is actually connected tothe sample capacitor. If this ti...

12-9 ANALOG-TO-DIGITAL (A/D) CONVERTER 12.5 DETERMINING A/D STATUS AND CONVERSION RESULTS You can read the AD_RESULT register (Figure 12-6) to determine the status of the A/D convert-er. The AD_RESULT register is cleared when a new conversion is started; therefore, to preventlosing data, you must re...

8XC196MC, MD, MH USER’S MANUAL 12-10 12.6 DESIGN CONSIDERATIONS This section describes considerations for the external interface circuitry and describes the errorsthat can occur in any A/D converter. The datasheet lists the absolute error specification, whichincludes all deviations between the actua...

12-11 ANALOG-TO-DIGITAL (A/D) CONVERTER Typically, the (R F / A V + 1) term is the major contributor to the total resistance and the factor that determines the minimum sample time specified in the datasheet. 12.6.1.1 Minimizing the Effect of High Input Source Resistance Under some conditions, the in...

12-13 ANALOG-TO-DIGITAL (A/D) CONVERTER ANGND should be within about ± 50 mV of V SS . V REF should be well regulated and used only for the A/D converter. The V REF supply can be between 4.5 and 5.5 volts and must be able to source approximately 5 mA (see the datasheet for actual specifications). V ...

12-15 ANALOG-TO-DIGITAL (A/D) CONVERTER Figure 12-9. Ideal A/D Conversion Characteristic Note that the ideal characteristic possesses unique qualities: • its first code transition occurs when the input voltage is 0.5 LSB; • its full-scale code transition occurs when the input voltage equals the full...

8XC196MC, MD, MH USER’S MANUAL 12-16 Figure 12-10. Actual and Ideal A/D Conversion Characteristics The actual characteristic of a hypothetical 3-bit converter is not perfect. When the ideal charac-teristic is overlaid with the actual characteristic, the actual converter is seen to exhibit errors int...

12-17 ANALOG-TO-DIGITAL (A/D) CONVERTER Differential nonlinearity is the degree to which actual code widths differ from the ideal one-LSBwidth. It provides a measure of how much the input voltage may have changed in order to producea one-count change in the conversion result. In the 10-bit converter...

13-1 CHAPTER 13 MINIMUM HARDWARE CONSIDERATIONS The 8XC196MC, MD, and MH have several basic requirements for operation within a system.This chapter describes options for providing the basic requirements and discusses other hardwareconsiderations. 13.1 MINIMUM CONNECTIONS Table 13-1 lists the signals...

8XC196MC, MD, MH USER’S MANUAL 13-2 13.1.1 Unused Inputs For predictable performance, it is important to tie unused inputs to V CC or V SS . Otherwise, they can float to a mid-voltage level and draw excessive current. Unused interrupt inputs may generatespurious interrupts if left unconnected. 13.1....

8XC196MC, MD, MH USER’S MANUAL 13-4 13.2 APPLYING AND REMOVING POWER When power is first applied to the device, RESET# must remain continuously low for at least onestate time after the power supply is within tolerance and the oscillator/clock has stabilized; oth-erwise, operation might be unpredicta...

13-5 MINIMUM HARDWARE CONSIDERATIONS If the A/D converter will be used, connect V REF to a separate reference supply to minimize noise during A/D conversions. Even if the A/D converter will not be used, V REF and ANGND must be connected to provide power to port 0. On the 8XC196MC and MD, they also p...

8XC196MC, MD, MH USER’S MANUAL 13-6 Figure 13-4 shows the connections between the external crystal and the device. When designingan external oscillator circuit, consider the effects of parasitic board capacitance, extended oper-ating temperatures, and crystal specifications. Consult the manufacturer...

13-7 MINIMUM HARDWARE CONSIDERATIONS 13.5 USING AN EXTERNAL CLOCK SOURCE To use an external clock source, apply a clock signal to XTAL1 and let XTAL2 float (Figure13-5). To ensure proper operation, the external clock source must meet the minimum high andlow times (T XH XX and T XLX X ) and the maxim...

8XC196MC, MD, MH USER’S MANUAL 13-8 13.6 RESETTING THE DEVICE Reset forces the device into a known state. As soon as RESET# is asserted, the I/O pins, the con-trol pins, and the registers are driven to their reset states. (Tables in Appendix B list the reset statesof the pins (see Table B-8 on page ...

13-9 MINIMUM HARDWARE CONSIDERATIONS The 8XC196MH provides the option of an internal-only reset or an internal reset that is also re-flected externally (by the RESET# pin). The GEN_CON register controls whether an internal re-set asserts the external RESET# signal and indicates the source of the mos...

8XC196MC, MD, MH USER’S MANUAL 13-10 Figure 13-9. Internal Reset Circuitry 13.6.1 Generating an External Reset To reset the device, hold the RESET# pin low for at least one state time after the power supply iswithin tolerance and the oscillator has stabilized. When RESET# is first asserted, the devi...

13-11 MINIMUM HARDWARE CONSIDERATIONS Figure 13-10. Minimum Reset Circuit Other devices in the system may not be reset because the capacitor will keep the voltage aboveV IL . Since RESET# is asserted for only 16 state times, it may be necessary to lengthen and buffer the system-reset pulse. Figure 1...

8XC196MC, MD, MH USER’S MANUAL 13-12 13.6.2 Issuing the Reset (RST) Instruction The RST instruction (opcode FFH) resets the device by pulling RESET# low for 16 state times.It also clears the processor status word (PSW), sets the master program counter (PC) to 2080H,and resets the special function re...

13-13 MINIMUM HARDWARE CONSIDERATIONS You must write two consecutive bytes to the watchdog register (location 0AH) to clear it. For the8XC196MC and MD, the first byte must be 1EH and the second must be E1H. For the8XC196MH, the first byte must also be 1EH; however, the second byte can be one of four...

14-1 CHAPTER 14 SPECIAL OPERATING MODES The 8XC196MC, MD, and MH provide two power saving modes: idle and powerdown. Theyalso provide an on-circuit emulation (ONCE) mode that electrically isolates the device from theother system components. This chapter describes each mode and explains how to enter ...

8XC196MC, MD, MH USER’S MANUAL 14-2 P5.4 ONCE# I On-circuit Emulation Holding ONCE# low during the rising edge of RESET# places the device into on-circuit emulation (ONCE) mode. This mode puts all pins, except XTAL1 and XTAL2, into a high-impedance state, thereby isolating the device from other comp...

14-3 SPECIAL OPERATING MODES 14.2 REDUCING POWER CONSUMPTION Both power-saving modes conserve power by disabling portions of the internal clock circuitry(Figure 14-1). The following paragraphs describe both modes in detail. P1_DIR (MH)P2_DIRP5_DIRP7_DIR (MD) 1F9BH1FD2H1FF3H1FD3H Port x Direction Eac...

14-5 SPECIAL OPERATING MODES The device enters idle mode after executing the IDLPD #1 instruction. Any enabled interruptsource, either internal or external, or a hardware reset can cause the device to exit idle mode.When an interrupt occurs, the CPU clocks restart and the CPU executes the corre spon...

8XC196MC, MD, MH USER’S MANUAL 14-6 14.4.2 Entering Powerdown Mode Before entering powerdown, complete the following tasks: • Complete all serial port transmissions or receptions. Otherwise, when the device exitspowerdown, the serial port activity will continue where it left off and incorrect data m...

14-7 SPECIAL OPERATING MODES 14.4.3.3 Asserting the External Interrupt Signal The final way to exit powerdown mode is to assert the external interrupt signal (EXTINT) for atleast 50 ns. Although EXTINT is normally a sampled input, the powerdown circuitry uses it as alevel-sensitive input. The interr...

14-9 SPECIAL OPERATING MODES Figure 14-4. Typical Voltage on the V PP Pin While Exiting Powerdown Select a resistor that will not interfere with the discharge current. In most cases, values between200 k Ω and 1 M Ω should perform satisfactorily. VPP, Volts 1 2 3 4 5 200 µ A C1 Discharge Pullup On Co...

14-11 SPECIAL OPERATING MODES Holding the ONCE# signal low during the rising edge of RESET# causes the device to enterONCE mode. To prevent accidental entry into ONCE mode, we highly recommend configuringthis pin as an output. If you choose to configure this pin as an input, always hold it high duri...

15-1 CHAPTER 15 INTERFACING WITH EXTERNAL MEMORY The microcontroller can interface with a variety of external memory devices. It supports either afixed 8-bit data bus width, a fixed 16-bit data bus width, or a dynamic 8-bit/16-bit data bus width;internal control of wait states for slow external memo...

8XC196MC, MD, MH USER’S MANUAL 15-4 WRH# P5.5 O Write High † During 16-bit bus cycles, this active-low output signal is asserted for high-byte writes and word writes to external memory. During 8-bit bus cycles, WRH# is asserted for all write operations. † The chip configuration register 0 (CCR0) det...

15-5 INTERFACING WITH EXTERNAL MEMORY 15.2 CHIP CONFIGURATION REGISTERS AND CHIP CONFIGURATION BYTES Two chip configuration registers (CCRs) have bits that set parameters for chip operation and ex-ternal bus cycles. The CCRs cannot be accessed by code. They are loaded from the chip config-uration by...

8XC196MC, MD, MH USER’S MANUAL 15-10 15.3 BUS WIDTH AND MULTIPLEXING The external bus can operate as either a 16-bit multiplexed address/data bus or as a multiplexed16-bit address/8-bit data bus (Figure 15-3). 1 IRC2 Ready Control This bit, along with IRC0 (CCR0.4), IRC1 (CCR0.5), and the READY pin ...

8XC196MC, MD, MH USER’S MANUAL 15-12 Figure 15-4. BUSWIDTH Timing Diagram (8XC196MC, MD) Figure 15-5. BUSWIDTH Timing Diagram (8XC196MH) AD15:0 XTAL1 BUSWIDTH ALE CLKOUT † T AVGV T CLGX (min) Valid A3162-01 Address Out Data In † The CLKOUT pin is available only on the 8XC196MC, MD. T XTAL1 XTAL1 T X...

15-13 INTERFACING WITH EXTERNAL MEMORY . The BUSWIDTH signal can be used in numerous applications. For example, a system could storecode in a 16-bit memory device and data in an 8-bit memory device. The BUSWIDTH signalcould be tied to the chip-select input of the 8-bit memory device (shown in Figure...

8XC196MC, MD, MH USER’S MANUAL 15-20 Figure 15-9. READY Timing Diagram — One Wait State (8XC196MH) Table 15-5. READY Signal Timing Definitions Symbol Definition T AV YV Address Valid to READY Setup Maximum time the external device has to deassert READY after the microcontroller outputs the address t...

15-29 INTERFACING WITH EXTERNAL MEMORY Figure 15-19 shows a 16-bit system with two EPROMs. This system configuration uses theADV# signal as both the EPROM chip-select signal and the address-latch signal. Figure 15-19. 16-bit System with EPROM A3095-01 V CC AD7:0 AD15:8 RD# ADV# 74AC 373 74AC 373 A13...

8XC196MC, MD, MH USER’S MANUAL 15-30 15.5.4 Address Valid with Write Strobe Mode When the address valid with write strobe mode is selected, the microcontroller generates theADV#, RD#, WRL#, and WRH# bus-control signals. This mode is used for a simple system us-ing an external 16-bit data bus. Figure...

15-31 INTERFACING WITH EXTERNAL MEMORY Figure 15-21. 16-bit System with RAM 15.6 SYSTEM BUS AC TIMING SPECIFICATIONS Refer to the latest datasheet for the AC timings to make sure your system meets specifications.The major external bus timing specifications are shown in Figure 15-22. AD7:0 AD15:8 WRL...

15-33 INTERFACING WITH EXTERNAL MEMORY 15.6.1 Explanation of AC Symbols Each symbol consists of two pairs of letters prefixed by “T” (for time). The characters in a pairindicate a signal and its condition, respectively. Symbols represent the time between the two sig-nal/condition points. For example...

8XC196MC, MD, MH USER’S MANUAL 15-34 Table 15-9. Microcontroller Meets These Specifications Symbol Definition T AV LL Address Setup to ALE/ADV# Low Length of time address is valid before ALE/ADV# falls. Useful when using an external latch to demultiplex the address from the address data bus. T CHCL ...

16-1 CHAPTER 16 PROGRAMMING THE NONVOLATILE MEMORY The 87C196MC and 87C196MD contain 16 Kbytes of one-time-programmable read-only mem-ory (OTPROM ); the 87C196MH contains 32 Kbytes. OTPROM is similar to EPROM, but itcomes in an unwindowed package and cannot be erased. You can either program the OTPR...

8XC196MC, MD, MH USER’S MANUAL 16-2 mode, you can program and verify single or multiple words in the OTPROM. This modeallows you to read the signature word and programming voltages and to program thePCCBs and unerasable PROM (UPROM) bits. Programming vendors and Intel distributorstypically use this ...

16-3 PROGRAMMING THE NONVOLATILE MEMORY 16.3 SECURITY FEATURES Several security features enable you to control access to both internal and external memory. Readand write protection bits in the chip configuration register (CCR0), combined with a security key,allow various levels of internal memory pr...

8XC196MC, MD, MH USER’S MANUAL 16-4 16.3.1.1 Controlling Access to the OTPROM During Normal Operation During normal operation, the lock bits in CCB0 control read and write accesses to the OTPROM.Table 16-2 describes the options. You can program the CCBs using any of the programmingmethods. Clearing ...

8XC196MC, MD, MH USER’S MANUAL 16-6 You can program the internal security key in either auto or slave programming mode. Once thesecurity key is programmed, you must provide a matching key to gain access to any programmingmode. For auto programming and ROM-dump modes, a matching security key must res...

8XC196MC, MD, MH USER’S MANUAL 16-8 16.4 PROGRAMMING PULSE WIDTH The programming pulse width is controlled in different ways, depending on the programmingmode. In slave programming mode, the pulse width is controlled by the PALE# signal. In autoprogramming mode, it is loaded from the external EPROM ...

16-11 PROGRAMMING THE NONVOLATILE MEMORY 16.6 PROGRAMMING MODE PINS Figure 16-4 illustrates the signals used in programming and Table 16-6 describes them. The EA#,V PP , and PMODE pins combine to control entry into programming modes. You must configure the PMODE (P0.7:4) pins to select the desired p...

16-13 PROGRAMMING THE NONVOLATILE MEMORY 16.7 ENTERING PROGRAMMING MODES To execute programs properly, the device must have these minimum hardware connections:XTAL1 driven, unused input pins strapped, and power and grounds applied. Follow the operatingconditions specified in the datasheet. Place the...

16-15 PROGRAMMING THE NONVOLATILE MEMORY 16.8 SLAVE PROGRAMMING MODE Slave programming mode allows you to program and verify the entire OTPROM array, includingthe PCCBs and UPROM bits, by using an EPROM programmer. In this mode, ports 3 and 4 serve as the PBUS, transferring commands, addresses, and ...

8XC196MC, MD, MH USER’S MANUAL 16-16 16.8.2 Slave Programming Circuit and Memory Map Figure 16-5 shows the circuit diagram and Table 16-9 shows the memory map for slave program-ming mode. The external clock signal can be supplied by either a clock or a crystal. Refer to thedevice datasheet for accep...

16-17 PROGRAMMING THE NONVOLATILE MEMORY 16.8.3 Operating Environment The chip configuration registers (CCRs) define the system environment. Since the programmingenvironment is not necessarily the same as the application environment, the device provides ameans for specifying different configurations...

16-25 PROGRAMMING THE NONVOLATILE MEMORY 16.9 AUTO PROGRAMMING MODE The auto programming mode is a low-cost programming alternative. Using this programmingmode, the device programs itself with data from an external EPROM (external locations 4000Hand above; see Table 16-1 on page 16-3). A bank switch...

16-29 PROGRAMMING THE NONVOLATILE MEMORY If the security key verification is successful, the routine loads the programming pulse width(PPW) value from the external EPROM into the internal PPW register. It then asserts PACT#, in-dicating that programming has begun. (PACT# is also active during reset,...

8XC196MC, MD, MH USER’S MANUAL 16-30 2. Using another blank EPROM device, follow these steps to program only CCB0. — Place the programming pulse width (PPW) in external locations 14H–15H. — Place the appropriate CCB0 value in external location 4018H. — Place the security key to be verified in extern...

8XC196MC, MD, MH USER’S MANUAL 16-32 Assert PALE# to begin programming. The algorithm sends five programming pulses that writethe port 3 data to the OTPROM, then it compares the input data with the programmed data. If theprogramming verifies, the PVER signal lights the LED to indicate successful pro...

A-3 INSTRUCTION SET REFERENCE Table A-1. Opcode Map (Right Half) Opcode x 8 x 9 x A x B x C x D x E x F 0 x SHR SHL SHRA XCH ix SHRL SHLL SHRAL NORML 1x SHRB SHLB SHRAB XCHB ix 2 x SCALL 3 x JBS bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 4 x SUB 3op MULU 3op (Note 2) di im in ix di im in ix 5 x...

A-5 INSTRUCTION SET REFERENCE Table A-3 shows the effect of the PSW flags or a specified condition on conditional jump instruc-tions. Table A-4 defines the symbols used in Table A-6 to show the effect of each instruction onthe PSW flags. . Table A-3. Effect of PSW Flags or Specified Conditions on Co...

A-41 INSTRUCTION SET REFERENCE Table A-7 lists the instruction opcodes, in hexadecimal order, along with the corresponding in-struction mnemonics. Table A-7. Instruction Opcodes Hex Code Instruction Mnemonic 00 SKIP 01 CLR 02 NOT 03 NEG 04 XCH Direct 05 DEC 06 EXT 07 INC 08 SHR 09 SHL 0A SHRA 0B XCH...

B-1 APPENDIX B SIGNAL DESCRIPTIONS This appendix provides reference information for the pin functions of the 8XC196MC,8XC196MD, and 8XC196MH. B.1 SIGNAL NAME CHANGES The names of some 8XC196MC and 8XC196MD signals have been changed for consistency with other MCS ® 96 microcontrollers. Table B-1 list...

8XC196MC, MD, MH USER’S MANUAL B-2 Table B-2. 8XC196MC Signals Arranged by Functional Categories Address & Data Programming Control Input/Output Input/Output (Cont’d) AD15:0 AINC# P0.7:0/ACH7:0 P6.5/WG3 CPVER P1.0/ACH8 P6.6/PWM0 Bus Control & Status PACT# P1.1/ACH9 P6.7/PWM1 ALE/ADV# PALE# P...

B-3 SIGNAL DESCRIPTIONS Figure B-1. 8XC196MC 64-lead Shrink DIP (SDIP) Package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P5.6 / READY P5.4 / ONCE# EXTINT V SS XTAL1 XTAL2 P6.6 / PWM0 P6.7 / PWM1 P2.6 / COMP2 / CPVER P2.5 / COMP1 / PACT# P2.4 / COMP0 / AIN...

8XC196MC, MD, MH USER’S MANUAL B-6 Table B-3. 8XC196MD Signals Arranged by Functional Categories Address & Data Programming Control Input/Output Input/Output (Cont’d) AD15:0 AINC# P0.7:0/ACH7:0 P7.1:0/EPA5:4 CPVER P1.1:0/ACH9:8 P7.3:2/COMP5:4 Bus Control & Status PACT# P1.2/ACH10/T1CLK P7.6:...

B-13 SIGNAL DESCRIPTIONS Table B-5. Description of Columns of Table B-6 Column Heading Description Name Lists the signals, arranged alphabetically. Many pins have two functions, so there are more entries in this column than there are pins. Every signal is listed in this column. Type Identifies the p...

8XC196MC, MD, MH USER’S MANUAL B-22 B.4 DEFAULT CONDITIONS Table B-8 lists the values of the signals of the 8XC196MC and 8XC196MD during various oper-ating conditions. The shaded rows indicate those signals that are available only on the WG3:1 O Waveform Generator Phase 1–3 Positive Outputs 3-phase ...

B-23 SIGNAL DESCRIPTIONS 8XC196MD. Table B-9 lists the same information for the 8XC196MH. Table B-7 defines thesymbols used to represent the pin status. Refer to the DC Characteristics table in the datasheet foractual specifications for V OL , V IL , V OH , and V IH . Table B-7. Definition of Status...

C-1 APPENDIX C REGISTERS This appendix provides reference information about the device registers. Table C-1 lists the mod-ules and major components of the device with their related configuration and status registers. Ta-ble C-2 lists the registers, arranged alphabetically by mnemonic, along with the...

C-3 REGISTERS EPA1_TIME EPA Capture/Comp 1 Time 1F46 XXXX XXXX XXXX XXXX EPA2_TIME (MC, MD) EPA Capture/Comp 2 Time 1F4A XXXX XXXX XXXX XXXX EPA3_TIME (MC, MD) EPA Capture/Comp 3 Time 1F4E XXXX XXXX XXXX XXXX EPA4_TIME (MD) EPA Capture/Comp 4 Time 1F52 XXXX XXXX XXXX XXXX EPA5_TIME (MD) EPA Capture/...

8XC196MC, MD, MH USER’S MANUAL C-20 EPAx_CON 0 ON/RT Overwrite New/Reset Timer The ON/RT bit functions as overwrite new in capture mode and reset timer in compare mode. In Capture Mode (ON): An overrun error is generated when an input capture occurs while the event-time register (EPA x _TIME) and it...

8XC196MC, MD, MH USER’S MANUAL C-30 Px_DIR P x _DIR x = 2, 5 (8XC196MC) x = 2, 5, 7 (8XC196MD) x = 1, 2, 5 (8XC196MH) Address: Reset State: Table C-6 Each pin of port x can operate in any of the standard I/O modes of operation: complementary output, open-drain output, or high-impedance input. The po...

C-31 REGISTERS Px_MODE P x _MODE x = 2, 5 (8XC196MC) x = 2, 5, 7 (8XC196MD) x = 1, 2, 5 (8XC196MH) Address: Reset State: Table C-7 Each bit of the port x mode (P x _MODE) register controls whether the corresponding pin functions as a standard I/O port pin or as a special-function signal. 7 0 x = 1 (...

8XC196MC, MD, MH USER’S MANUAL C-34 Px_REG P x _REG x = 2–5 (8XC196MC) x = 2–5, 7 (8XC196MD) x = 1–5 (8XC196MH) Address: Reset State: Table C-10 For an input, set the corresponding port x data output (P x _REG) register bit. For an output, write the data to be driven out by each pin to the correspon...

C-39 REGISTERS PPW PPW no direct access The programming pulse width (PPW) register is loaded from the external EPROM (locations 14H and 15H for the 8XC196MC and MD; locations 4014H and 4015H for the 8XC196MH) in auto programming mode. The PPW_VALUE determines the programming pulse width. 15 8 PPW15 ...

8XC196MC, MD, MH USER’S MANUAL C-40 PSW PSW no direct access The processor status word (PSW) actually consists of two bytes. The high byte is the status word, which is described here; the low byte is the INT_MASK register. The status word contains one bit (PSW.1) that globally enables or disables se...

C-41 REGISTERS PSW 12 VT Overflow-trap Flag This flag is set when the overflow flag is set, but it is cleared only by the CLRVT, JVT, and JNVT instructions. This allows testing for a possible overflow at the end of a sequence of related arithmetic operations, which is generally more efficient than t...

8XC196MC, MD, MH USER’S MANUAL C-42 PTSSEL PTSSEL Address: Reset State: 0004H0000H The PTS select (PTSSEL) register selects either a PTS microcode routine or a standard interrupt service routine for each interrupt request. Setting a bit selects a PTS microcode routine; clearing a bit selects a stand...

C-43 REGISTERS PTSSRV PTSSRV Address: Reset State: 0006H0000H The PTS service (PTSSRV) register is used by the hardware to indicate that the final PTS interrupt has been serviced by the PTS routine. When PTSCOUNT reaches zero, hardware clears the corre-sponding PTSSEL bit and sets the PTSSRV bit, wh...

C-47 REGISTERS SBUFx_RX SBUF x _RX x = 0–1 (8XC196MH) Address: Reset State: 1F80H, 1F88H 00H The serial port receive buffer x (SBUF x _RX) register contains data received from serial port x . The serial port receiver is buffered and can begin receiving a second data byte before the first byte is rea...

C-53 REGISTERS T1CONTROL T1CONTROL Address: Reset State: 1F78H 00H The timer 1 control (T1CONTROL) register determines the clock source, counting direction, and count rate for timer 1. 7 0 CE UD M2 M1 M0 P2 P1 P0 Bit Number Bit Mnemonic Function 7 CE Counter Enable This bit enables or disables the t...

8XC196MC, MD, MH USER’S MANUAL C-54 T1RELOAD T1RELOAD Address: Reset State: 1F72H XXXXH The timer 1 reload (T1RELOAD) register contains a reinitialization value for timer 1. The value of T1RELOAD is loaded into TIMER1 when timer 1 overflows or underflows and both quadrature clocking and the reload f...

C-55 REGISTERS T2CONTROL T2CONTROL Address: Reset State: 1F7CH 00H The timer 2 control (T2CONTROL) register determines the clock source, counting direction, and count rate for timer 2. 7 0 CE UD M2 M1 M0 P2 P1 P0 Bit Number Bit Mnemonic Function 7 CE Counter Enable This bit enables or disables the t...

8XC196MC, MD, MH USER’S MANUAL C-56 TIMERx TIMER x x = 1–2 Address: Reset State: 1F7AH, 1F7EH 0000H This register contains the value of timer x . This register can be written, allowing timer x to be initialized to a value other than zero. 15 0 Timer Value Bit Number Function 15:0 Timer Value Read th...

8XC196MC, MD, MH USER’S MANUAL C-58 WATCHDOG WATCHDOG Address: Reset State: 0AH XXH Unless it is cleared every 64K state times, the watchdog timer resets the device. To clear the watchdog timer, send “1EH” followed immediately by “E1H” to location 0AH. Clearing this register the first time enables t...

8XC196MC, MD, MH USER’S MANUAL C-68 WSR WSR Address: Reset State: 0014H 00H The window selection register (WSR) maps sections of RAM into the top of the lower register file, in 32-, 64-, or 128-byte increments. PUSHA saves this register on the stack and POPA restores it. 7 0 — W6 W5 W4 W3 W2 W1 W0 B...

Glossary-1 GLOSSARY This glossary defines acronyms, abbreviations, and terms that have special meaning in this man-ual. (Chapter 1 discusses notational conventions and general terminology.) absolute error The maximum difference between correspondingactual and ideal code transitions. Absolute errorac...

8XC196MC, MD, MH USER’S MANUAL Glossary-2 CCBs Chip configuration bytes. The chip configurationregisters (CCRs) are loaded with the contents of theCCBs after a device reset, unless the device isentering programming modes, in which case thePCCBs are used. CCRs Chip configuration registers. Registers ...

Glossary-3 GLOSSARY deassert The act of making a signal inactive (disabled). Thepolarity (high or low) is defined by the signal name.Active-low signals are designated by a pound symbol(#) suffix; active-high signals have no suffix. Todeassert RD# is to drive it high; to deassert ALE is todrive it lo...

Glossary-5 GLOSSARY LSB 1) Least-significant bit of a byte or least-significantbyte of a word. 2) In an A/D converter, the reference voltage dividedby 2 n , where n is the number of bits to be converted. For a 10-bit converter with a reference voltage of 5.12volts, one LSB is equal to 5.0 millivolts...

Glossary-7 GLOSSARY program memory A partition of memory where instructions can bestored for fetching and execution. protected instruction An instruction that prevents an interrupt from beingacknowledged until after the next instructionexecutes. The protected instructions are DI, EI, DPTS,EPTS, POPA...

Glossary-9 GLOSSARY sample time The period of time that the sample window is open.(That is, the length of time that the input channel isactually connected to the sample capacitor.) sample time uncertainty The variation in the sample time. sample window The period of time that begins when the samplec...

Glossary-11 GLOSSARY transfer function errors Errors inherent in an analog-to-digital conversionprocess: quantizing error, zero-offset error, full-scaleerror, differential nonlinearity, and nonlinearity.Errors that are hardware-dependent, rather than beinginherent in the process itself, include feed...

Index-1 #, defined, 1-3, A-116-bit data bus read cycles, 15-14timing diagram, 15-15write cycles, 15-14 8-bit data bus read cycles, 15-16timing diagram, 15-17write cycles, 15-16 A A/D command register, 12-8, C-6A/D converter, 2-11, 12-1–12-18 actual characteristic, 12-16and port 0 reads, 12-13and PTS...

8XC196MC, MD, MH USER’S MANUAL Index-4 re-enabling the compare event, 11-20, 11-22reloading the waveform generator, 11-20, 11-23, C-16 resetting the timer in compare mode, 11-21resetting the timers, 11-21, 11-23selecting the capture/compare event, 11-19selecting the compare event, 11-22selecting the...

Index-5 INDEX Hypertext manuals and datasheets, downloading, 1-10 I Idle mode, 2-11, 13-13, 14-4–14-5 entering, 14-5pin status, B-23, B-25timeout control, 11-7 IDLPD instruction, A-2, A-16, A-46, A-51, A-57 IDLPD #1, 14-5IDLPD #2, 14-6illegal operand, 13-9, 13-12 Immediate addressing, 3-6INC instruc...

Index-7 INDEX ORB instruction, A-2, A-28, A-43, A-48, A-53Oscillator and powerdown mode, 14-5external crystal, 13-6on-chip, 13-5 OTPROM controlling access to internal memory, 16-3–16-6 controlling fetches from external memory, 16-6–16-7 memory map, 16-2programming, 16-1–16-33 See also programming mo...

8XC196MC, MD, MH USER’S MANUAL Index-8 SFRs, 6-6, 14-3 Port 3, B-18 addressing, 6-14idle, powerdown, reset status, B-23, B-25operation, 6-15–6-16overview, 6-1pin configuration, 6-14structure, 6-15 Port 4, B-18 addressing, 6-14idle, powerdown, reset status, B-23, B-25operation, 6-15–6-16overview, 6-1...

Index-9 INDEX instructions, A-51, A-57interrupt latency, 5-11interrupt processing flow, 5-2routine, defined, 5-1serial I/O modes, 5-37–5-58single transfer mode, 5-27synchronous serial I/O receive mode, 5-47–5-50 synchronous serial I/O transmit mode, 5-43–5-46 vectors, memory locations, 4-3See also P...

Index-11 INDEX RST instruction, 3-11, 13-9, 13-12, A-3, A-31, A-46, A-51, A-57 Run-time programming, 16-32–16-33 code example, 16-33 RXD, B-20 and SIO port mode 0, 7-5, 7-7and SIO port modes 1, 2, and 3, 7-7 S Sampled input, B-13SBUFx_RX, C-70SBUFx_TX, C-70SCALL instruction, A-3, A-31, A-41, A-47, A...

Index-13 INDEX Timing diagrams 16-bit data bus, 15-158-bit data bus, 15-17BUSWIDTH, 15-12READY, 15-19system bus timing, 15-32 Timing requirements BUSWIDTH, 15-13READY, 15-18 TRAP instruction, 5-6, A-2, A-39, A-46, A-50, A-55, A-56 TRAP interrupt, 5-4TXD, B-21 and SIO port mode 0, 7-5 U UART, 2-9, 7-...

8XC196MC, MD, MH USER’S MANUAL Index-14 WSR values and direct addresses, 4-15 WORD, defined, 3-2World Wide Web, 1-11WR#, B-22 idle, powerdown, reset status, B-23, B-25 WRH#, B-22Write cycles 16-bit data bus, 15-148-bit data bus, 15-16 Write strobe mode example system, 15-26signals, 15-25 WRL#, B-22W...