Texas Instruments TMS320VC5402 - Manuals

Texas Instruments TMS320VC5402 – Manual in PDF format online.

Manuals:

Manual

Manual Texas Instruments TMS320VC5402

Summary

Page 3 - description

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 3 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 description The TMS320VC5402 fixed-point, digital signal processor (DSP) (hereafter referred to as the ’5402 unlessotherwise specified) is based on an advanced modified Harvard architecture that has one ...

Page 12 - memory; on-chip ROM with bootloader; TMS320C54x DSP CPU and Peripherals Reference Set,

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 memory The ’5402 device provides both on-chip ROM and RAM memories to aid in system performance and integration. on-chip ROM with bootloader The ’5402 features a 4K-word × 16-bit on-chip maskable ROM. C...

Page 14 - Twenty address lines, instead of sixteen

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 relocatable interrupt vector table (continued) 15 7 6 5 4 3 2 1 0 IPTR MP/MC OVLY AVIS DROM CLK OFF SMUL SST R/W R/W R/W R R R R/W R/W LEGEND: R = Read, W = Write Figure 2. Processor Mode Status (PMST) ...

Page 15 - Figure 3. Extended Program Memory

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 15 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 0 0000 1 0000 1 3FFF Page 1 Lower 16K External 2 0000 2 3FFF Page 2 Lower 16K External . . . . . . F 0000 F 3FFF Page 15 Lower 16K External 0 FFFF Page 0 64K Words 1 4000 1 FFFF Page 1 Upper 48K Externa...

Page 16 - software-programmable wait-state generator

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 on-chip peripherals The ’5402 device has the following peripherals: Software-programmable wait-state generator with programmable bank-switching wait states An enhanced 8-bit host-port interface (HPI8) T...

Page 18 - programmable bank-switching wait states

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 programmable bank-switching wait states The programmable bank-switching logic of the ’5402 is functionally equivalent to that of the ’548/’549 devices.This feature automatically inserts one cycle when a...

Page 20 - multichannel buffered serial ports

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 multichannel buffered serial ports The ’5402 device includes two high-speed, full-duplex multichannel buffered serial ports (McBSPs) that allowdirect interface to other ’C54x/’LC54x devices, codecs, and...

Page 21 - multichannel buffered serial ports (continued); Frame synchronization pulse width; hardware timer

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 21 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 multichannel buffered serial ports (continued) On the receiver, receive frame synchronization and clocking are indicated by the BFSR and BCLKR pins,respectively. The CPU or DMA can read received data fr...

Page 22 - Table 5. Clock Mode Settings at Reset

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 clock generator (continued) The reference clock input is then divided by two (DIV mode) to generate clocks for the ’5402 device, or the PLLcircuit can be used (PLL mode) to generate the device clock by ...

Page 23 - The DMA has the following features:; DMA memory map

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 23 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 DMA controller The ’5402 direct memory access (DMA) controller transfers data between points in the memory map withoutintervention by the CPU. The DMA controller allows movements of data to and from int...

Page 27 - memory-mapped registers

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 27 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 memory-mapped registers The ’5402 has 27 memory-mapped CPU registers, which are mapped in data memory space addresses 0h to1Fh. Table 9 gives a list of CPU memory-mapped registers (MMRs) available on ’5...

Page 28 - Table 10. Peripheral Memory-Mapped Registers

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 memory-mapped registers (continued) Table 10. Peripheral Memory-Mapped Registers NAME ADDRESS DESCRIPTION TYPE DRR20 20h ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ McBSP0 data receive register 2 McBSP #0 D...

Page 29 - McBSP control registers and subaddresses; Table 11. McBSP Control Registers and Subaddresses; DMA subbank addressed registers

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 29 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 McBSP control registers and subaddresses The control registers for the multichannel buffered serial port (McBSP) are accessed using the subbankaddressing scheme. This allows a set or subbank of register...

Page 30 - DMA subbank addressed registers (continued); Table 12. DMA Subbank Addressed Registers

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 30 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 DMA subbank addressed registers (continued) Table 12. DMA Subbank Addressed Registers DMA NAME ADDRESS SUB- ADDRESS DESCRIPTION DMSRC0 56h/57h ÁÁÁÁÁ ÁÁÁÁÁ 00h DMA channel 0 source address register DMDST...

Page 31 - interrupts; Table 13. Interrupt Locations and Priorities

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 31 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 interrupts Vector-relative locations and priorities for all internal and external interrupts are shown in Table 13. Table 13. Interrupt Locations and Priorities NAME LOCATION DECIMAL HEX PRIORITY FUNCTI...

Page 33 - documentation support

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 33 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 documentation support Extensive documentation supports all TMS320  DSP family of devices from product announcement through applications development. The following types of documentation are available t...

Page 34 - Supply voltage core range, CV; DD; Input voltage range, V; stg; recommended operating conditions

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 absolute maximum ratings over specified temperature range (unless otherwise noted) † Supply voltage I/O range, DV DD ‡ –0.3 V to 4.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

Page 35 - PARAMETER MEASUREMENT INFORMATION

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 35 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 electrical characteristics over recommended operating case temperature range (unless otherwisenoted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VOH High-level output voltage IOH = MAX 2.4 V VOL Low-lev...

Page 36 - internal oscillator with external crystal; and power dissipation of 1 mW.; Figure 10. Internal Oscillator With External Crystal

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 internal oscillator with external crystal The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN. The frequency of CLKOUTis a multiple of the oscillator frequency. The multipl...

Page 37 - Figure 11, and the recommended operating conditions table)

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 37 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 divide-by-two clock option (PLL disabled) The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two to generatethe internal machine cycle. The selection of the ...

Page 41 - memory write

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 41 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 memory and parallel I/O interface timing (continued) switching characteristics over recommended operating conditions for a memory write (MSTRB = 0) [H = 0.5 t c(CO) ] † (see Figure 14) PARAMETER MIN MAX...

Page 44 - parallel I/O port write

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 memory and parallel I/O interface timing (continued) switching characteristics over recommended operating conditions for a parallel I/O port write (IOSTRB = 0) [H = 0.5 t c(CO) ] † (see Figure 16) PARAM...

Page 45 - Figure 17. Memory Read With Externally Generated Wait States

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 45 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ready timing for externally generated wait states timing requirements for externally generated wait states [H = 0.5 t c(CO) ] † (see Figure 17, Figure 18, Figure 19, and Figure 20) MIN MAX UNIT tsu(RDY)...

Page 46 - ready timing for externally generated wait states (continued); Figure 18. Memory Write With Externally Generated Wait States

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ready timing for externally generated wait states (continued) MSC MSTRB READY D[15:0] A[19:0] CLKOUT tv(MSCH) th(RDY) Wait State Generatedby READY Wait States Generated Internally th(RDY)MSTRB tv(RDY)MS...

Page 47 - Figure 19. I/O Read With Externally Generated Wait States

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 47 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ready timing for externally generated wait states (continued) tsu(RDY) MSC IOSTRB READY A[19:0] CLKOUT tv(MSCH) th(RDY) Wait State Generatedby READY Wait States Generated Internally tv(RDY)IOSTRB tv(MSC...

Page 48 - Figure 20. I/O Write With Externally Generated Wait States

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ready timing for externally generated wait states (continued) IOSTRB MSC READY D[15:0] A[19:0] CLKOUT th(RDY) Wait State Generatedby READY Wait States Generated Internally tv(RDY)IOSTRB tsu(RDY) tv(MSCH...

Page 51 - Figure 22. Reset and BIO Timings; Figure 23. Interrupt Timing

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 51 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 reset, BIO, interrupt, and MP/MC timings (continued) BIO CLKOUT RS, INTn, NMI X2/CLKIN th(BIO) th(RS) tsu(INT) tw(BIO)S tsu(BIO) tw(RSL) tsu(RS) Figure 22. Reset and BIO Timings INTn, NMI CLKOUT th(INT)...

Page 52 - Figure 25. IAQ and IACK Timings

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 instruction acquisition (IAQ), interrupt acknowledge (IACK), external flag (XF), and TOUT timings switching characteristics over recommended operating conditions for IAQ and IACK[H = 0.5 t c(CO) ] (see ...

Page 53 - Figure 27. TOUT Timing

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 53 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 instruction acquisition (IAQ), interrupt acknowledge (IACK), external flag (XF), and TOUT timings(continued) switching characteristics over recommended operating conditions for XF and TOUT[H = 0.5 t c(C...

Page 54 - multichannel buffered serial port timing

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 54 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 multichannel buffered serial port timing timing requirements for McBSP [H=0.5t c(CO) ] † (see Figure 28 and Figure 29) MIN MAX UNIT tc(BCKRX) Cycle time, BCLKR/X BCLKR/X ext 4H ns tw(BCKRX) Pulse durati...

Page 55 - multichannel buffered serial port timing (continued); Figure 28. McBSP Receive Timings

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 55 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 multichannel buffered serial port timing (continued) (n–2) Bit (n–1) (n–3) (n–2) Bit (n–1) (n–4) (n–3) (n–2) Bit (n–1) th(BCKRL–BDRV) tsu(BDRV–BCKRL) th(BCKRL–BDRV) tsu(BDRV–BCKRL) tsu(BDRV–BCKRL) th(BC...

Page 61 - HPI8 timing

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 61 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 HPI8 timing switching characteristics over recommended operating conditions †‡§¶ [H = 0.5t c(CO) ] (see Figure 35, Figure 36, Figure 37, and Figure 38) PARAMETER MIN MAX UNIT ten(DSL-HD) Enable time, HD...

Page 62 - timing requirements

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 62 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 HPI8 timing (continued) timing requirements †‡§ (see Figure 35, Figure 36, Figure 37, and Figure 38) MIN MAX UNIT tsu(HBV-DSL) Setup time, HBIL and HAD valid before DS low or before HAS low¶# 5 ns th(DS...

Page 65 - MECHANICAL DATA; PLASTIC QUAD FLATPACK

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 65 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MECHANICAL DATA PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK 4040147/C 10/96 0,27 72 0,17 37 73 0,13 NOM 0,25 0,750,45 0,05 MIN 36 Seating Plane Gage Plane 108 109 144 SQ SQ 22,2021,80 1 19,80 17,50 TYP 20,2...

Page 66 - PLASTIC BALL GRID ARRAY PACKAGE

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000 66 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MECHANICAL DATA GGU (S-PBGA-N144) PLASTIC BALL GRID ARRAY PACKAGE 0,80 0,10 M 0,08 0,80 9,60 TYP 12 13 10 11 8 9 6 7 N M K L J H 4 2 3 F E C B D A 1 G 5 Seating Plane 4073221-2/B 08/00 SQ 11,90 12,10 0,...

Page 67 - PACKAGING INFORMATION; PACKAGE OPTION ADDENDUM

PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) DSG5402PGE100 ACTIVE LQFP PGE 144 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YR TMS320VC5402GGU100 ACTIVE BGA GGU 144 160 TBD SNPB Level-3-220C-...