Page 3 - Contents
Contents Preface .............................................................................................................................. 10 1 Introduction .............................................................................................................. 11 1.1 Purpose of the Perip...
Page 10 - Read This First; About This Manual; This document uses the following conventions.; Related Documentation From Texas Instruments; . Tip: Enter the literature number in the search box
Preface SPRU941A – April 2007 Read This First About This Manual This document provides a functional description of the Ethernet Media Access Controller (EMAC) andphysical layer (PHY) device Management Data Input/Output (MDIO) module integrated in theTMS320DM643x Digital Media Processor (DMP). Includ...
Page 11 - Introduction; Purpose of the Peripheral; The EMAC/MDIO has the following features:
1 Introduction 1.1 Purpose of the Peripheral 1.2 Features User's Guide SPRU941A – April 2007 Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO) This document provides a functional description of the Ethernet Media Access Controller (EMAC) andphysical layer (PHY) device Mana...
Page 12 - Functional Block Diagram; Figure 1; Figure 1. EMAC and MDIO Block Diagram
www.ti.com 1.3 Functional Block Diagram Configuration bus DMA memory transfer controller Peripheral bus EMAC control module EMAC module MDIO module MII bus MDIO bus EMAC/MDIO interrupt DSP interrupt controller Introduction Figure 1 shows the three main functional modules of the EMAC/MDIO peripheral:...
Page 13 - Industry Standard(s) Compliance Statement; Clock Control; Peripheral Architecture; 2 bits in size. Data can be written to and
www.ti.com 1.4 Industry Standard(s) Compliance Statement 2 Peripheral Architecture 2.1 Clock Control 2.2 Memory Map 2.3 Signal Descriptions Peripheral Architecture The EMAC peripheral conforms to the IEEE 802.3 standard, describing the Carrier Sense Multiple Accesswith Collision Detection (CSMA/CD) ...
Page 14 - Figure 2. Typical Ethernet Configuration
www.ti.com MTCLK MTXD(3−0) MTXEN MCOL MCRS MRCLK MRXD(3−0) MRXDV MRXER MDCLK MDIO Physical layer device (PHY) System core Transformer 2.5 MHz or 25 MHz RJ−45 EMAC MDIO Peripheral Architecture Figure 2. Typical Ethernet Configuration Table 1. EMAC and MDIO Signals Signal Type Description MTCLK I Tran...
Page 15 - Ethernet Protocol Overview; Ethernet Frame Format; Figure 3; Figure 3. Ethernet Frame Format
www.ti.com 2.4 Ethernet Protocol Overview 2.4.1 Ethernet Frame Format Preamble SFD Destination Source Len Data 7 1 6 6 2 46−1500 4 FCS Number of bytes Legend: SFD=Start Frame Delimeter; FCS=Frame Check Sequence (CRC) Peripheral Architecture A brief overview of the Ethernet protocol is given in the f...
Page 16 - Ethernet’s Multiple Access Protocol; Programming Interface; Packet Buffer Descriptors; the frame in a buffer.; Figure 4. Basic Descriptor Format
www.ti.com 2.4.2 Ethernet’s Multiple Access Protocol 2.5 Programming Interface 2.5.1 Packet Buffer Descriptors Peripheral Architecture Nodes in an Ethernet Local Area Network are interconnected by a broadcast channel, as a result, whenan EMAC port transmits a frame, all the adapters on the local net...
Page 17 - Table 3. Basic Descriptor Description; Figure 5. Typical Descriptor Linked List
www.ti.com SOP | EOP 60 0 60 pBuffer pNext Packet A 60 bytes 0 SOP Fragment 1 Packet B 512 1514 pBuffer pNext 512 bytes EOP 0 0 −−− Packet B Fragment 3 500 bytes 502 pBuffer −−− 500 pNext −−− pBuffer pNext Packet B Fragment 2 502 bytes SOP | EOP 0 1514 bytes Packet C 1514 pBuffer pNext (NULL) 1514 P...
Page 18 - Transmit and Receive Descriptor Queues; TXnHDP - Transmit Channel n DMA Head Descriptor Pointer Register
www.ti.com 2.5.2 Transmit and Receive Descriptor Queues Peripheral Architecture The EMAC module processes descriptors in linked list chains as discussed in Section 2.5.1 . The lists controlled by the EMAC are maintained by the application software through the use of the head descriptorpointer regist...
Page 19 - Transmit and Receive EMAC Interrupts; , using the linked list
www.ti.com 2.5.3 Transmit and Receive EMAC Interrupts Peripheral Architecture The EMAC processes descriptors in linked list chains as discussed in Section 2.5.1 , using the linked list queue mechanism discussed in Section 2.5.2 . The EMAC synchronizes descriptor list processing through the use of in...
Page 20 - Transmit Buffer Descriptor Format; Figure 6; Figure 6. Transmit Buffer Descriptor Format; Example 1. Transmit Buffer Descriptor in C Structure Format
www.ti.com 2.5.4 Transmit Buffer Descriptor Format Peripheral Architecture A transmit (TX) buffer descriptor ( Figure 6 ) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 1 shows the transmit buffer descriptor describe...
Page 21 - The range of legal values for this field is 0 to (Buffer Length – 1).
www.ti.com 2.5.4.1 Next Descriptor Pointer 2.5.4.2 Buffer Pointer 2.5.4.3 Buffer Offset 2.5.4.4 Buffer Length 2.5.4.5 Packet Length 2.5.4.6 Start of Packet (SOP) Flag Peripheral Architecture The next descriptor pointer points to the 32-bit word aligned memory address of the next buffer descriptorin ...
Page 23 - Receive Buffer Descriptor Format; Next Descriptor Pointer; Figure 7; Figure 7. Receive Buffer Descriptor Format
www.ti.com 2.5.5 Receive Buffer Descriptor Format 2.5.5.1 Next Descriptor Pointer 2.5.5.2 Buffer Pointer Peripheral Architecture A receive (RX) buffer descriptor ( Figure 7 ) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Ex...
Page 24 - Buffer Offset; Example 2. Receive Buffer Descriptor in C Structure Format
www.ti.com 2.5.5.3 Buffer Offset Peripheral Architecture Example 2. Receive Buffer Descriptor in C Structure Format /* // EMAC Descriptor // // The following is the format of a single buffer descriptor // on the EMAC. */ typedef struct _EMAC_Desc { struct _EMAC_Desc *pNext; /* Pointer to next descri...
Page 25 - This 16-bit field is used for two purposes:
www.ti.com 2.5.5.4 Buffer Length 2.5.5.5 Packet Length 2.5.5.6 Start of Packet (SOP) Flag 2.5.5.7 End of Packet (EOP) Flag 2.5.5.8 Ownership (OWNER) Flag 2.5.5.9 End of Queue (EOQ) Flag Peripheral Architecture This 16-bit field is used for two purposes: • Before the descriptor is first placed on the...
Page 27 - EMAC Control Module; Internal Memory; The basic functions of the EMAC control module (; Figure 8. EMAC Control Module Block Diagram
www.ti.com 2.5.5.21 No Match (NOMATCH) Flag 2.6 EMAC Control Module Arbiter and bus switches CPU DMA Controllers 8K byte descriptor memory Configuration registers Interrupt logic Single interruptto CPU EMAC interrupts MDIO interrupts Configuration bus Transmit and Receive 2.6.1 Internal Memory 2.6.2...
Page 28 - Interrupt Control; MDIO Module; MDIO Module Components; Figure 9
www.ti.com 2.6.3 Interrupt Control 2.7 MDIO Module 2.7.1 MDIO Module Components Peripheral Architecture The EMAC control module combines multiple interrupt conditions generated by the EMAC and MDIOmodules into a single interrupt signal that is mapped to a CPU interrupt via the CPU interrupt controll...
Page 29 - Figure 9. MDIO Module Block Diagram
www.ti.com EMAC control module Control registers and logic PHY monitoring Peripheral clock MDIO clock generator USERINT MDIO interface polling PHY MDCLK MDIO LINKINT Configuration bus 2.7.1.1 MDIO Clock Generator 2.7.1.2 Global PHY Detection and Link State Monitoring 2.7.1.3 Active PHY Monitoring 2....
Page 30 - MDIO Module Operational Overview
www.ti.com 2.7.2 MDIO Module Operational Overview Peripheral Architecture The MDIO module implements the 802.3 serial management interface to interrogate and control anEthernet PHY, using a shared two-wired bus. It separately performs autodetection and records the currentlink status of up to 32 PHYs...
Page 31 - PHY and PHY register you want to write.
www.ti.com 2.7.2.1 Initializing the MDIO Module 2.7.2.2 Writing Data To a PHY Register 2.7.2.3 Reading Data From a PHY Register Peripheral Architecture The following steps are performed by the application software or device driver to initialize the MDIOdevice: 1. Configure the PREAMBLE and CLKDIV bi...
Page 32 - Example of MDIO Register Access Code; Start the process of reading a PHY register
www.ti.com 2.7.2.4 Example of MDIO Register Access Code Peripheral Architecture The MDIO module uses the MDIO user access register (USERACCESSn) to access the PHY controlregisters. Software functions that implement the access process may simply be the following four macros: • PHYREG_read( regadr, ph...
Page 33 - EMAC Module; EMAC Module Components; Receive DMA Engine; Statistics logic; Figure 10. EMAC Module Block Diagram
www.ti.com 2.8 EMAC Module 2.8.1 EMAC Module Components Clock and reset logic Receive DMA engine Interrupt controller Transmit DMA engine Control registers Configuration bus EMAC control module Configuration bus RAM State FIFO Receive FIFO Transmit MAC transmitter Statistics receiver MAC SYNC MII ad...
Page 34 - EMAC Module Operational Overview
www.ti.com 2.8.1.4 Transmit DMA Engine 2.8.1.5 Transmit FIFO 2.8.1.6 MAC Transmitter 2.8.1.7 Statistics Logic 2.8.1.8 State RAM 2.8.1.9 EMAC Interrupt Controller 2.8.1.10 Control Registers and Logic 2.8.1.11 Clock and Reset Logic 2.8.2 EMAC Module Operational Overview Peripheral Architecture The tra...
Page 35 - Data Reception; Receive Control; Collision-based flow control for half-duplex mode
www.ti.com 2.9 Media Independent Interface (MII) 2.9.1 Data Reception 2.9.1.1 Receive Control 2.9.1.2 Receive Inter-Frame Interval 2.9.1.3 Receive Flow Control Peripheral Architecture The EMAC module operates independently of the CPU. It is configured and controlled by its register setmapped into de...
Page 36 - Collision-Based Receive Buffer Flow Control; The EMAC transmits pause frames as described below:
www.ti.com Peripheral Architecture In either case, receive flow control prevents frame reception by issuing the flow control appropriate for thecurrent mode of operation. Receive flow control prevents reception of frames on the EMAC until all of thetriggering conditions clear, at which time frames m...
Page 37 - Data Transmission; Transmit Control
www.ti.com 2.9.2 Data Transmission 2.9.2.1 Transmit Control 2.9.2.2 CRC Insertion 2.9.2.3 Adaptive Performance Optimization (APO) 2.9.2.4 Interpacket-Gap (IPG) Enforcement 2.9.2.5 Back Off Peripheral Architecture The EMAC passes data to the PHY from the transmit FIFO (when enabled). Data is synchron...
Page 38 - Transmit Flow Control
www.ti.com 2.9.2.6 Transmit Flow Control 2.9.2.7 Speed, Duplex, and Pause Frame Support Peripheral Architecture Incoming pause frames are acted upon, when enabled, to prevent the EMAC from transmitting any furtherframes. Incoming pause frames are only acted upon when the FULLDUPLEX and TXFLOWEN bits...
Page 39 - Packet Receive Operation; Receive DMA Host Configuration; To configure the receive DMA for operation the host must:
www.ti.com 2.10 Packet Receive Operation 2.10.1 Receive DMA Host Configuration 2.10.2 Receive Channel Enabling 2.10.3 Receive Address Matching Peripheral Architecture To configure the receive DMA for operation the host must: • Initialize the receive addresses. • Initialize the receive channel n DMA ...
Page 41 - Table 4
www.ti.com 2.10.7 Receive Frame Classification 2.10.8 Promiscuous Receive Mode Peripheral Architecture Received frames are proper (good) frames, if they are between 64 bytes and the value in the receivemaximum length register (RXMAXLEN) bytes in length (inclusive) and contain no code, align, or CRCe...
Page 42 - Table 4. Receive Frame Treatment Summary
www.ti.com Peripheral Architecture Table 4. Receive Frame Treatment Summary Address Match RXCAFEN RXCEFEN RXCMFEN RXCSFEN Receive Frame Treatment 0 0 X X X No frames transferred. 0 1 0 0 0 Proper frames transferred to promiscuous channel. 0 1 0 0 1 Proper/undersized data frames transferred topromisc...
Page 43 - Receive Overrun; The types of receive overrun are:; Table 5. Middle of Frame Overrun Treatment
www.ti.com 2.10.9 Receive Overrun Peripheral Architecture The types of receive overrun are: • FIFO start of frame overrun (FIFO_SOF) • FIFO middle of frame overrun (FIFO_MOF) • DMA start of frame overrun (DMA_SOF) • DMA middle of frame overrun (DMA_MOF) The statistics counters used to track these ty...
Page 44 - Packet Transmit Operation; Transmit DMA Host Configuration; Receive and Transmit Latency
www.ti.com 2.11 Packet Transmit Operation 2.11.1 Transmit DMA Host Configuration 2.11.2 Transmit Channel Teardown 2.12 Receive and Transmit Latency Peripheral Architecture The transmit DMA is an eight channel interface. Priority between the eight queues may be either fixed orround-robin as selected ...
Page 45 - Software Reset Considerations; PSC, see the TMS320DM643x DMP DSP Subsystem Reference Guide (
www.ti.com 2.13 Transfer Node Priority 2.14 Reset Considerations 2.14.1 Software Reset Considerations Peripheral Architecture Latency to system’s internal and external RAM can be controlled through the use of the transfer nodepriority allocation register available at the device level. Latency to des...
Page 46 - Initializing the EMAC and MDIO modules.
www.ti.com 2.14.2 Hardware Reset Considerations 2.15 Initialization 2.15.1 Enabling the EMAC/MDIO Peripheral 2.15.2 EMAC Control Module Initialization Peripheral Architecture When a hardware reset occurs, the EMAC peripheral has its register values reset and all the componentsreturn to their default...
Page 47 - MDIO Module Initialization; Example 4. EMAC Control Module Initialization Code; Example 5
www.ti.com 2.15.3 MDIO Module Initialization Peripheral Architecture Example 4. EMAC Control Module Initialization Code Uint32 tmpval ; /* // Globally disable EMAC/MDIO interrupts in the control module */ CSL_FINST( ECTL_REGS->EWCTL, ECTL_EWCTL_INTEN, DISABLE ) ; /* Wait about 100 cycles */ for( ...
Page 48 - EMAC Module Initialization; TXEN bit in TXCONTROL. Then set the GMIIEN bit in MACCONTROL.
www.ti.com 2.15.4 EMAC Module Initialization Peripheral Architecture The EMAC module is used to send and receive data packets over the network. This is done bymaintaining up to eight transmit and receive descriptor queues. The EMAC module configuration mustalso be kept up-to-date based on PHY negoti...
Page 49 - Interrupt Support; EMAC Module Interrupt Events and Requests; Transmit Packet Completion Interrupts; The EMAC module generates 18 interrupt events:
www.ti.com 2.16 Interrupt Support 2.16.1 EMAC Module Interrupt Events and Requests 2.16.1.1 Transmit Packet Completion Interrupts 2.16.1.2 Receive Packet Completion Interrupts Peripheral Architecture The EMAC module generates 18 interrupt events: • TXPENDn: Transmit packet completion interrupt for t...
Page 51 - MDIO Module Interrupt Events and Requests; Link Change Interrupt; Proper Interrupt Processing; The MDIO module generates two interrupt events:
www.ti.com 2.16.2 MDIO Module Interrupt Events and Requests 2.16.2.1 Link Change Interrupt 2.16.2.2 User Access Completion Interrupt 2.16.3 Proper Interrupt Processing 2.16.4 Interrupt Multiplexing Peripheral Architecture The MDIO module generates two interrupt events: • LINKINT: Serial interface li...
Page 52 - Table 6; Emulation suspend has not been tested.; Table 6. Emulation Control
www.ti.com 2.17 Power Management 2.18 Emulation Considerations Peripheral Architecture Each of the three main components of the EMAC peripheral can independently be placed inreduced-power modes to conserve power during periods of low activity. The power management of theEMAC peripheral is controlled...
Page 53 - EMAC Control Module Interrupt Control Register (EWCTL); EMAC Control Module Registers; Table 7; Table 7. EMAC Control Module Registers; The EWCTL is shown in; Figure 11. EMAC Control Module Interrupt Control Register (EWCTL)
www.ti.com 3 EMAC Control Module Registers 3.1 EMAC Control Module Interrupt Control Register (EWCTL) EMAC Control Module Registers Table 7 lists the memory-mapped registers for the EMAC control module. See the device-specific data manual for the memory address of these registers. Table 7. EMAC Cont...
Page 54 - EMAC Control Module Interrupt Timer Count Register (EWINTTCNT); The EWINTTCNT is shown in
www.ti.com 3.2 EMAC Control Module Interrupt Timer Count Register (EWINTTCNT) EMAC Control Module Registers The EMAC control module interrupt timer count register (EWINTTCNT) is used to control the generationof back-to-back interrupts from the EMAC and MDIO modules. The value of this timer count is ...
Page 55 - MDIO Registers; for the memory address of these registers.
www.ti.com 4 MDIO Registers 4.1 MDIO Version Register (VERSION) MDIO Registers Table 10 lists the memory-mapped registers for the MDIO module. See the device-specific data manual for the memory address of these registers. Table 10. Management Data Input/Output (MDIO) Registers Offset Acronym Registe...
Page 56 - The MDIO control register (CONTROL) is shown in
www.ti.com 4.2 MDIO Control Register (CONTROL) MDIO Registers The MDIO control register (CONTROL) is shown in Figure 14 and described in Table 12 . Figure 14. MDIO Control Register (CONTROL) 31 30 29 28 24 23 21 20 19 18 17 16 IDLE ENABLE Rsvd HIGHEST_USER_CHANNEL Reserved PREAMBLE FAULT FAULTENB Re...
Page 57 - The PHY acknowledge status register (ALIVE) is shown in
www.ti.com 4.3 PHY Acknowledge Status Register (ALIVE) 4.4 PHY Link Status Register (LINK) MDIO Registers The PHY acknowledge status register (ALIVE) is shown in Figure 15 and described in Table 13 . Figure 15. PHY Acknowledge Status Register (ALIVE) 31 16 ALIVE R/WC-0 15 0 ALIVE R/WC-0 LEGEND: R/W ...
Page 58 - and; Field Descriptions
www.ti.com 4.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) MDIO Registers The MDIO link status change interrupt (unmasked) register (LINKINTRAW) is shown in Figure 17 and described in Table 15 . Figure 17. MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) 31 1...
Page 60 - and described in
www.ti.com 4.7 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) MDIO Registers The MDIO user command complete interrupt (unmasked) register (USERINTRAW) is shown in Figure 19 and described in Table 17 . Figure 19. MDIO User Command Complete Interrupt (Unmasked) Register (USERINT...
Page 64 - The MDIO user access register 0 (USERACCESS0) is shown in
www.ti.com 4.11 MDIO User Access Register 0 (USERACCESS0) MDIO Registers The MDIO user access register 0 (USERACCESS0) is shown in Figure 23 and described in Table 21 . Figure 23. MDIO User Access Register 0 (USERACCESS0) 31 30 29 28 26 25 21 20 16 GO WRITE ACK Reserved REGADR PHYADR R/WS-0 R/W-0 R/...
Page 65 - The MDIO user PHY select register 0 (USERPHYSEL0) is shown in
www.ti.com 4.12 MDIO User PHY Select Register 0 (USERPHYSEL0) MDIO Registers The MDIO user PHY select register 0 (USERPHYSEL0) is shown in Figure 24 and described in Table 22 . Figure 24. MDIO User PHY Select Register 0 (USERPHYSEL0) 31 16 Reserved R-0 15 8 7 6 5 4 0 Reserved LINKSEL LINKINTENB Rsvd...
Page 66 - The MDIO user access register 1 (USERACCESS1) is shown in
www.ti.com 4.13 MDIO User Access Register 1 (USERACCESS1) MDIO Registers The MDIO user access register 1 (USERACCESS1) is shown in Figure 25 and described in Table 23 . Figure 25. MDIO User Access Register 1 (USERACCESS1) 31 30 29 28 26 25 21 20 16 GO WRITE ACK Reserved REGADR PHYADR R/WS-0 R/W-0 R/...
Page 67 - The MDIO user PHY select register 1 (USERPHYSEL1) is shown in
www.ti.com 4.14 MDIO User PHY Select Register 1 (USERPHYSEL1) MDIO Registers The MDIO user PHY select register 1 (USERPHYSEL1) is shown in Figure 26 and described in Table 24 . Figure 26. MDIO User PHY Select Register 1 (USERPHYSEL1) 31 16 Reserved R-0 15 8 7 6 5 4 0 Reserved LINKSEL LINKINTENB Rsvd...
Page 68 - Ethernet Media Access Controller (EMAC) Registers; memory address of these registers.
www.ti.com 5 Ethernet Media Access Controller (EMAC) Registers Ethernet Media Access Controller (EMAC) Registers Table 25 lists the memory-mapped registers for the EMAC. See the device-specific data manual for the memory address of these registers. Table 25. Ethernet Media Access Controller (EMAC) R...
Page 71 - Transmit Identification and Version Register (TXIDVER); Figure 27. Transmit Identification and Version Register (TXIDVER); The transmit control register (TXCONTROL) is shown in
www.ti.com 5.1 Transmit Identification and Version Register (TXIDVER) 5.2 Transmit Control Register (TXCONTROL) Ethernet Media Access Controller (EMAC) Registers The transmit identification and version register (TXIDVER) is shown in Figure 27 and described in Table 26 . Figure 27. Transmit Identific...
Page 72 - The transmit teardown register (TXTEARDOWN) is shown in
www.ti.com 5.3 Transmit Teardown Register (TXTEARDOWN) Ethernet Media Access Controller (EMAC) Registers The transmit teardown register (TXTEARDOWN) is shown in Figure 29 and described in Table 28 . Figure 29. Transmit Teardown Register (TXTEARDOWN) 31 16 Reserved R-0 15 3 2 0 Reserved TXTDNCH R-0 R...
Page 73 - Receive Identification and Version Register (RXIDVER); Figure 30. Receive Identification and Version Register (RXIDVER); The receive control register (RXCONTROL) is shown in; Table 30. Receive Control Register (RXCONTROL) Field Descriptions
www.ti.com 5.4 Receive Identification and Version Register (RXIDVER) 5.5 Receive Control Register (RXCONTROL) Ethernet Media Access Controller (EMAC) Registers The receive identification and version register (RXIDVER) is shown in Figure 30 and described in Table 29 . Figure 30. Receive Identificatio...
Page 74 - The receive teardown register (RXTEARDOWN) is shown in
www.ti.com 5.6 Receive Teardown Register (RXTEARDOWN) Ethernet Media Access Controller (EMAC) Registers The receive teardown register (RXTEARDOWN) is shown in Figure 32 and described in Table 31 . Figure 32. Receive Teardown Register (RXTEARDOWN) 31 16 Reserved R-0 15 3 2 0 Reserved RXTDNCH R-0 R/W-...
Page 77 - Transmit Interrupt Mask Set Register (TXINTMASKSET); Figure 35. Transmit Interrupt Mask Set Register (TXINTMASKSET)
www.ti.com 5.9 Transmit Interrupt Mask Set Register (TXINTMASKSET) Ethernet Media Access Controller (EMAC) Registers The transmit interrupt mask set register (TXINTMASKSET) is shown in Figure 35 and described in Table 34 . Figure 35. Transmit Interrupt Mask Set Register (TXINTMASKSET) 31 16 Reserved...
Page 79 - The MAC input vector register (MACINVECTOR) is shown in
www.ti.com 5.11 MAC Input Vector Register (MACINVECTOR) Ethernet Media Access Controller (EMAC) Registers The MAC input vector register (MACINVECTOR) is shown in Figure 37 and described in Table 36 . Figure 37. MAC Input Vector Register (MACINVECTOR) 31 30 29 18 17 16 USERINT LINKINT Reserved HOSTPE...
Page 82 - The receive interrupt mask set register (RXINTMASKSET) is shown in; Figure 40. Receive Interrupt Mask Set Register (RXINTMASKSET)
www.ti.com 5.14 Receive Interrupt Mask Set Register (RXINTMASKSET) Ethernet Media Access Controller (EMAC) Registers The receive interrupt mask set register (RXINTMASKSET) is shown in Figure 40 and described in Table 39 . Figure 40. Receive Interrupt Mask Set Register (RXINTMASKSET) 31 16 Reserved R...
Page 83 - Figure 41. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)
www.ti.com 5.15 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Ethernet Media Access Controller (EMAC) Registers The receive interrupt mask clear register (RXINTMASKCLEAR) is shown in Figure 41 and described in Table 40 . Figure 41. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) 31 1...
Page 85 - The MAC interrupt mask set register (MACINTMASKSET) is shown in; Figure 45. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)
www.ti.com 5.18 MAC Interrupt Mask Set Register (MACINTMASKSET) 5.19 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Ethernet Media Access Controller (EMAC) Registers The MAC interrupt mask set register (MACINTMASKSET) is shown in Figure 44 and described in Table 43 . Figure 44. MAC Interrupt Ma...
Page 89 - The receive unicast enable set register (RXUNICASTSET) is shown in; Figure 47. Receive Unicast Enable Set Register (RXUNICASTSET)
www.ti.com 5.21 Receive Unicast Enable Set Register (RXUNICASTSET) Ethernet Media Access Controller (EMAC) Registers The receive unicast enable set register (RXUNICASTSET) is shown in Figure 47 and described in Table 46 . Figure 47. Receive Unicast Enable Set Register (RXUNICASTSET) 31 16 Reserved R...
Page 90 - The receive unicast clear register (RXUNICASTCLEAR) is shown in
www.ti.com 5.22 Receive Unicast Clear Register (RXUNICASTCLEAR) Ethernet Media Access Controller (EMAC) Registers The receive unicast clear register (RXUNICASTCLEAR) is shown in Figure 48 and described in Table 47 . Figure 48. Receive Unicast Clear Register (RXUNICASTCLEAR) 31 16 Reserved R-0 15 8 R...
Page 91 - The receive maximum length register (RXMAXLEN) is shown in
www.ti.com 5.23 Receive Maximum Length Register (RXMAXLEN) 5.24 Receive Buffer Offset Register (RXBUFFEROFFSET) Ethernet Media Access Controller (EMAC) Registers The receive maximum length register (RXMAXLEN) is shown in Figure 49 and described in Table 48 . Figure 49. Receive Maximum Length Registe...
Page 94 - The MAC control register (MACCONTROL) is shown in; Table 53. MAC Control Register (MACCONTROL) Field Descriptions
www.ti.com 5.28 MAC Control Register (MACCONTROL) Ethernet Media Access Controller (EMAC) Registers The MAC control register (MACCONTROL) is shown in Figure 54 and described in Table 53 . Figure 54. MAC Control Register (MACCONTROL) 31 16 Reserved R-0 15 14 13 12 11 10 9 8 Reserved RXOFFLENBLOCK RXO...
Page 96 - The MAC status register (MACSTATUS) is shown in
www.ti.com 5.29 MAC Status Register (MACSTATUS) Ethernet Media Access Controller (EMAC) Registers The MAC status register (MACSTATUS) is shown in Figure 55 and described in Table 54 . Figure 55. MAC Status Register (MACSTATUS) 31 30 24 23 20 19 18 16 IDLE Reserved TXERRCODE Rsvd TXERRCH R-0 R-0 R-0 ...
Page 98 - The emulation control register (EMCONTROL) is shown in; Table 56. FIFO Control Register (FIFOCONTROL) Field Descriptions
www.ti.com 5.30 Emulation Control Register (EMCONTROL) 5.31 FIFO Control Register (FIFOCONTROL) Ethernet Media Access Controller (EMAC) Registers The emulation control register (EMCONTROL) is shown in Figure 56 and described in Table 55 . Figure 56. Emulation Control Register (EMCONTROL) 31 16 Reser...
Page 99 - The MAC configuration register (MACCONFIG) is shown in
www.ti.com 5.32 MAC Configuration Register (MACCONFIG) 5.33 Soft Reset Register (SOFTRESET) Ethernet Media Access Controller (EMAC) Registers The MAC configuration register (MACCONFIG) is shown in Figure 58 and described in Table 57 . Figure 58. MAC Configuration Register (MACCONFIG) 31 24 23 16 TXC...
Page 100 - Figure 60. MAC Source Address Low Bytes Register (MACSRCADDRLO); and described; Figure 61. MAC Source Address High Bytes Register (MACSRCADDRHI)
www.ti.com 5.34 MAC Source Address Low Bytes Register (MACSRCADDRLO) 5.35 MAC Source Address High Bytes Register (MACSRCADDRHI) Ethernet Media Access Controller (EMAC) Registers The MAC source address low bytes register (MACSRCADDRLO) is shown in Figure 60 and described in Table 59 . Figure 60. MAC ...
Page 101 - The MAC hash address register 1 (MACHASH1) is shown in; Table 61. MAC Hash Address Register 1 (MACHASH1) Field Descriptions; The MAC hash address register 2 (MACHASH2) is shown in; Table 62. MAC Hash Address Register 2 (MACHASH2) Field Descriptions
www.ti.com 5.36 MAC Hash Address Register 1 (MACHASH1) 5.37 MAC Hash Address Register 2 (MACHASH2) Ethernet Media Access Controller (EMAC) Registers The MAC hash registers allow group addressed frames to be accepted on the basis of a hash functionof the address. The hash function creates a 6-bit dat...
Page 102 - The back off test register (BOFFTEST) is shown in; Table 63. Back Off Test Register (BOFFTEST) Field Descriptions; Figure 65. Transmit Pacing Algorithm Test Register (TPACETEST)
www.ti.com 5.38 Back Off Test Register (BOFFTEST) 5.39 Transmit Pacing Algorithm Test Register (TPACETEST) Ethernet Media Access Controller (EMAC) Registers The back off test register (BOFFTEST) is shown in Figure 64 and described in Table 63 . Figure 64. Back Off Random Number Generator Test Regist...
Page 103 - The receive pause timer register (RXPAUSE) is shown in
www.ti.com 5.40 Receive Pause Timer Register (RXPAUSE) 5.41 Transmit Pause Timer Register (TXPAUSE) Ethernet Media Access Controller (EMAC) Registers The receive pause timer register (RXPAUSE) is shown in Figure 66 and described in Table 65 . Figure 66. Receive Pause Timer Register (RXPAUSE) 31 16 R...
Page 105 - The MAC index register (MACINDEX) is shown in
www.ti.com 5.44 MAC Index Register (MACINDEX) Ethernet Media Access Controller (EMAC) Registers The MAC index register (MACINDEX) is shown in Figure 70 and described in Table 69 . Figure 70. MAC Index Register (MACINDEX) 31 16 Reserved R-0 15 3 2 0 Reserved MACINDEX R-0 R/W-0 LEGEND: R = Read only; ...
Page 108 - Network Statistics Registers; Good Receive Frames Register (RXGOODFRAMES); Figure 75. Statistics Register
www.ti.com 5.49 Network Statistics Registers 5.49.1 Good Receive Frames Register (RXGOODFRAMES) 5.49.2 Broadcast Receive Frames Register (RXBCASTFRAMES) 5.49.3 Multicast Receive Frames Register (RXMCASTFRAMES) Ethernet Media Access Controller (EMAC) Registers The EMAC has a set of statistics that re...
Page 114 - Was any size
www.ti.com 5.49.25 Transmit Carrier Sense Errors Register (TXCARRIERSENSE) 5.49.26 Transmit Octet Frames Register (TXOCTETS) 5.49.27 Transmit and Receive 64 Octet Frames Register (FRAME64) 5.49.28 Transmit and Receive 65 to 127 Octet Frames Register (FRAME65T127) 5.49.29 Transmit and Receive 128 to ...
Page 115 - Also counted in this statistic is:
www.ti.com 5.49.30 Transmit and Receive 256 to 511 Octet Frames Register (FRAME256T511) 5.49.31 Transmit and Receive 512 to 1023 Octet Frames Register (FRAME512T1023) 5.49.32 Transmit and Receive 1024 to RXMAXLEN Octet Frames Register (FRAME1024TUP) 5.49.33 Network Octet Frames Register (NETOCTETS) ...
Page 117 - Appendix A Glossary; portion of a single Ethernet frame on the wire.
www.ti.com Appendix A Glossary Broadcast MAC Address — A special Ethernet MAC address used to send data to all Ethernet devices on the local network. The broadcast address is FFh-FFh-FFh-FFh-FFh-FFh. The LSB ofthe first byte is odd, qualifying it as a group address; however, its value is reserved fo...
Page 118 - Appendix A; Port — Ethernet device.
www.ti.com Appendix A Link — The transmission path between any two instances of generic cabling. Multicast MAC Address — A class of MAC address that sends a packet to potentially more than one recipient. A group address is specified by setting the LSB of the first MAC address byte to 1.Thus, 01h-02h...
Page 119 - Appendix B Revision History
www.ti.com Appendix B Revision History Table B-1 lists the changes made since the previous version of this document. Table B-1. Document Revision History Reference Additions/Modifications/Deletions Section 2.4.1 Changed last sentence. Table 2 Changed Data field Bytes and Description. Table 25 Change...
Page 120 - IMPORTANT NOTICE
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.Customers should obtain the l...
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