Texas Instruments TMS320DM36X - Manuals

Configuration bus DMA memory transfer controller Peripheral bus EMAC control module EMAC module MDIO module MII bus MDIO bus EMAC/MDIO interrupts ARM interrupt controller 4 Introduction www.ti.com • Emulation support • Loopback mode 1.3 Functional Block Diagram Figure 1 shows the three main function...

www.ti.com Architecture The EMAC and MDIO interrupts are combined within the control module, so only the control moduleinterrupt needs to be monitored by the application software or device driver. The EMAC control modulecombines the EMAC and MDIO interrupts and generates 4 separate interrupts to the...

EMAC_TX_CLK EMAC_TXD(3-0) EMAC_TX_EN EMAC_COL EMAC_CRS EMAC_RX_CLK EMAC_RXD(3-0) EMAC_RX_DV MRXER MDCLK MDIO Physical layer device (PHY) System core Transformer 2.5 MHz, 25 MHz RJ-45 EMAC MDIO _ Architecture www.ti.com 2.2 Memory Map The EMAC peripheral includes internal memory that is used to hold ...

www.ti.com Architecture Table 1. EMAC and MDIO Signals for MII Interface Signal Type Description EMAC_TX_CLK I Transmit clock (EMAC_TX_CLK). The transmit clock is a continuous clock that provides the timingreference for transmit operations. The EMAC_TXD and EMAC_TX_EN signals are tied to this clock....

Preamble SFD Destination Source Len Data 7 1 6 6 2 46−1500 4 FCS Number of bytes Legend: SFD=Start Frame Delimeter; FCS=Frame Check Sequence (CRC) Architecture www.ti.com 2.5 Ethernet Protocol Overview Ethernet provides an unreliable, connection-less service to a networking application. A brief over...

www.ti.com Architecture 2.5.2 Ethernet’s Multiple Access Protocol Nodes in an Ethernet Local Area Network are interconnected by a broadcast channel, as a result, whenan EMAC port transmits a frame, all the adapters on the local network receive the frame. Carrier SenseMultiple Access with Collision D...

SOP | EOP 60 0 60 pBuffer pNext Packet A 60 bytes 0 SOP Fragment 1 Packet B 512 1514 pBuffer pNext 512 bytes EOP 0 0 −−− Packet B Fragment 3 500 bytes 502 pBuffer −−− 500 pNext −−− pBuffer pNext Packet B Fragment 2 502 bytes SOP | EOP 0 1514 bytes Packet C 1514 pBuffer pNext (NULL) 1514 Architecture...

www.ti.com Architecture 2.6.2 Transmit and Receive Descriptor Queues The EMAC module processes descriptors in linked list chains as discussed in Section 2.6.1 . The lists controlled by the EMAC are maintained by the application software through the use of the head descriptorpointer registers (HDP). ...

Architecture www.ti.com 2.6.3 Transmit and Receive EMAC Interrupts The EMAC processes descriptors in linked list chains as discussed in Section 2.6.1 , using the linked list queue mechanism discussed in Section 2.6.2 . The EMAC synchronizes descriptor list processing through the use of interrupts to...

www.ti.com Architecture 2.6.4 Transmit Buffer Descriptor Format A transmit (TX) buffer descriptor ( Figure 6 ) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 1 shows the transmit buffer descriptor described by a C st...

Architecture www.ti.com 2.6.4.1 Next Descriptor Pointer The next descriptor pointer points to the 32-bit word aligned memory address of the next buffer descriptorin the transmit queue. This pointer is used to create a linked list of buffer descriptors. If the value of thispointer is zero, then the c...

Architecture www.ti.com 2.6.5 Receive Buffer Descriptor Format A receive (RX) buffer descriptor ( Figure 7 ) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 2 shows the receive buffer descriptor described by a C struc...

www.ti.com Architecture Example 2. Receive Buffer Descriptor in C Structure Format /* // EMAC Descriptor // // The following is the format of a single buffer descriptor // on the EMAC. */ typedef struct _EMAC_Desc { struct _EMAC_Desc *pNext; /* Pointer to next descriptor in chain */ Uint8 *pBuffer; ...

Architecture www.ti.com 2.6.5.4 Buffer Length This 16-bit field is used for two purposes:• Before the descriptor is first placed on the receive queue by the application software, the buffer lengthfield is first initialized by the software to have the physical size of the empty data buffer pointed to...

Arbiter and bus switches CPU DMA Controllers 8K byte descriptor memory Configuration registers Interrupt control and pacing logic EMAC interrupts MDIO interrupts Configuration bus Transmit and Receive 4 interruptsto ARM Architecture www.ti.com 2.7 EMAC Control Module The basic functions of the EMAC ...

www.ti.com Architecture 2.7.3 Interrupt Control The EMAC control module combines multiple interrupt conditions generated by the EMAC and MDIOmodules into four separate interrupt signals that are mapped to a CPU interrupt via the CPU interruptcontroller. The four separate sources of interrupt can be ...

Architecture www.ti.com 2.7.3.3 Receive Threshold Pulse Interrupt The EMAC control module receives the eight individual receive threshold interrupts originating from theEMAC module, one for each of the eight channels, and combines them into a single receive thresholdpulse interrupt to the CPU. This ...

EMAC control module Control registers and logic PHY monitoring Peripheral clock MDIO clock generator USERINT MDIO interface polling PHY MDCLK MDIO LINKINT Configuration bus www.ti.com Architecture 2.8 MDIO Module The MDIO module is used to manage up to 32 physical layer (PHY) devices connected to th...

Architecture www.ti.com 2.8.1.3 Active PHY Monitoring Once a PHY candidate has been selected for use, the MDIO module transparently monitors its link stateby reading the MDIO PHY link status register (LINK). Link change events are stored on the MDIO deviceand can optionally interrupt the CPU. This a...

www.ti.com Architecture 2.8.2.1 Initializing the MDIO Module The following steps are performed by the application software or device driver to initialize the MDIOdevice: 1. Configure the PREAMBLE and CLKDIV bits in the MDIO control register (CONTROL).2. Enable the MDIO module by setting the ENABLE b...

Architecture www.ti.com 2.8.2.4 Example of MDIO Register Access Code The MDIO module uses the MDIO user access register (USERACCESSn) to access the PHY controlregisters. Software functions that implement the access process may simply be the following four macros: Start the process of reading a PHY r...

Clock and reset logic Receive DMA engine Interrupt controller Transmit DMA engine Control registers Configuration bus EMAC control module Configuration bus RAM State FIFO Receive FIFO Transmit MAC transmitter Statistics receiver MAC SYNC www.ti.com Architecture 2.9 EMAC Module This section discusses...

www.ti.com Architecture 2.9.2 EMAC Module Operational Overview After reset, initialization, and configuration, the application software running on the host may initiatetransmit operations. Transmit operations are initiated by host writes to the appropriate transmit channelhead descriptor pointer con...

Architecture www.ti.com 2.10 Media Independent Interface (MII) The following sections discuss the operation of the Media Independent Interface (MII) in 10 Mbps and100 Mbps mode. An IEEE 802.3 compliant Ethernet MAC controls the interface. 2.10.1 Data Reception 2.10.1.1 Receive Control Data received ...

www.ti.com Architecture 2.10.1.3.1 Collision-Based Receive Buffer Flow Control Collision-based receive buffer flow control provides a means of preventing frame reception when theEMAC is operating in half-duplex mode (the FULLDUPLEX bit is cleared in MACCONTROL). Whenreceive flow control is enabled a...

Architecture www.ti.com 2.10.2 Data Transmission The EMAC passes data to the PHY from the transmit FIFO (when enabled). Data is synchronized to thetransmit clock rate. Transmission begins when there are TXCELLTHRESH cells of 64 bytes each, or acomplete packet, in the FIFO. 2.10.2.1 Transmit Control ...

www.ti.com Architecture 2.10.2.6 Transmit Flow Control Incoming pause frames are acted upon, when enabled, to prevent the EMAC from transmitting any furtherframes. Incoming pause frames are only acted upon when the FULLDUPLEX and TXFLOWEN bits in theMAC control register (MACCONTROL) are set. Pause f...

Architecture www.ti.com 2.11 Packet Receive Operation 2.11.1 Receive DMA Host Configuration To configure the receive DMA for operation the host must: • Initialize the receive addresses. • Initialize the receive channel n DMA head descriptor pointer registers (RXnHDP) to 0. • Write the MAC address ha...

www.ti.com Architecture 2.11.3 Receive Address Matching The receive address block can store up to 32 addresses to be filtered or matched. Before enabling packetreception, all the address RAM locations should be initialized, including locations to be unused. Thesystem software is responsible for addi...

Architecture www.ti.com 2.11.5 Host Free Buffer Tracking The host must track free buffers for each enabled channel (including unicast, multicast, broadcast, andpromiscuous), if receive QOS or receive flow control is used. Disabled channel free buffer values are donot cares. During initialization, th...

www.ti.com Architecture • If the frame length is 1522, there are 1518 bytes transferred to memory. The last byte is the last databyte. 2.11.8 Promiscuous Receive Mode When the promiscuous receive mode is enabled by setting the RXCAFEN bit in the receivemulticast/broadcast/promiscuous channel enable ...

Architecture www.ti.com Table 4. Receive Frame Treatment Summary (continued) Address Match RXCAFEN RXCEFEN RXCMFEN RXCSFEN Receive Frame Treatment 1 X 1 1 0 Proper/oversize/jabber/code/align/CRC data andcontrol frames transferred to address matchchannel. No undersized/fragment frames aretransferred....

www.ti.com Architecture 2.12 Packet Transmit Operation The transmit DMA is an eight channel interface. Priority between the eight queues may be either fixed orround-robin as selected by the TXPTYPE bit in the MAC control register (MACCONTROL). If the prioritytype is fixed, then channel 7 has the hig...

Architecture www.ti.com Receive overrun is prevented if the receive memory cell latency is less than the time required to transmit a64-byte cell on the wire (0.512 ms in 1 Gbps mode, 5.12 ms in 100 Mbps mode, or 51.2ms in 10 Mbpsmode). The latency time includes any required buffer descriptor reads f...

www.ti.com Architecture 2.15.2 Hardware Reset Considerations When a hardware reset occurs, the EMAC peripheral has its register values reset and all the componentsreturn to their default state. After the hardware reset, the EMAC needs to be initialized before being ableto resume its data transmissio...

Architecture www.ti.com Example 4. EMAC Control Module Initialization Code Uint32 tmpval ; /* Disable all the EMAC/MDIO interrupts in the control module */EmacControlRegs->CONTROL.C_RX_EN = 0;EmacControlRegs->CONTROL.C_TX_EN = 0;EmacControlRegs->CONTROL.C_RX_THRESH_EN = 0; EmacControlRegs-&...

www.ti.com Architecture 2.16.3 MDIO Module Initialization The MDIO module is used to initially configure and monitor one or more external PHY devices. Otherthan initializing the software state machine (details on this state machine can be found in theIEEE 802.3 standard), all that needs to be done f...

Architecture www.ti.com 2.16.4 EMAC Module Initialization The EMAC module is used to send and receive data packets over the network. This is done bymaintaining up to eight transmit and receive descriptor queues. The EMAC module configuration mustalso be kept up-to-date based on PHY negotiation resul...

EMAC core MDIO core RXTHRESHOLDPEND(0..7) Receive threshold interrupt RXPEND(0..7) Receive interrupt TXPEND(0..7) Transmit interrupt STATPEND HOSTPEND MDIO_USER Miscellaneous interrupt MDIO_LINKINT Interrupt control and pacing logic www.ti.com Architecture 2.17 Interrupt Support 2.17.1 EMAC Module I...

Architecture www.ti.com Each of the eight transmit channel interrupts may be individually enabled by setting the correspondingbit in the transmit interrupt mask set register (TXINTMASKSET) to 1. Each of the eight transmit channelinterrupts may be individually disabled by clearing the corresponding b...

www.ti.com Architecture 2.17.1.4 Statistics Interrupt The statistics level interrupt (STATPEND) is issued when any statistics value is greater than or equal to8000 0000h, if enabled by setting the STATMASK bit in the MAC interrupt mask set register(MACINTMASKSET) to 1. The statistics interrupt is re...

Architecture www.ti.com 2.17.2 MDIO Module Interrupt Events and Requests The MDIO module generates two interrupt events:• LINKINT: Serial interface link change interrupt. Indicates a change in the state of the PHY link • USERINT: Serial interface user command event complete interrupt 2.17.2.1 Link C...

www.ti.com Architecture 2.18 Power Management Each of the three main components of the EMAC peripheral can independently be placed inreduced-power modes to conserve power during periods of low activity. The power management of theEMAC peripheral is controlled by the processor Power and Sleep Control...

EMAC Control Module Registers www.ti.com 3 EMAC Control Module Registers Table 7 lists the memory-mapped registers for the EMAC control module. See the device-specific data manual for the memory address of these registers. Table 7. EMAC Control Module Registers Slave VBUS Address Acronym Register De...

www.ti.com EMAC Control Module Registers 3.2 EMAC Control Module Software Reset Register (CMSOFTRESET) The software reset register (CMSOFTRESET) is shown in Figure 13 and described in Table 9 . Figure 13. EMAC Control Module Software Reset Register (CMSOFTRESET) 31 16 Reserved R-0 15 1 0 Reserved SO...

EMAC Control Module Registers www.ti.com 3.4 EMAC Control Module Interrupt Control Register (CMINTCTRL) The interrupt control register (CMINTCTRL) is shown in Figure 15 and described in Table 11 . Figure 15. EMAC Control Module Interrupt Control Register (CMINTCTRL) 31 30 18 17 16 Reserved Reserved ...

www.ti.com EMAC Control Module Registers 3.5 EMAC Control Module Receive Threshold Interrupt Enable Register(CMRXTHRESHINTEN) The receive threshold interrupt enable register (CMRXTHRESHINTEN) is shown in Figure 16 and described in Table 12 . Figure 16. EMAC Control Module Receive Threshold Interrupt...

EMAC Control Module Registers www.ti.com 3.7 EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN) The transmit interrupt enable register (CMTXINTEN) is shown in Figure 18 and described in Table 14 . Figure 18. EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN) 31 16 Res...

www.ti.com EMAC Control Module Registers 3.8 EMAC Control Module Miscellaneous Interrupt Enable Register (CMMISCINTEN) The miscellaneous interrupt enable register (CMMISCINTEN) is shown in Figure 19 and described in Table 15 . Figure 19. EMAC Control Module Miscellaneous Interrupt Enable Register (C...

www.ti.com EMAC Control Module Registers 3.11 EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT) The transmit interrupt status register (CMTXINTSTAT) is shown in Figure 22 and described in Table 18 . Figure 22. EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT) 31...

MDIO Registers www.ti.com 4 MDIO Registers Table 22 lists the memory-mapped registers for the MDIO module. See the device-specific data manual for the memory address of these registers. Table 22. Management Data Input/Output (MDIO) Registers Offset Acronym Register Description Section 0h VERSION MDI...

www.ti.com MDIO Registers 4.2 MDIO Control Register (CONTROL) The MDIO control register (CONTROL) is shown in Figure 27 and described in Table 24 . Figure 27. MDIO Control Register (CONTROL) 31 30 29 28 24 23 21 20 19 18 17 16 IDLE ENABLE Rsvd HIGHEST_USER_CHANNEL Reserved PREAMBLE FAULT FAULTENB Re...

MDIO Registers www.ti.com 4.3 PHY Acknowledge Status Register (ALIVE) The PHY acknowledge status register (ALIVE) is shown in Figure 28 and described in Table 25 . Figure 28. PHY Acknowledge Status Register (ALIVE) 31 16 ALIVE R/W1C-0 15 0 ALIVE R/W1C-0 LEGEND: R/W = Read/Write; W1C = Write 1 to cle...

MDIO Registers www.ti.com 4.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) The MDIO user command complete interrupt mask clear register (USERINTMASKCLEAR) is shown in Figure 35 and described in Table 32 . Figure 35. MDIO User Command Complete Interrupt Mask Clear Regi...

www.ti.com MDIO Registers 4.11 MDIO User Access Register 0 (USERACCESS0) The MDIO user access register 0 (USERACCESS0) is shown in Figure 36 and described in Table 33 . Figure 36. MDIO User Access Register 0 (USERACCESS0) 31 30 29 28 26 25 21 20 16 GO WRITE ACK Reserved REGADR PHYADR R/W1S-0 R/W-0 R...

MDIO Registers www.ti.com 4.12 MDIO User PHY Select Register 0 (USERPHYSEL0) The MDIO user PHY select register 0 (USERPHYSEL0) is shown in Figure 37 and described in Table 34 . Figure 37. MDIO User PHY Select Register 0 (USERPHYSEL0) 31 16 Reserved R-0 15 8 7 6 5 4 0 Reserved LINKSEL LINKINTENB Rsvd...

www.ti.com MDIO Registers 4.13 MDIO User Access Register 1 (USERACCESS1) The MDIO user access register 1 (USERACCESS1) is shown in Figure 38 and described in Table 35 . Figure 38. MDIO User Access Register 1 (USERACCESS1) 31 30 29 28 26 25 21 20 16 GO WRITE ACK Reserved REGADR PHYADR R/W1S-0 R/W-0 R...

MDIO Registers www.ti.com 4.14 MDIO User PHY Select Register 1 (USERPHYSEL1) The MDIO user PHY select register 1 (USERPHYSEL1) is shown in Figure 39 and described in Table 36 . Figure 39. MDIO User PHY Select Register 1 (USERPHYSEL1) 31 16 Reserved R-0 15 8 7 6 5 4 0 Reserved LINKSEL LINKINTENB Rsvd...

www.ti.com Ethernet Media Access Controller (EMAC) Registers 5 Ethernet Media Access Controller (EMAC) Registers Table 37 lists the memory-mapped registers for the EMAC. See the device-specific data manual for the memory address of these registers. Table 37. Ethernet Media Access Controller (EMAC) R...

Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.1 Transmit Identification and Version Register (TXIDVER) The transmit identification and version register (TXIDVER) is shown in Figure 40 and described in Table 38 . Figure 40. Transmit Identification and Version Register (TXIDVER) 31 16...

www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.3 Transmit Teardown Register (TXTEARDOWN) The transmit teardown register (TXTEARDOWN) is shown in Figure 42 and described in Table 40 . Figure 42. Transmit Teardown Register (TXTEARDOWN) 31 16 Reserved R-0 15 3 2 0 Reserved TXTDNCH R-0 R...

Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.4 Receive Identification and Version Register (RXIDVER) The receive identification and version register (RXIDVER) is shown in Figure 43 and described in Table 41 . Figure 43. Receive Identification and Version Register (RXIDVER) 31 16 RX...

www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.5 Receive Control Register (RXCONTROL) The receive control register (RXCONTROL) is shown in Figure 44 and described in Table 42 . Figure 44. Receive Control Register (RXCONTROL) 31 16 Reserved R-0 15 1 0 Reserved RXEN R-0 R/W-0 LEGEND: R...

Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.9 Transmit Interrupt Mask Set Register (TXINTMASKSET) The transmit interrupt mask set register (TXINTMASKSET) is shown in Figure 48 and described in Table 46 . Figure 48. Transmit Interrupt Mask Set Register (TXINTMASKSET) 31 16 Reserved...

Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.11 MAC Input Vector Register (MACINVECTOR) The MAC input vector register (MACINVECTOR) is shown in Figure 50 and described in Table 48 . Figure 50. MAC Input Vector Register (MACINVECTOR) 31 28 27 26 25 24 23 16 Reserved STATPEND HOSTPEN...

www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.15 Receive Interrupt Mask Set Register (RXINTMASKSET) The receive interrupt mask set register (RXINTMASKSET) is shown in Figure 54 and described in Table 52 . Figure 54. Receive Interrupt Mask Set Register (RXINTMASKSET) 31 16 Reserved R...

Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) The receive interrupt mask clear register (RXINTMASKCLEAR) is shown in Figure 55 and described in Table 53 . Figure 55. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) 31 1...

Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.19 MAC Interrupt Mask Set Register (MACINTMASKSET) The MAC interrupt mask set register (MACINTMASKSET) is shown in Figure 58 and described in Table 56 . Figure 58. MAC Interrupt Mask Set Register (MACINTMASKSET) 31 16 Reserved R-0 15 2 1...

Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.22 Receive Unicast Enable Set Register (RXUNICASTSET) The receive unicast enable set register (RXUNICASTSET) is shown in Figure 61 and described in Table 59 . Figure 61. Receive Unicast Enable Set Register (RXUNICASTSET) 31 16 Reserved R...

www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.23 Receive Unicast Clear Register (RXUNICASTCLEAR) The receive unicast clear register (RXUNICASTCLEAR) is shown in Figure 62 and described in Table 60 . Figure 62. Receive Unicast Clear Register (RXUNICASTCLEAR) 31 16 Reserved R-0 15 8 R...

Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.24 Receive Maximum Length Register (RXMAXLEN) The receive maximum length register (RXMAXLEN) is shown in Figure 63 and described in Table 61 . Figure 63. Receive Maximum Length Register (RXMAXLEN) 31 16 Reserved R-0 15 0 RXMAXLEN R/W-151...

www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.29 MAC Control Register (MACCONTROL) The MAC control register (MACCONTROL) is shown in Figure 68 and described in Table 66 . Figure 68. MAC Control Register (MACCONTROL) 31 18 17 16 Reserved R-0 15 14 13 12 11 10 9 8 Reserved RXOFFLENBLO...

www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.30 MAC Status Register (MACSTATUS) The MAC status register (MACSTATUS) is shown in Figure 69 and described in Table 67 . Figure 69. MAC Status Register (MACSTATUS) 31 30 24 23 20 19 18 16 IDLE Reserved TXERRCODE Rsvd TXERRCH R-0 R-0 R-0 ...

www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.31 Emulation Control Register (EMCONTROL) The emulation control register (EMCONTROL) is shown in Figure 70 and described in Table 68 . Figure 70. Emulation Control Register (EMCONTROL) 31 16 Reserved R-0 15 2 1 0 Reserved SOFT FREE R-0 R...

Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.33 MAC Configuration Register (MACCONFIG) The MAC configuration register (MACCONFIG) is shown in Figure 72 and described in Table 70 . Figure 72. MAC Configuration Register (MACCONFIG) 31 24 23 16 TXCELLDEPTH RXCELLDEPTH R-18h R-44h 15 8...

www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) The MAC source address low bytes register (MACSRCADDRLO) is shown in Figure 74 and described in Table 72 . Figure 74. MAC Source Address Low Bytes Register (MACSRCADDRLO) 31 16 Rese...

Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.37 MAC Hash Address Register 1 (MACHASH1) The MAC hash registers allow group addressed frames to be accepted on the basis of a hash functionof the address. The hash function creates a 6-bit data value (Hash_fun) from the 48-bit destinati...

www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.39 Back Off Test Register (BOFFTEST) The back off test register (BOFFTEST) is shown in Figure 78 and described in Table 76 . Figure 78. Back Off Random Number Generator Test Register (BOFFTEST) 31 26 25 16 Reserved RNDNUM R-0 R-0 15 12 1...

Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.41 Receive Pause Timer Register (RXPAUSE) The receive pause timer register (RXPAUSE) is shown in Figure 80 and described in Table 78 . Figure 80. Receive Pause Timer Register (RXPAUSE) 31 16 Reserved R-0 15 0 PAUSETIMER R-0 LEGEND: R = R...

Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.44 MAC Address High Bytes Register (MACADDRHI) The MAC address high bytes register (MACADDRHI) is shown in Figure 83 and described in Table 81 . Figure 83. MAC Address High Bytes Register (MACADDRHI) 31 24 23 16 MACADDR2 MACADDR3 R/W-0 R...

www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.50 Network Statistics Registers The EMAC has a set of statistics that record events associated with frame traffic. The statistics valuesare cleared to zero 38 clocks after the rising edge of reset. When the MII bit in the MACCONTROLregis...

Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.50.4 Pause Receive Frames Register (RXPAUSEFRAMES) The total number of IEEE 802.3X pause frames received by the EMAC (whether acted upon or not). Apause frame is defined as having all of the following: • Contained any unicast, broadcast,...

www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.50.8 Receive Jabber Frames Register (RXJABBER) The total number of jabber frames received on the EMAC. A jabber frame is defined as having all of thefollowing: • Was any data or MAC control frame that matched a unicast, broadcast, or mul...

Ethernet Media Access Controller (EMAC) Registers www.ti.com 5.50.33 Network Octet Frames Register (NETOCTETS) The total number of bytes of frame data received and transmitted on the EMAC. Each frame countedhas all of the following: • Was any data or MAC control frame destined for any unicast, broad...

www.ti.com Appendix A Glossary Broadcast MAC Address— A special Ethernet MAC address used to send data to all Ethernet devices on the local network. The broadcast address is FFh-FFh-FFh-FFh-FFh-FFh. The LSB ofthe first byte is odd, qualifying it as a group address; however, its value is reserved for...

Appendix A www.ti.com Multicast MAC Address— A class of MAC address that sends a packet to potentially more than one recipient. A group address is specified by setting the LSB of the first MAC address byte to 1.Thus, 01h-02h-03h-04h-05h-06h is a valid multicast address. Typically, an Ethernet MAC lo...

www.ti.com Appendix B Revision History Table 88 lists the changes made since the previous version of this document. Table 88. Document Revision History Reference Additions/Modifications/Deletions Section 1.3 Changed fourth paragraph. 133 SPRUFI5B – March 2009 – Revised December 2010 Revision History...

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