Page 2 - PRODUCT PREVIEW; 0nm Process Technology
www.ti.com PRODUCT PREVIEW TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 – IEEE-1149.1 (JTAG) • 337-Pin Ball Grid Array (BGA) Package Boundary-Scan-Compatible (ZCE Suffix), 0.65-mm Ball Pitch – ETB (Embedded Trace Buffer) with • 90nm Process Techn...
Page 4 - Functional Block Diagram; shows the functional block diagram of the DM355 device.
www.ti.com PRODUCT PREVIEW 1.3 Functional Block Diagram Peripherals 64bit DMA/Data Bus JTAG 24 MHz 27 MHz (optional) CCD/ CMOS Module DDR2/MDDR 16 CLOCK PLL CLOCK ctrl PLLs JTA JTAG I/F Clocks ARM z ) ARM926EJ-S_Z8 I- cach e 16 K B l-cache 16KB B RA M 32 K B RAM 32KB B D- cach e 8 K D-cache 8KB RO M...
Page 5 - Contents
www.ti.com PRODUCT PREVIEW Contents TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 1 TMS320DM355 Digital Media System-on-Chip 4.2 Recommended Operating Conditions ............... 92 (DMSoC) ................................................... 1 4.3...
Page 6 - Device Characteristics; Table 2-1. Characteristics of the Processor; HARDWARE FEATURES
www.ti.com PRODUCT PREVIEW 2 Device Overview 2.1 Device Characteristics TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-1 provides an overview of the DMSoC. The table shows significant features of the device, including the peripherals, capac...
Page 7 - Memory Map Summary; shows the memory map address ranges of the device.; Table 2-3. DM355 ARM Configuration Bus Access to Peripherals
www.ti.com PRODUCT PREVIEW 2.2 Memory Map Summary TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-3 shows the memory map address ranges of the device. Table 2-3 depicts the expanded map of the Configuration Space (0x01C0 0000 through 0x01FF...
Page 8 - Address
www.ti.com PRODUCT PREVIEW TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-3. DM355 ARM Configuration Bus Access to Peripherals (continued) Address Accessibility UART1 0x01C2 0400 0x01C2 07FF 1K √ √ Timer4/5 0x01C2 0800 0x01C2 0BFF 1K √ √ Re...
Page 9 - through
www.ti.com PRODUCT PREVIEW 2.3 Pin Assignments 2.3.1 Pin Map (Bottom View) 9 J 8 V SSA_PLL2 7 V DDA33_USB 6 5 4 3 1 H G V DDA13_USB V SS F E D CIN2 C B A VREF CIN3 CIN0 V DDA_PLL2 V SS LCD_OE FIELD VCLK V SS V SS CV DD VSYNC EXTCLK VFB V DD_VOUT V DD_VOUT V DD_VOUT HSYNC COUT0 COUT1 TVOUT TDO EMU0 E...
Page 13 - Image Data Input - Video Processing Front End; The pin functions tables (; Table 2-4. CCD Controller Signals for Each Input Mode; PIN NAME
www.ti.com PRODUCT PREVIEW 2.4 Pin Functions 2.4.1 Image Data Input - Video Processing Front End TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The pin functions tables ( Table 2-4 through Table 2-22 ) identify the external signal names, the assoc...
Page 14 - TERMINAL
www.ti.com PRODUCT PREVIEW TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-5. CCD Controller/Video Input Terminal Functions TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO. Standard CCD Analog Front End (AFE): NOT USED • YCC 16-bit: Time...
Page 15 - and
www.ti.com PRODUCT PREVIEW 2.4.2 Image Data Output - Video Processing Back End (VPBE) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-5. CCD Controller/Video Input Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION N...
Page 16 - Table 2-6. Signals for VPBE Display Modes
www.ti.com PRODUCT PREVIEW TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-6. Signals for VPBE Display Modes PIN NAME YCC16 YCC8/ PRGB SRGB REC656 HSYNC HSYNC HSYNC HSYNC HSYNC GIO073 VSYNC VSYNC VSYNC VSYNC VSYNC GIO072 LCD_OE As needed As ...
Page 17 - Table 2-7. Digital Video Terminal Functions
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-7. Digital Video Terminal Functions TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION (4) NAME NO. YOUT7-R7 C3 I/O/Z V DD_VOUT Digital Video Out: VENC settings determine f...
Page 18 - Asynchronous External Memory Interface (AEMIF); Table 2-8. Analog Video Terminal Functions
www.ti.com PRODUCT PREVIEW 2.4.3 Asynchronous External Memory Interface (AEMIF) TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-8. Analog Video Terminal Functions TERMINAL TYPE (1) OTHER (2) DESCRIPTION NAME NO. Video DAC: Reference voltage ...
Page 20 - DDR Memory Interface; The DDR EMIF supports DDR2 and mobile DDR.
www.ti.com PRODUCT PREVIEW 2.4.4 DDR Memory Interface TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-9. Asynchronous EMIF/NAND/OneNAND Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO. Async EMIF: Lowest nu...
Page 22 - GPIO
www.ti.com PRODUCT PREVIEW 2.4.5 GPIO TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The General Purpose I/O signals provide generic I/O to external devices. Most of the GIO signals aremultiplexed with other functions. Table 2-11. GPIO Terminal Fun...
Page 29 - Audio Interfaces
www.ti.com PRODUCT PREVIEW 2.4.7 Universal Serial Bus (USB) Interface 2.4.8 Audio Interfaces TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The Universal Serial Bus (USB) interface supports the USB2.0 High-Speed protocol and includes dual-roleHost...
Page 30 - UART Interface
www.ti.com PRODUCT PREVIEW 2.4.9 UART Interface TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-14. ASP Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO. ASP0_CL ASP0: Transmit Clock KX / F18 I/O/Z V DD GIO:...
Page 31 - C Interface; The includes an I; C Terminal Functions
www.ti.com PRODUCT PREVIEW 2.4.10 I 2 C Interface 2.4.11 Serial Interface TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-15. UART Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO. MMCSD1_DA MMCSD1: DATA0 T...
Page 32 - The provides interface with the system clocks.
www.ti.com PRODUCT PREVIEW 2.4.12 Clock Interface TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-17. SPI Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO. Standard CCD Analog Front End (AFE): Not used • YCC...
Page 34 - The provides interfaces for system configuration and boot load.
www.ti.com PRODUCT PREVIEW 2.4.15 System Configuration Interface TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-20. PWM Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO. COUT3-B6 / Digital Video Out: VENC s...
Page 35 - The emulation interface allow software and hardware debugging.
www.ti.com PRODUCT PREVIEW 2.4.16 Emulation TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-21. System/Boot Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO. Async EMIF: Address bus bit 08GIO: GIO[062] EM_A...
Page 36 - provides a complete pin description list in pin number order.
www.ti.com PRODUCT PREVIEW 2.5 Pin List TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 2-23 provides a complete pin description list in pin number order. Table 2-23. DM355 Pin Descriptions Name BGA Type Group Power PU Reset Description (4) Mu...
Page 55 - Development Tools; . For information on pricing and
www.ti.com PRODUCT PREVIEW 2.6 Device Support 2.6.1 Development Tools 2.6.2 Device Nomenclature TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 TI offers an extensive line of development tools for DM355 systems, including tools to evaluate theperfo...
Page 56 - Device Documentation; This document; SPRUFB3
www.ti.com PRODUCT PREVIEW DM355 PREFIX TMX 320 DM355 ZCE TMX = Experimental deviceTMS = Qualified device DEVICE FAMILY 320 = TMS320 DSP family PACKAGE TYPE (A) ZCE = 337-pin plastic BGA, with Pb-free soldered balls DEVICE (B) A. BGA = Ball Grid Array B. ( ) SILICON REVISION Blank = Initial Silicon1...
Page 57 - DMSoC
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Digital Media System-on-Chip (DMSoC). The primary audio modes that are supported by theASP are the AC97 and IIS modes. In addition to the primary audio modes, the ASP suppor...
Page 58 - SPRUEE7
www.ti.com PRODUCT PREVIEW TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 SPRUEE7 TMS320DM35x DMSoC Pulse-Width Modulator (PWM) Reference Guide This documentdescribes the pulse-width modulator (PWM) peripheral in the TMS320DM35x Digital MediaSystem...
Page 59 - Detailed Device Description; ARM Subsystem Overview; Components of the ARM Subsystem
www.ti.com PRODUCT PREVIEW 3 Detailed Device Description 3.1 ARM Subsystem Overview 3.1.1 Components of the ARM Subsystem TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 This section provides a detailed overview of the DM355 device. The ARM Subsyst...
Page 60 - Figure 3-1. DM355 ARM Subsystem Block Diagram
www.ti.com PRODUCT PREVIEW ARM926EJ-S 16K I$ 8K D$ MMU CP15 Arbiter Arbiter I-AHBD-AHB Master IF DMAbus I-TCM D-TCM 16K RAM0 RAM1 16K ROM 8K Arbiter Slave IF Master IF CFGbus ARM interrupt controller (AINTC) control System PLLC2 PLLC1 (PSC) controller sleep Power Peripherals ... 3.2 ARM926EJ-S RISC ...
Page 61 - MMU; Hardware page table walks
www.ti.com PRODUCT PREVIEW 3.2.1 CP15 3.2.2 MMU 3.2.3 Caches and Write Buffer TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 • Embedded Trace Module and Embedded Trace Buffer (ETM/ETB) For more complete details on the ARM9, refer to the ARM926EJ-S...
Page 62 - Memory Mapping; ARM Internal Memories
www.ti.com PRODUCT PREVIEW 3.2.4 Tightly Coupled Memory (TCM) 3.2.5 Advanced High-performance Bus (AHB) 3.2.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB) 3.3 Memory Mapping 3.3.1 ARM Internal Memories TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVI...
Page 63 - External Memories
www.ti.com PRODUCT PREVIEW 3.3.2 External Memories 3.3.3 Peripherals 3.4 ARM Interrupt Controller (AINTC) 3.4.1 Interrupt Mapping TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The ARM has access to the following External memories: • DDR2 / mDDR S...
Page 65 - Overview; . The PLLs are described further in
www.ti.com PRODUCT PREVIEW 3.5 Device Clocking 3.5.1 Overview TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The DM355 requires one primary reference clock . The reference clock frequency may be generatedeither by crystal input or by external osci...
Page 66 - Sequencer; Figure 3-2. Device Clocking Block Diagram
www.ti.com PRODUCT PREVIEW ARM subsystem MPEG/JPEG Coprocessor SYSCLK1 SYSCLK2 VPFE VPBE DAC DDR PHY DDR PLLDIV1 (/1) BPDIV (/8) PLL controller 2 PLL controller 1 PLLDIV3 (/n) PLLDIV2 (/4) PLLDIV1 (/2) SYSCLK3 I2C Timers (x4) PWMs (x4) SPI (x3) MMC/SD (x2) EMIF/NAND ASP (x2) GPIO UART2 ARM INTC USB ...
Page 67 - Supported Clocking Configurations for DM355-216
www.ti.com PRODUCT PREVIEW 3.5.2 Supported Clocking Configurations for DM355-216 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 This section describes the only supported device clocking configurations for DM355-216. The DM355supports either 24 MHz...
Page 69 - Supported Clocking Configurations for DM355-270
www.ti.com PRODUCT PREVIEW 3.5.3 Supported Clocking Configurations for DM355-270 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 This section describes the only supported device clocking configurations for DM355-270. The DM355supports either 24 MHz...
Page 71 - Peripheral Clocking Considerations; 4 MHz crystal input at MXI1; NOTE; For proper USB function, SYSCLK2 must be greater than 60 MHz.
www.ti.com PRODUCT PREVIEW 3.5.4 Peripheral Clocking Considerations TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 3.5.3.2.2 DM355-270 PLL2 (36 MHz reference) All supported clocking configurations for DM355-270 PLL2 with 36 MHz reference clock are...
Page 73 - PLL Controller Module
www.ti.com PRODUCT PREVIEW 3.6 PLL Controller (PLLC) 3.6.1 PLL Controller Module TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 This section describes the PLL Controllers for PLL1 and PLL2. See the TMS320DM355 Digital MediaSystem-on-Chip ARM Subsy...
Page 74 - Output Clock
www.ti.com PRODUCT PREVIEW 3.6.2 PLLC1 TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 PLLC1 provides most of the DM355 clocks. Software controls PLLC1 operation through the PLLC1registers. The following list, Table 3-10 , and Figure 3-3 describe th...
Page 76 - PLLC2 Configuration in DM355
www.ti.com PRODUCT PREVIEW 3.6.3 PLLC2 PLLDIV1 (/1) 1 0 PLL 0 1 CLKMODE CLKIN OSCIN PLLEN SYSCLK1(DDR PHY) SYSCLKBP(CLKOUT3) BPDIV (/8) PLLM (programmable) Pre-DIV (programmable) Post-DIV (/1) TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 PLLC2 pr...
Page 77 - System Control Module
www.ti.com PRODUCT PREVIEW 3.7 Power and Sleep Controller (PSC) arm_clockarm_mresetarm_power AINTC ARM module_power module_mreset MODx module_clock Always on domain Interrupt PSC clks PLLC Emulation RESETN VDD DMSoC 3.8 System Control Module TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A ...
Page 78 - Hardware Controlled Pin Multiplexing; Deep sleep and fast NAND boot control; Peripheral
www.ti.com PRODUCT PREVIEW 3.9 Pin Multiplexing 3.9.1 Hardware Controlled Pin Multiplexing TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 • Power management– Deep sleep and fast NAND boot control • Bandwidth Management– Bus master DMA priority cont...
Page 79 - Software Controlled Pin Multiplexing; and further described in the ARM; Type
www.ti.com PRODUCT PREVIEW 3.9.2 Software Controlled Pin Multiplexing 3.10 Device Reset TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 3-13. AECFG (Async EMIF Configuration) Pin Mux Coding 1101(NAND) 1100 1010 (OneNAND) 1000 (8-bit SRAM) 001...
Page 80 - Default Device Configurations; for more information on the boot process.; The device configuration pins are described in
www.ti.com PRODUCT PREVIEW 3.11 Default Device Configurations 3.11.1 Device Configuration Pins TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 3-14. Reset Types (continued) Type Initiator Effect Module Reset ARM software Resets a specific modu...
Page 81 - Power Domain and Module State Configuration
www.ti.com PRODUCT PREVIEW 3.11.2 PLL Configuration 3.11.3 Power Domain and Module State Configuration TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 After POR, warm reset, and max reset, the PLLs and clocks are set to their default configurations...
Page 83 - Device Boot Modes; Default States; Boot modes are further described in
www.ti.com PRODUCT PREVIEW 3.11.4 ARM Boot Mode Configuration 3.11.5 AEMIF Configuration 3.12 Device Boot Modes TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 3-16. Module Configuration (continued) Default States 31 ARM AlwaysOn ON Enable 32...
Page 84 - for information on the boot selection pins.
www.ti.com PRODUCT PREVIEW 3.12.1 Boot Modes Overview TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The boot selection pins (BTSEL[1:0]) determine the ARM boot process. After reset (POR, warm reset, ormax reset), ARM program execution begins in AR...
Page 85 - Power Management; The general boot sequence is shown in; Figure 3-6. Boot Mode Functional Block Diagram
www.ti.com PRODUCT PREVIEW Boot mode ? Reset Boot mode ? Boot from NAND flash Internal ROM Boot OK ? No Yes Boot from UART Boot from MMC/SD Boot OK ? Boot OK ? Yes No Invoke loaded Program Invoke OneNAND No Yes 3.13 Power Management TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMB...
Page 86 - Power Management Features
www.ti.com PRODUCT PREVIEW TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 to static current leakage and occurs regardless of the clock rate. Leakage, or standby power, isunavoidable while power is applied and scales roughly with the operating junct...
Page 87 - Slave Module
www.ti.com PRODUCT PREVIEW 3.14 64-Bit Crossbar Architecture 3.14.1 Crossbar Connections 3.14.2 EDMA Controller TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The DM355 uses a 64-bit crossbar architecture to control access between device processor...
Page 89 - EDMA Channel Synchronization Events; EDMA
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 DMA Channels: Can be triggered by: " External events (for example, ASP TX Evt and RX Evt), " Softwarewriting a '1' to the given bit location, or channel, of the Even...
Page 91 - Device Operating Conditions
www.ti.com PRODUCT PREVIEW 4 Device Operating Conditions 4.1 Absolute Maximum Ratings Over Operating Case Temperature Range TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 (Unless Otherwise Noted) (3) (4) All 1.3 V supplies -0.5 V to 1.7 V All digi...
Page 92 - Recommended Operating Conditions; MIN NOM
www.ti.com PRODUCT PREVIEW 4.2 Recommended Operating Conditions TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 MIN NOM MAX UNIT CV DD Supply voltage, Core 1.235 1.3 1.365 V V DDA_PLL1 Supply voltage, PLL1 1.235 1.3 1.365 V V DDA_PLL2 Supply voltage...
Page 93 - Case Temperature (Unless Otherwise Noted)
www.ti.com PRODUCT PREVIEW 4.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Case Temperature (Unless Otherwise Noted) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UN...
Page 94 - Parameter Information Device-Specific Information; Tester Pin Electronics; Signal Transition Levels; Figure 5-1. Test Load Circuit for AC Timing Measurements; All input and output timing parameters are referenced to V; Figure 5-3. Rise and Fall Transition Time Voltage Reference Levels
www.ti.com PRODUCT PREVIEW 5 Peripheral Information and Electrical Specifications 5.1 Parameter Information Device-Specific Information Transmission Line 4.0 pF 1.85 pF Z0 = 50 Ω (see note) Tester Pin Electronics Data Sheet Timing Reference Point OutputUnderTest 42 Ω 3.5 nH Device Pin(see note) 5.1....
Page 95 - Timing Parameters and Board Routing Analysis
www.ti.com PRODUCT PREVIEW 5.1.2 Timing Parameters and Board Routing Analysis TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The timing parameter values specified in this data sheet do not include delays by board routings. As agood board design pr...
Page 96 - Recommended Clock and Control Signal Transition Behavior; All clocks and control signals should transition between V; and V; and V; The power supplies of DM355 are summarized in
www.ti.com PRODUCT PREVIEW 5.2 Recommended Clock and Control Signal Transition Behavior 5.3 Power Supplies TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 All clocks and control signals should transition between V IH and V IL (or between V IL and V ...
Page 97 - Power-Supply Sequencing; for a description of DM355 power supplies.; Power-Supply Design Considerations; placed outside of the BGA footprint.
www.ti.com PRODUCT PREVIEW 5.3.1 Power-Supply Sequencing TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 In order to ensure device reliability, the DM355 requires the following power supply power-on andpower-off sequences. See table Table 5-1 for a...
Page 98 - Reset Electrical Data/Timing; UNIT
www.ti.com PRODUCT PREVIEW 5.4 Reset 5.4.1 Reset Electrical Data/Timing 1 2 3 RESET Boot Configuration Pins (BTSEL[1:0], AECFG[3:0]) TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-2. Timing Requirements for Reset (1) (2) (see Figure 5-4 ) D...
Page 99 - Oscillators and Clocks; circuit shown in
www.ti.com PRODUCT PREVIEW 5.5 Oscillators and Clocks 5.5.1 MXI1 (24-MHz) Oscillator Crystal 24 MHz or36 MHz C1 C2 MXI1/CLKIN MXO1 V SS_MX1 0.1 F 1 F L1 V DDA_PLL1 V SSA_PLL1 C L C 1 C 2 (C 1 C 2 ) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 ha...
Page 100 - . The external crystal load capacitors must be connected only to; shown in; Oscillator
www.ti.com PRODUCT PREVIEW 5.5.2 MXI2 (27-MHz) Oscillator (optional oscillator) Crystal 27 MHz C1 C2 MXI2 MXO2 V SS_MX2 L1 V DDA_PLL2 V SSA_PLL2 0.1 F 1 F C L C 1 C 2 (C 1 C 2 ) TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-3. Switching Ch...
Page 103 - PARAMETER
www.ti.com PRODUCT PREVIEW 5 6 1 2 3 4 4 MXI/CLKIN CLKOUT3 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-9. Switching Characteristics Over Recommended Operating Conditions for CLKOUT3 (1) (2) (see Figure 5-11 ) DM355 NO. PARAMETER UNIT MI...
Page 104 - GPIO Peripheral Input/Output Electrical Data/Timing; The GPIO peripheral supports the following:
www.ti.com PRODUCT PREVIEW 5.6 General-Purpose Input/Output (GPIO) 5.6.1 GPIO Peripheral Input/Output Electrical Data/Timing TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The GPIO peripheral provides general-purpose pins that can be configured as ...
Page 105 - GPIO Peripheral External Interrupts Electrical Data/Timing; Figure 5-13. GPIO External Interrupt Timing
www.ti.com PRODUCT PREVIEW GPIx GPOx 4 3 2 1 5.6.2 GPIO Peripheral External Interrupts Electrical Data/Timing EXT_INTx 2 1 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Figure 5-12. GPIO Port Timing Table 5-12. Timing Requirements for External In...
Page 107 - AEMIF Electrical Data/Timing
www.ti.com PRODUCT PREVIEW TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.7.1.3 AEMIF Electrical Data/Timing Table 5-13. Timing Requirements for Asynchronous Memory Cycles for AEMIF Module (1) (see Figure 5-14 and Figure 5-15 ) DM355 NO UNIT . M...
Page 108 - Memory Cycles for AEMIF Module (see
www.ti.com PRODUCT PREVIEW TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-14. Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for AEMIF Module (see Figure 5-14 and Figure 5-15 ) (continued) DM3...
Page 109 - UNI; Figure 5-14. Asynchronous Memory Read Timing for EMIF
www.ti.com PRODUCT PREVIEW EM_CE[1:0] EM_BA[1:0] 13 12 EM_A[13:0] EM_OE EM_D[15:0] EM_WE 10 59 7 48 6 3 1 EM_CE[1:0] EM_BA[1:0] EM_A[13:0] EM_WE EM_D[15:0] EM_OE 15 1 16 18 20 22 24 17 19 21 23 26 27 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 ...
Page 111 - Figure 5-18. Synchronous OneNAND Flash Read Timing
www.ti.com PRODUCT PREVIEW 34 33 35 36 37 30 31 Da Da+1 Da+2 Da+3 Da+4 Da+5 Da+n Da+n+1 EM_CLK EM_CE[1:0] EM_ADV EM_BA0, EM_A[13:0], EM_BA1 EM_D[15:0] EM_OE EM_WAIT 38 39 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Figure 5-18. Synchronous OneN...
Page 112 - DDR2 Memory Controller
www.ti.com PRODUCT PREVIEW 5.7.2 DDR2 Memory Controller TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The DDR2 / mDDR Memory Controller is a dedicated interface to DDR2 / mDDR SDRAM. It supportsJESD79D-2A standard compliant DDR2 SDRAM devices and ...
Page 115 - SPRUEC8
www.ti.com PRODUCT PREVIEW 5.9 Video Processing Sub-System (VPSS) Overview 5.9.1 Video Processing Front-End (VPFE) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The contains a Video Processing Sub-System (VPSS) that provides an input interface (V...
Page 116 - Support for program lens shading correction.
www.ti.com PRODUCT PREVIEW TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 • Support for program lens shading correction. • Support for 10-bit to 8-bit A-law compression. • Support for a low-pass filter prior to writing to SDRAM. If this filter is e...
Page 120 - Support for 2 ROM tables, one of which can be selected at a given time
www.ti.com PRODUCT PREVIEW PCLK (Positive Edge Clocking) 18 20 HD VD PCLK (Negative Edge Clocking) 5.9.2 Video Processing Back-End (VPBE) TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-20. Switching Characteristics Over Recommended Operatin...
Page 123 - Figure 5-28. VPBE Input Timing With Respect to PCLK and EXTCLK
www.ti.com PRODUCT PREVIEW VCLKIN (A) (Positive Edge Clocking) 9 VCLKIN (A) (Negative Edge Clocking) 10 VCTL (B) A. VCLKIN = PCLK or EXTCLKB. VCTL = HSYNC, VSYNC, and FIELD VCLKIN (A) (Positive Edge Clocking) 13 VCLKIN (A) (Negative Edge Clocking) 11 VCTL (B) A. VCLKIN = PCLK or EXTCLKB. VCTL = HSYN...
Page 124 - Data Output With Respect to VCLK
www.ti.com PRODUCT PREVIEW VCLK (Positive Edge Clocking) VCLK (Negative Edge Clocking) 17 VCTL (B) VDATA (C) 19 18 22 21 23 24 25 26 VCLKIN (A) A. VCLKIN = PCLK or EXTCLKB. VCTL = HSYNC, VSYNC, FIELD, and LCD_OE C. VDATA = COUT[7:0], YOUT[7:0], R[7:3], G[7:2], and B[7:3] 20 20 TMS320DM355Digital Med...
Page 125 - Figure 5-31. DAC Only Application Example
www.ti.com PRODUCT PREVIEW DIN <9:0> MSB LSB DAC Digital Input Example for External Circuit Iout [mA] 1.4 mA 0 DAC Output Current C BG 0.1 F m VREF Video DAC R BIAS 2550 W IBIAS RLOAD 499 W IOUT Buffer VFB TVOUT TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVIS...
Page 128 - Figure 5-34. USB Reference Resistor Routing
www.ti.com PRODUCT PREVIEW t r t f V CRS 90% V OH 10% V OL USB_DM USB_DP t per − t jr V SS_USB_REF USB_R1 USB 10 K ±1% W TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Figure 5-33. USB2.0 Integrated Transceiver Interface Timing Figure 5-34. USB Ref...
Page 134 - to/from the DM355 through the I2C module.
www.ti.com PRODUCT PREVIEW 5.13 Inter-Integrated Circuit (I2C) TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The inter-integrated circuit (I2C) module provides an interface between and other devices compliant withPhilips Semiconductors Inter-IC bu...
Page 135 - I2C Electrical Data/Timing; Table 5-33. Timing Requirements for I2C Timings
www.ti.com PRODUCT PREVIEW 5.13.1 I2C Electrical Data/Timing 10 8 4 3 7 12 5 6 14 2 3 13 Stop Start Repeated Start Stop SDA SCL 1 11 9 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.13.1.1 Inter-Integrated Circuits (I2C) Timing Table 5-33. Timin...
Page 136 - Table 5-34. Switching Characteristics for I2C Timings; CAUTION
www.ti.com PRODUCT PREVIEW 23 19 18 22 20 21 17 18 28 Stop Start Repeated Start Stop SDA SCL 16 TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-34. Switching Characteristics for I2C Timings (1) (see Figure 5-40 ) DM355 STANDARD NO. PARAMETER...
Page 138 - ASP Electrical Data/Timing
www.ti.com PRODUCT PREVIEW 5.14.1 ASP Electrical Data/Timing TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 5.14.1.1 Audio Serial Port (ASP) Timing Table 5-35. Timing Requirements for ASP (1) (see Figure 5-41 ) DM355 NO. UNIT MIN MAX 15 tc(CLK) Cyc...
Page 140 - Table 5-37. ASP as SPI Timing Requirements
www.ti.com PRODUCT PREVIEW Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) M31 M30 M26 M27 M25 M24 CLKX FSX DX DR M33 TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-37. ASP as SPI Timing Requirements CLKSTP = 10b, CLKXP = ...
Page 141 - Table 5-39. ASP as SPI Timing Requirements
www.ti.com PRODUCT PREVIEW Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) M39 M36 M38 M37 M35 M34 CLKX FSX DX DR M40 M42 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-39. ASP as SPI Timing Requirements CLKSTP = 11b, CLK...
Page 142 - Table 5-41. ASP as SPI Timing Requirements
www.ti.com PRODUCT PREVIEW Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) M50 M49 M45 M46 M44 M43 CLKX FSX DX DR M52 TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-41. ASP as SPI Timing Requirements CLKSTP = 10b, CLKXP = ...
Page 143 - Table 5-43. ASP as SPI Timing Requirements
www.ti.com PRODUCT PREVIEW Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) M59 M58 M55 M57 M56 M54 M53 CLKX FSX DX DR M62 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 Table 5-43. ASP as SPI Timing Requirements CLKSTP = 11b, CLK...
Page 144 - Timer Electrical Data/Timing; Table 5-45. Timing Requirements for Timer Input
www.ti.com PRODUCT PREVIEW 5.15 Timer 5.15.1 Timer Electrical Data/Timing 1 2 4 4 3 TIM_IN TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The contains four software-programmable timers. Timer 0, Timer 1, and Timer 3 (general-purpose timers)can be p...
Page 145 - 2-bit period counter; Outputs
www.ti.com PRODUCT PREVIEW 5.16 Pulse Width Modulator (PWM) 5.16.1 PWM0/1/2/3 Electrical/Timing Data PWM0/1/2/3 1 3 3 2 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The DM355 contains 4 separate Pulse Width Modulator (PWM) modules. The pulse wid...
Page 147 - The Real Time Out (RTO) peripheral supports the following features:
www.ti.com PRODUCT PREVIEW 5.17 Real Time Out (RTO) 5.17.1 RTO Electrical/Timing Data RTO0/1/2/3 1 3 3 2 4 TINT12/TINT34 (Timer3) 4 4 INVALID INVALID INVALID VALID VALID VALID RTO0 4 INVALID VALID RTO1 RTO2 RTO3 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEP...
Page 148 - The JTAG
www.ti.com PRODUCT PREVIEW 5.18 IEEE 1149.1 JTAG TMS320DM355Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The JTAG (1) interface is used for BSDL testing and emulation of the device. The device requires that both TRST and RESET be asserted upon power up to b...
Page 151 - Revision History; Updated DM355 Pin Descriptions table, etc.
www.ti.com PRODUCT PREVIEW 6 Revision History TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 This data sheet revision history highlights the technical changes made to the SPRS463 device-specificdata sheet to make it an SPRS463A revision. Scope: Up...
Page 153 - Mechanical Data; Thermal Data for ZCE
www.ti.com PRODUCT PREVIEW 7 Mechanical Data 7.1 Thermal Data for ZCE 7.1.1 Packaging Information TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007 The following table(s) show the thermal resistance characteristics for the PBGA – ZCE mechanicalpackag...
Page 155 - IMPORTANT NOTICE; Products
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.Customers should obtain the l...
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