Texas Instruments TMS320C674X - Manuals

DMA Master 8K CPPI RAM Interrupt Combiner C0 C1 C2 Control Module EMAC Module MDIO Module EMAC Interrupts MDIOInterrupts Interrupts EMAC Sub System Register Bus DMA Bus MII/RMII Bus MDIO Bus www.ti.com Introduction 1.3 Functional Block Diagram Figure 1 shows the three main functional modules of the ...

Architecture www.ti.com 1.4 Industry Standard(s) Compliance Statement The EMAC peripheral conforms to the IEEE 802.3 standard, describing the Carrier Sense Multiple Accesswith Collision Detection (CSMA/CD) Access Method and Physical Layer specifications. The IEEE 802.3standard has also been adopted ...

MII_TXCLK MII_TXD[3−0] MII_TXEN MII_COL MII_CRS MII_RXCLK MII_RXD[3−0] MII_RXDV MII_RXER MDIO_CLK MDIO_D Physical layer device (PHY) System core Transformer 2.5 MHz or 25 MHz RJ−45 EMAC MDIO www.ti.com Architecture The individual EMAC and MDIO signals for the MII interface are summarized in Table 1 ...

RMII_TXD[1-0] RMII_TXEN RMII_MHZ_50_CLK RMII_RXD[1-0] RMII_CRS_DV RMII_RXER MDIO_CLK MDIO_D MDIO EMAC Physical Layer Device (PHY) Transformer 50 MHz RJ-45 Architecture www.ti.com Table 1. EMAC and MDIO Signals for MII Interface (continued) Signal Type Description MDIO_CLK O Management data clock (MD...

Preamble SFD Destination Source Len Data 7 1 6 6 2 46−1500 4 FCS Number of bytes Legend: SFD=Start Frame Delimeter; FCS=Frame Check Sequence (CRC) www.ti.com Architecture 2.4 Ethernet Protocol Overview A brief overview of the Ethernet protocol is given in the following subsections. See the IEEE 802....

Architecture www.ti.com 2.4.2 Ethernet’s Multiple Access Protocol Nodes in an Ethernet Local Area Network are interconnected by a broadcast channel -- when an EMACport transmits a frame, all the adapters on the local network receive the frame. Carrier Sense MultipleAccess with Collision Detection (C...

SOP | EOP 60 0 60 pBuffer pNext Packet A 60 bytes 0 SOP Fragment 1 Packet B 512 1514 pBuffer pNext 512 bytes EOP 0 0 −−− Packet B Fragment 3 500 bytes 502 pBuffer −−− 500 pNext −−− pBuffer pNext Packet B Fragment 2 502 bytes SOP | EOP 0 1514 bytes Packet C 1514 pBuffer pNext (NULL) 1514 www.ti.com A...

Architecture www.ti.com 2.5.2 Transmit and Receive Descriptor Queues The EMAC module processes descriptors in linked lists as discussed in Section 2.5.1 . The lists used by the EMAC are maintained by the application software through the use of the head descriptor pointerregisters (HDP). The EMAC sup...

www.ti.com Architecture 2.5.3 Transmit and Receive EMAC Interrupts The EMAC processes descriptors in linked list chains as discussed in Section 2.5.1 , using the linked list queue mechanism discussed in Section 2.5.2 . The EMAC synchronizes descriptor list processing through the use of interrupts to...

Architecture www.ti.com Figure 7. Transmit Buffer Descriptor Format Word 0 31 0 Next Descriptor Pointer Word 1 31 0 Buffer Pointer Word 2 31 16 15 0 Buffer Offset Buffer Length Word 3 31 30 29 28 27 26 25 16 SOP EOP OWNER EOQ TDOWNCMPLT PASSCRC Reserved 15 0 Packet Length Example 1. Transmit Buffer ...

www.ti.com Architecture 2.5.4.1 Next Descriptor Pointer The next descriptor pointer points to the 32-bit word aligned memory address of the next buffer descriptorin the transmit queue. This pointer is used to create a linked list of buffer descriptors. If the value of thispointer is zero, then the c...

www.ti.com Architecture 2.5.5 Receive Buffer Descriptor Format A receive (RX) buffer descriptor ( Figure 8 ) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 2 shows the receive buffer descriptor described by a C struc...

Architecture www.ti.com Example 2. Receive Buffer Descriptor in C Structure Format /* // EMAC Descriptor // // The following is the format of a single buffer descriptor // on the EMAC. */ typedef struct _EMAC_Desc { struct _EMAC_Desc *pNext; /* Pointer to next descriptor in chain */ Uint8 *pBuffer; ...

www.ti.com Architecture 2.5.5.4 Buffer Length This 16-bit field is used for two purposes:• Before the descriptor is first placed on the receive queue by the application software, the buffer lengthfield is first initialized by the software to have the physical size of the empty data buffer pointed to...

Arbiter and bus switches CPU DMA Controllers 8K byte descriptor memory Configuration registers Interrupt logic Interruptsto CPU EMAC interrupts MDIO interrupts Configuration bus Transmit and Receive www.ti.com Architecture 2.6 EMAC Control Module The EMAC control module ( Figure 9 ) interfaces the E...

Architecture www.ti.com 2.6.3 Interrupt Control Interrupt conditions generated by the EMAC and MDIO modules are combined into four interrupt signalsthat are routed to three independent interrupt cores in the EMAC control module; the interrupt cores thenrelay the interrupt signals to the CPU interrup...

EMAC control module Control registers and logic PHY monitoring Peripheral clock MDIO clock generator USERINT MDIO interface polling PHY MDCLK MDIO LINKINT Configuration bus www.ti.com Architecture Figure 10. MDIO Module Block Diagram 2.7.1.1 MDIO Clock Generator The MDIO clock generator controls the...

Architecture www.ti.com 2.7.2 MDIO Module Operational Overview The MDIO module implements the 802.3 serial management interface to interrogate and control anEthernet PHY, using a shared two-wired bus. It separately performs autodetection and records the currentlink status of up to 32 PHYs, polling a...

www.ti.com Architecture 2.7.2.1 Initializing the MDIO Module The following steps are performed by the application software or device driver to initialize the MDIOdevice: 1. Configure the PREAMBLE and CLKDIV bits in the MDIO control register (CONTROL).2. Enable the MDIO module by setting the ENABLE b...

Architecture www.ti.com 2.7.2.4 Example of MDIO Register Access Code The MDIO module uses the MDIO user access register (USERACCESSn) to access the PHY controlregisters. Software functions that implement the access process may simply be the following four macros: • PHYREG_read( regadr, phyadr ) Star...

Clock and reset logic Receive DMA engine Interrupt controller Transmit DMA engine Control registers Configuration bus EMAC control module Configuration bus RAM State FIFO Receive FIFO Transmit MAC transmitter Statistics receiver MAC SYNC MII address Receive RMII www.ti.com Architecture 2.8 EMAC Modu...

Architecture www.ti.com 2.8.1.4 Transmit DMA Engine The transmit DMA engine is the interface between the transmit FIFO and the CPU. It interfaces to theCPU through the bus arbiter in the EMAC control module. 2.8.1.5 Transmit FIFO The transmit FIFO consists of three cells of 64-bytes each and associa...

www.ti.com Architecture The EMAC module operates independently of the CPU. It is configured and controlled by its register setmapped into device memory. Information about data packets is communicated by use of 16-bytedescriptors that are placed in an 8K-byte block of RAM in the EMAC control module (...

Architecture www.ti.com In either case, receive flow control prevents frame reception by issuing the flow control appropriate for thecurrent mode of operation. Receive flow control prevents reception of frames on the EMAC until all of thetriggering conditions clear, at which time frames may again be...

www.ti.com Architecture 2.9.2 Data Transmission The EMAC passes data to the PHY from the transmit FIFO (when enabled). Data is synchronized to thetransmit clock rate. Transmission begins when there are TXCELLTHRESH cells of 64 bytes each, or acomplete packet, in the FIFO. 2.9.2.1 Transmit Control A ...

Architecture www.ti.com 2.9.2.6 Transmit Flow Control Incoming pause frames are acted upon, when enabled, to prevent the EMAC from transmitting any furtherframes. Incoming pause frames are only acted upon when the FULLDUPLEX and TXFLOWEN bits in theMAC control register (MACCONTROL) are set. Pause fr...

www.ti.com Architecture 2.10 Packet Receive Operation 2.10.1 Receive DMA Host Configuration To configure the receive DMA for operation the host must: • Initialize the receive addresses. • Initialize the receive channel n DMA head descriptor pointer registers (RXnHDP) to 0. • Write the MAC address ha...

Architecture www.ti.com 2.10.4 Hardware Receive QOS Support Hardware receive quality of service (QOS) is supported, when enabled, by the Tag Protocol Identifierformat and the associated Tag Control Information (TCI) format priority field. When the incoming framelength/type value is equal to 81.00h, ...

www.ti.com Architecture 2.10.7 Receive Frame Classification Received frames are proper (good) frames, if they are between 64 bytes and the value in the receivemaximum length register (RXMAXLEN) bytes in length (inclusive) and contain no code, align, or CRCerrors. Received frames are long frames, if ...

Architecture www.ti.com Table 5. Receive Frame Treatment Summary Address Match RXCAFEN RXCEFEN RXCMFEN RXCSFEN Receive Frame Treatment 0 0 X X X No frames transferred. 0 1 0 0 0 Proper frames transferred to promiscuous channel. 0 1 0 0 1 Proper/undersized data frames transferred topromiscuous channe...

www.ti.com Architecture 2.10.9 Receive Overrun The types of receive overrun are: • FIFO start of frame overrun (FIFO_SOF) • FIFO middle of frame overrun (FIFO_MOF) • DMA start of frame overrun (DMA_SOF) • DMA middle of frame overrun (DMA_MOF) The statistics counters used to track these types of rece...

Architecture www.ti.com 2.11 Packet Transmit Operation The transmit DMA is an eight channel interface. Priority between the eight queues may be either fixed orround-robin as selected by the TXPTYPE bit in the MAC control register (MACCONTROL). If the prioritytype is fixed, then channel 7 has the hig...

www.ti.com Architecture 2.12 Receive and Transmit Latency The transmit and receive FIFOs each contain three 64-byte cells. The EMAC begins transmission of apacket on the wire after TXCELLTHRESH (configurable through the FIFO control register) cells, or acomplete packet, are available in the FIFO. Tr...

Architecture www.ti.com 2.14 Reset Considerations 2.14.1 Software Reset Considerations Peripheral clock and reset control is done through the Power and Sleep Controller (PSC) module includedwith the device. For more on how the EMAC, MDIO, and EMAC control module are disabled or placed inreset at run...

www.ti.com Architecture 2.15 Initialization 2.15.1 Enabling the EMAC/MDIO Peripheral When the device is powered on, the EMAC peripheral may be in a disabled state. Before any EMACspecific initialization can take place, the EMAC needs to be enabled; otherwise, its registers cannot bewritten and the r...

Architecture www.ti.com 2.15.4 EMAC Module Initialization The EMAC module is used to send and receive data packets over the network. This is done bymaintaining up to eight transmit and receive descriptor queues. The EMAC module configuration mustalso be kept up-to-date based on PHY negotiation resul...

www.ti.com Architecture 2.16 Interrupt Support 2.16.1 EMAC Module Interrupt Events and Requests The EMAC module generates 26 interrupt events:• TXPENDn: Transmit packet completion interrupt for transmit channels 0 through 7 • RXPENDn: Receive packet completion interrupt for receive channels 0 throug...

Architecture www.ti.com When the EMAC completes a packet reception, the EMAC issues an interrupt to the CPU by writing thepacket's last buffer descriptor address to the appropriate channel queue's receive completion pointerlocated in the state RAM block. The interrupt is generated by the write when ...

www.ti.com Architecture The receive host error conditions are:• Ownership bit not set in input buffer • Zero buffer pointer The application software must acknowledge the EMAC control module after receiving host error interruptsby writing the appropriate CnMISC key to the EMAC End-Of-Interrupt Vector...

Architecture www.ti.com 2.16.2.2 User Access Completion Interrupt When the GO bit in one of the MDIO register USERACCESS0 transitions from 1 to 0 (indicatingcompletion of a user access) and the corresponding USERINTMASKSET bit in the MDIO user commandcomplete interrupt mask set register (USERINTMASK...

www.ti.com Architecture 2.17 Power Management Each of the three main components of the EMAC peripheral can independently be placed inreduced-power modes to conserve power during periods of low activity. The power management of theEMAC peripheral is controlled by the processor Power and Sleep Control...

EMAC Control Module Registers www.ti.com 3 EMAC Control Module Registers Table 8 lists the memory-mapped registers for the EMAC control module. See your device-specific data manual for the memory address of these registers. Table 8. EMAC Control Module Registers Offset Acronym Register Description S...

www.ti.com EMAC Control Module Registers Table 8. EMAC Control Module Registers (continued) Offset Acronym Register Description Section 70h C0RXIMAX EMAC Control Module Interrupt Core 0 Receive Interrupts Per Section 3.12 Millisecond Register 74h C0TXIMAX EMAC Control Module Interrupt Core 0 Transmi...

EMAC Control Module Registers www.ti.com 3.2 EMAC Control Module Software Reset Register (SOFTRESET) The EMAC Control Module Software Reset Register (SOFTRESET) is shown in Figure 13 and described in Table 10 . Figure 13. EMAC Control Module Software Reset Register (SOFTRESET) 31 16 Reserved R-0 15 ...

www.ti.com EMAC Control Module Registers 3.3 EMAC Control Module Interrupt Control Register (INTCONTROL) The EMAC control module interrupt control register (INTCONTROL) is shown in Figure 14 and described in Table 11 . The settings in the INTCONTROL register are used in conjunction with the CnRXIMAX...

EMAC Control Module Registers www.ti.com 3.4 EMAC Control Module Interrupt Core Receive Threshold Interrupt Enable Registers(C0RXTHRESHEN-C2RXTHRESHEN) The EMAC control module interrupt core 0-2 receive threshold interrupt enable register(CnRXTHRESHEN) is shown in Figure 15 and described in Table 12...

MDIO Registers www.ti.com 4 MDIO Registers Table 22 lists the memory-mapped registers for the MDIO module. See your device-specific data manual for the memory address of these registers. Table 22. Management Data Input/Output (MDIO) Registers Offset Acronym Register Description Section 0h REVID MDIO...

www.ti.com MDIO Registers 4.2 MDIO Control Register (CONTROL) The MDIO control register (CONTROL) is shown in Figure 26 and described in Table 24 . Figure 26. MDIO Control Register (CONTROL) 31 30 29 28 24 23 21 20 19 18 17 16 IDLE ENABLE Rsvd HIGHEST_USER_CHANNEL Reserved PREAMBLE FAULT FAULTENB Re...

MDIO Registers www.ti.com 4.3 PHY Acknowledge Status Register (ALIVE) The PHY acknowledge status register (ALIVE) is shown in Figure 27 and described in Table 25 . Figure 27. PHY Acknowledge Status Register (ALIVE) 31 0 ALIVE R/W1C-0 LEGEND: R/W = Read/Write; W1C = Write 1 to clear (writing a 0 has ...

www.ti.com MDIO Registers 4.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) The MDIO link status change interrupt (unmasked) register (LINKINTRAW) is shown in Figure 29 and described in Table 27 . Figure 29. MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) 31 1...

MDIO Registers www.ti.com 4.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) The MDIO user command complete interrupt mask clear register (USERINTMASKCLEAR) is shown in Figure 34 and described in Table 32 . Figure 34. MDIO User Command Complete Interrupt Mask Clear Regi...

www.ti.com MDIO Registers 4.11 MDIO User Access Register 0 (USERACCESS0) The MDIO user access register 0 (USERACCESS0) is shown in Figure 35 and described in Table 33 . Figure 35. MDIO User Access Register 0 (USERACCESS0) 31 30 29 28 26 25 21 20 16 GO WRITE ACK Reserved REGADR PHYADR R/W1S-0 R/W-0 R...

MDIO Registers www.ti.com 4.12 MDIO User PHY Select Register 0 (USERPHYSEL0) The MDIO user PHY select register 0 (USERPHYSEL0) is shown in Figure 36 and described in Table 34 . Figure 36. MDIO User PHY Select Register 0 (USERPHYSEL0) 31 16 Reserved R-0 15 8 7 6 5 4 0 Reserved LINKSEL LINKINTENB Rsvd...

www.ti.com MDIO Registers 4.13 MDIO User Access Register 1 (USERACCESS1) The MDIO user access register 1 (USERACCESS1) is shown in Figure 37 and described in Table 35 . Figure 37. MDIO User Access Register 1 (USERACCESS1) 31 30 29 28 26 25 21 20 16 GO WRITE ACK Reserved REGADR PHYADR R/W1S-0 R/W-0 R...

MDIO Registers www.ti.com 4.14 MDIO User PHY Select Register 1 (USERPHYSEL1) The MDIO user PHY select register 1 (USERPHYSEL1) is shown in Figure 38 and described in Table 36 . Figure 38. MDIO User PHY Select Register 1 (USERPHYSEL1) 31 16 Reserved R-0 15 8 7 6 5 4 0 Reserved LINKSEL LINKINTENB Rsvd...

www.ti.com EMAC Module Registers 5 EMAC Module Registers Table 37 lists the memory-mapped registers for the EMAC. See your device-specific data manual for the memory address of these registers. Table 37. Ethernet Media Access Controller (EMAC) Registers Offset Acronym Register Description Section 0h...

EMAC Module Registers www.ti.com 5.1 Transmit Revision ID Register (TXREVID) The transmit revision ID register (TXREVID) is shown in Figure 39 and described in Table 38 . Figure 39. Transmit Revision ID Register (TXREVID) 31 0 TXREV R-4EC0 020Dh LEGEND: R = Read only; -n = value after reset Table 38...

www.ti.com EMAC Module Registers 5.3 Transmit Teardown Register (TXTEARDOWN) The transmit teardown register (TXTEARDOWN) is shown in Figure 41 and described in Table 40 . Figure 41. Transmit Teardown Register (TXTEARDOWN) 31 16 Reserved R-0 15 3 2 0 Reserved TXTDNCH R-0 R/W-0 LEGEND: R/W = Read/Writ...

EMAC Module Registers www.ti.com 5.4 Receive Revision ID Register (RXREVID) The receive revision ID register (RXREVID) is shown in Figure 42 and described in Table 41 . Figure 42. Receive Revision ID Register (RXREVID) 31 0 RXREV R-4EC0 020Dh LEGEND: R = Read only; -n = value after reset Table 41. R...

www.ti.com EMAC Module Registers 5.6 Receive Teardown Register (RXTEARDOWN) The receive teardown register (RXTEARDOWN) is shown in Figure 44 and described in Table 43 . Figure 44. Receive Teardown Register (RXTEARDOWN) 31 16 Reserved R-0 15 3 2 0 Reserved RXTDNCH R-0 R/W-0 LEGEND: R/W = Read/Write; ...

EMAC Module Registers www.ti.com 5.9 Transmit Interrupt Mask Set Register (TXINTMASKSET) The transmit interrupt mask set register (TXINTMASKSET) is shown in Figure 47 and described in Table 46 . Figure 47. Transmit Interrupt Mask Set Register (TXINTMASKSET) 31 16 Reserved R-0 15 8 Reserved R-0 7 6 5...

EMAC Module Registers www.ti.com 5.11 MAC Input Vector Register (MACINVECTOR) The MAC input vector register (MACINVECTOR) is shown in Figure 49 and described in Table 48 . Figure 49. MAC Input Vector Register (MACINVECTOR) 31 28 27 26 25 24 23 16 Reserved STATPEND HOSTPEND LINKINT0 USERINT0 TXPEND R...

www.ti.com EMAC Module Registers 5.12 MAC End Of Interrupt Vector Register (MACEOIVECTOR) The MAC end of interrupt vector register (MACEOIVECTOR) is shown in Figure 50 and described in Table 49 . Figure 50. MAC End Of Interrupt Vector Register (MACEOIVECTOR) 31 16 Reserved R-0 15 5 4 0 Reserved INTV...

EMAC Module Registers www.ti.com 5.15 Receive Interrupt Mask Set Register (RXINTMASKSET) The receive interrupt mask set register (RXINTMASKSET) is shown in Figure 53 and described in Table 52 . Figure 53. Receive Interrupt Mask Set Register (RXINTMASKSET) 31 16 Reserved R-0 15 14 13 12 11 10 9 8 RX7...

www.ti.com EMAC Module Registers 5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) The receive interrupt mask clear register (RXINTMASKCLEAR) is shown in Figure 54 and described in Table 53 . Figure 54. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) 31 16 Reserved R-0 15 14 13 12 1...

www.ti.com EMAC Module Registers 5.19 MAC Interrupt Mask Set Register (MACINTMASKSET) The MAC interrupt mask set register (MACINTMASKSET) is shown in Figure 57 and described in Table 56 . Figure 57. MAC Interrupt Mask Set Register (MACINTMASKSET) 31 16 Reserved R-0 15 2 1 0 Reserved HOSTMASK STATMAS...

www.ti.com EMAC Module Registers 5.22 Receive Unicast Enable Set Register (RXUNICASTSET) The receive unicast enable set register (RXUNICASTSET) is shown in Figure 60 and described in Table 59 . Figure 60. Receive Unicast Enable Set Register (RXUNICASTSET) 31 16 Reserved R-0 15 8 Reserved R-0 7 6 5 4...

EMAC Module Registers www.ti.com 5.23 Receive Unicast Clear Register (RXUNICASTCLEAR) The receive unicast clear register (RXUNICASTCLEAR) is shown in Figure 61 and described in Table 60 . Figure 61. Receive Unicast Clear Register (RXUNICASTCLEAR) 31 16 Reserved R-0 15 8 Reserved R-0 7 6 5 4 3 2 1 0 ...

www.ti.com EMAC Module Registers 5.24 Receive Maximum Length Register (RXMAXLEN) The receive maximum length register (RXMAXLEN) is shown in Figure 62 and described in Table 61 . Figure 62. Receive Maximum Length Register (RXMAXLEN) 31 16 Reserved R-0 15 0 RXMAXLEN R/W-5EEh LEGEND: R/W = Read/Write; ...

EMAC Module Registers www.ti.com 5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) The receive filter low priority frame threshold register (RXFILTERLOWTHRESH) is shown in Figure 64 and described in Table 63 . Figure 64. Receive Filter Low Priority Frame Threshold Registe...

EMAC Module Registers www.ti.com 5.29 MAC Control Register (MACCONTROL) The MAC control register (MACCONTROL) is shown in Figure 67 and described in Table 66 . Figure 67. MAC Control Register (MACCONTROL) 31 16 Reserved R-0 15 14 13 12 11 10 9 8 RMIISPEED RXOFFLENBLOCK RXOWNERSHIP Rsvd CMDIDLE TXSHO...

EMAC Module Registers www.ti.com 5.30 MAC Status Register (MACSTATUS) The MAC status register (MACSTATUS) is shown in Figure 68 and described in Table 67 . Figure 68. MAC Status Register (MACSTATUS) 31 30 24 23 20 19 18 16 IDLE Reserved TXERRCODE Rsvd TXERRCH R-0 R-0 R-0 R-0 R-0 15 12 11 10 8 RXERRC...

EMAC Module Registers www.ti.com 5.31 Emulation Control Register (EMCONTROL) The emulation control register (EMCONTROL) is shown in Figure 69 and described in Table 68 . Figure 69. Emulation Control Register (EMCONTROL) 31 16 Reserved R-0 15 2 1 0 Reserved SOFT FREE R-0 R/W-0 R/W-0 LEGEND: R/W = Rea...

www.ti.com EMAC Module Registers 5.33 MAC Configuration Register (MACCONFIG) The MAC configuration register (MACCONFIG) is shown in Figure 71 and described in Table 70 . Figure 71. MAC Configuration Register (MACCONFIG) 31 24 23 16 TXCELLDEPTH RXCELLDEPTH R-3h R-3h 15 8 7 0 ADDRESSTYPE MACCFIG R-2h ...

EMAC Module Registers www.ti.com 5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) The MAC source address low bytes register (MACSRCADDRLO) is shown in Figure 73 and described in Table 72 . Figure 73. MAC Source Address Low Bytes Register (MACSRCADDRLO) 31 16 Reserved R-0 15 8 7 0 MACSRCADDR...

www.ti.com EMAC Module Registers 5.37 MAC Hash Address Register 1 (MACHASH1) The MAC hash registers allow group addressed frames to be accepted on the basis of a hash function ofthe address. The hash function creates a 6-bit data value (Hash_fun) from the 48-bit destination address(DA) as follows: H...

EMAC Module Registers www.ti.com 5.39 Back Off Test Register (BOFFTEST) The back off test register (BOFFTEST) is shown in Figure 77 and described in Table 76 . Figure 77. Back Off Random Number Generator Test Register (BOFFTEST) 31 26 25 16 Reserved RNDNUM R-0 R-0 15 12 11 10 9 0 COLLCOUNT Reserved ...

www.ti.com EMAC Module Registers 5.41 Receive Pause Timer Register (RXPAUSE) The receive pause timer register (RXPAUSE) is shown in Figure 79 and described in Table 78 . Figure 79. Receive Pause Timer Register (RXPAUSE) 31 16 Reserved R-0 15 0 PAUSETIMER R-0 LEGEND: R = Read only; -n = value after r...

www.ti.com EMAC Module Registers 5.44 MAC Address High Bytes Register (MACADDRHI) The MAC address high bytes register (MACADDRHI) is shown in Figure 82 and described in Table 81 . Figure 82. MAC Address High Bytes Register (MACADDRHI) 31 24 23 16 MACADDR2 MACADDR3 R/W-x R/W-x 15 8 7 0 MACADDR4 MACAD...

EMAC Module Registers www.ti.com 5.50 Network Statistics Registers The EMAC has a set of statistics that record events associated with frame traffic. The statistics values arecleared to zero 38 clocks after the rising edge of reset. When the GMIIEN bit in the MACCONTROLregister is set, all statistic...

www.ti.com EMAC Module Registers 5.50.4 Pause Receive Frames Register (RXPAUSEFRAMES) The total number of IEEE 802.3X pause frames received by the EMAC (whether acted upon or not). Apause frame is defined as having all of the following: • Contained any unicast, broadcast, or multicast address • Cont...

EMAC Module Registers www.ti.com 5.50.7 Receive Oversized Frames Register (RXOVERSIZED) The total number of oversized frames received on the EMAC. An oversized frame is defined as having allof the following: • Was any data or MAC control frame that matched a unicast, broadcast, or multicast address,...

EMAC Module Registers www.ti.com 5.50.25 Transmit Carrier Sense Errors Register (TXCARRIERSENSE) The total number of frames on the EMAC that experienced carrier loss. Such a frame is defined as havingall of the following: • Was any data or MAC control frame destined for any unicast, broadcast, or mu...

www.ti.com EMAC Module Registers 5.50.30 Transmit and Receive 256 to 511 Octet Frames Register (FRAME256T511) The total number of 256-byte to 511-byte frames received and transmitted on the EMAC. Such a frame isdefined as having all of the following: • Any data or MAC control frame that was destined...

www.ti.com Appendix A Glossary Broadcast MAC Address— A special Ethernet MAC address used to send data to all Ethernet devices on the local network. The broadcast address is FFh-FFh-FFh-FFh-FFh-FFh. The LSB of the firstbyte is odd, qualifying it as a group address; however, its value is reserved for...

Appendix A www.ti.com Multicast MAC Address— A class of MAC address that sends a packet to potentially more than one recipient. A group address is specified by setting the LSB of the first MAC address byte to 1. Thus,01h-02h-03h-04h-05h-06h is a valid multicast address. Typically, an Ethernet MAC lo...

www.ti.com Appendix B Revision History Table 88 lists the changes made since the previous version of this document. Table 88. Document Revision History Reference Additions/Modifications/Deletions Figure 2 Changed figure. Section 2.5.2 Changed first paragraph. Section 2.5.3 Changed third paragraph. 1...

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