Page 3 - Contents
Contents Preface ........................................................................................................................................ 8 1 Features .............................................................................................................................. 9 2 In...
Page 8 - Read This First; About This Manual; — TMS320C6000 DSP CPU and Instruction Set Reference Guide.; Trademarks
Preface SPRUGK1 – March 2009 Read This First About This Manual Channel decoding of high bit-rate data channels found in third-generation (3G) cellular standards requiresdecoding of turbo-encoded data. The turbo-decoder coprocessor (TCP2) in some of the digital signalprocessors (DSPs) of the TMS320C6...
Page 9 - Features
1 Features User's Guide SPRUGK1 – March 2009 TMS320C6457 Turbo-Decoder Coprocessor 2 Channel decoding of high bit-rate data channels found in third-generation (3G) cellular standards requiresdecoding of turbo-encoded data. The turbo-decoder coprocessor (TCP2) in some of the digital signalprocessor (...
Page 10 - Introduction; Encoding is done as shown in; Figure 1. 3GPP and IS2000 Turbo-Encoder Block Diagram; Figure 2
2 Introduction z −1 z −1 z −1 B A X z −1 z −1 z −1 B’ A’ X’ Interleaver Puncture and repetition X P1 P2 P3 Information Switches in upper position for information bits and in lower position for tail bits Introduction www.ti.com Encoding is done as shown in Figure 1 . The 3GPP and IS2000 turbo encoder...
Page 11 - Overview; a priori; Figure 2. 3GPP and IS2000 Turbo-Decoder Block Diagram; Figure 3
MAP1 MAP2 Received systematics Interleave Deinterleave A priori Interleave A priori Received systematics Received parities Received parities A’ & B ’ symbols Hard decisions calculation Decoded bits X’ symbols information X symbols A & B symbols information 3 Overview www.ti.com Overview uses...
Page 12 - Figure 3. TCP2 Block Diagram; Figure 4
32-bit configuration bus 64-bit EDMA3 bus Turbo-decoder coprocessor (TCP2) REVT/XEVT generation CPU interrupt generation TCP2 control EDMA3 I/F unit Memory block Processing unit TCP2_INT TCPXEVT TCPREVT 4 Standalone (SA) Mode Standalone (SA) Mode www.ti.com Figure 3. TCP2 Block Diagram Table 1. Fram...
Page 13 - Input Data Format; Systematic and Parity Data
Parity A Parity A’ Parity B Parity B’ Void input I I I −1 Apriori 1 Apriori 2 Systematic Stop? (stopping criterion algo) New apriori Previous apriori Yes Systematic No Slicer Create hard decisions End MAP decoder unit Extrinsicsavedas newapriori Keep on iterations Enable next log−map by switching th...
Page 16 - Interleaver Indexes; Output Decision Data Format; interleaver table; Table 2. Interleaver Data
4.1.2 Interleaver Indexes 4.2 Output Decision Data Format 4.3 Stopping Criteria Standalone (SA) Mode www.ti.com Figure 15. Rate 3/4 EN = 0 (Big-Endian Mode) Rate = 3/4 Word Word N N + 1 SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5 0 0 0 A0 X0 0 0 0 0 X1 Word Word N + 2 N + 3 SP4 SP3 SP2 SP1 SP0 SP9 SP8 S...
Page 17 - Stopping Test Unit; SNR Threshold Termination
4.4 Stopping Test Unit 4.4.1 SNR Threshold Termination 4.4.2 CRC Termination www.ti.com Standalone (SA) Mode The CRC-based stopping criterion can be used by setting the CRC polynomial length (CRCLEN) and thenumber of CRC iterations required to pass CRCITERPASS. After each iteration, hard decisions a...
Page 18 - Parameter Termination; Maximum Iterations
4.4.3 Parameter Termination 4.4.3.1 Maximum Iterations 4.4.3.2 Minimum Iterations 5 Shared-Processing (SP) Mode Shared-Processing (SP) Mode www.ti.com The CRC will process one sub-block at time using the data stored from the previous sub-block. Thedecision bit will be used by a CRC block. After all ...
Page 20 - Figure 17. Subframe Equations
Num Subframe + CEIL ǒ Size Block Size MAX_Subframe Ǔ Size Subframe + CEIL ǒ Size Block 256 Num Subframe Ǔ 256 while ǒ Size Block u Size MAX_Subsystem Ǔ { Size Block + Size Block * Size Subframe if( Size Block u 128) } Size Last_Subframe + Size Block if( Size Block v 128) Num Subframe + Num Subframe ...
Page 22 - . The DSP has to split
MAP decoder unit MAP 1: Parity A or MAP 2: Parity A’ MAP 2: Parity B’ MAP 1: Parity B or Void input MAP 1: Systemic or MAP 2: Interleaved (systematic) MAP 1: De−interlaced (Apriori 2) or MAP 2: Interleaved (Apriori 1) MAP 1: Apriori 1 or MAP 2: Apriori 2 Extrinsic saved as apriori 5.1 Input Data For...
Page 24 - A Priori Data; Output Data Format; A priori data for MAP0 and MAP1 must be organized as described in; Figure 31. A Priori Data
5.1.2 A Priori Data 5.2 Output Data Format Shared-Processing (SP) Mode www.ti.com Figure 28. EN = 0 (Big-Endian Mode) Rate = 1/5 Word Word N N + 1 SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5 B0' A0' B0 A0 X0 B1' A1' B1 A1 X1 Word Word N + 2 N + 3 SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5 B2' A2 B2 A2 X2 B...
Page 25 - Registers; The memory map is listed in; Table 3. TCP2 Registers
6 Registers www.ti.com Registers The TCP2 contains several memory-mapped registers accessible via the CPU, QDMA, and EDMA3. Aperipheral-bus access is faster than an EDMA3-bus access for isolated accesses (typically whenaccessing control registers). EDMA3-bus accesses are intended to be used for EDMA...
Page 27 - and described in
6.1 Peripheral Identification Register (PID) www.ti.com Registers The peripheral identification register (PID) is a constant register that contains the ID and ID revisionnumber for that peripheral. The PID stores version information used to identify the peripheral. All bitswithin this register are r...
Page 28 - TCP2 Input Configuration Register 0 (TCPIC0); The TCP2 input configuration register 0 (TCPIC0) is shown in
6.2 TCP2 Input Configuration Register 0 (TCPIC0) Registers www.ti.com The TCP2 input configuration register 0 (TCPIC0) is shown in Figure 33 and described in Table 6 . TCPIC0 configures the TCP. Figure 33. TCP2 Input Configuration Register 0 (TCPIC0) 31 30 16 Rsvd FL R/W-0 R/W-0 15 14 13 12 11 10 8 ...
Page 29 - The TCP2 input configuration register 1 (TCPIC1) is shown in
6.3 TCP2 Input Configuration Register 1 (TCPIC1) 6.4 TCP2 Input Configuration Register 2 (TCPIC2) www.ti.com Registers The TCP2 input configuration register 1 (TCPIC1) is shown in Figure 34 and described in Table 7 . TCPIC1 configures the TCP. Figure 34. TCP2 Input Configuration Register 1 (TCPIC1) ...
Page 30 - TCP2 Input Configuration Register 3 (TCPIC3); The TCP2 input configuration register 3 (TCPIC3) is shown in
6.5 TCP2 Input Configuration Register 3 (TCPIC3) Registers www.ti.com The TCP2 input configuration register 3 (TCPIC3) is shown in Figure 36 and described in Table 9 . TCPIC3 informs the TCP2 on the EDMA3 data flow segmentation. Figure 36. TCP2 Input Configuration Register 3 (TCPIC3) 31 16 Reserved ...
Page 31 - TCP2 Input Configuration Register 4 (TCPIC4); The TCP2 input configuration register 4 (TCPIC4) is shown in
6.6 TCP2 Input Configuration Register 4 (TCPIC4) www.ti.com Registers The TCP2 input configuration register 4 (TCPIC4) is shown in Figure 37 and described in Table 10 . TCPIC4 informs the TCP2 on the EDMA3 data flow segmentation. Figure 37. TCP2 Input Configuration Register 4 (TCPIC4) 31 16 Reserved...
Page 32 - The TCP2 input configuration register 5 (TCPIC5) is shown in; Table 12. CRC Examples
6.7 TCP2 Input Configuration Register 5 (TCPIC5) 6.8 Tail Symbols Registers www.ti.com The TCP2 input configuration register 5 (TCPIC5) is shown in Figure 38 and described in Table 11 . TCPIC5 provides the 32-bit CRC Polynomial to TCP2. Figure 38. TCP2 Input Configuration Register 5 (TCPIC5) 31 0 CR...
Page 33 - TCP2 Input Configuration Register 6 (TCPIC6); The TCP2 input configuration register 6 (TCPIC6) is shown in; CDMA-2000 Tail Symbol Pattern for Code Rate 1/5
6.9 TCP2 Input Configuration Register 6 (TCPIC6) www.ti.com Registers The TCP2 input configuration register 6 (TCPIC6) is shown in Figure 39 and described in Table 13 . TCPIC6 sets the tail bits used by the TCP. Figure 39. TCP2 Input Configuration Register 6 (TCPIC6) 31 18 17 0 Reserved TAIL1 R/W-0 ...
Page 34 - The TCP2 input configuration register 7 (TCPIC7) is shown in; CDMA-2000 Tail Symbol Pattern for Code Rate 1/4
6.10 TCP2 Input Configuration Register 7 (TCPIC7) Registers www.ti.com The TCP2 input configuration register 7 (TCPIC7) is shown in Figure 40 and described in Table 14 . TCPIC7 sets set the tail bits used by the TCP. Figure 40. TCP2 Input Configuration Register 7 (TCPIC7) 31 18 17 0 Reserved TAIL2 R...
Page 36 - The TCP2 input configuration register 9 (TCPIC9) is shown in
6.12 TCP2 Input Configuration Register 9 (TCPIC9) Registers www.ti.com The TCP2 input configuration register 9 (TCPIC9) is shown in Figure 42 and described in Table 16 . TCPIC9 sets the tail bits used by the TCP. Figure 42. CP2 Input Configuration Register 9 (TCPIC9) 31 18 17 0 Reserved TAIL4 R/W-0 ...
Page 39 - The TCP2 input configuration register 12 (TCPIC12) is shown in
6.15 TCP2 Input Configuration Register 12 (TCPIC12) 6.16 TCP2 Input Configuration Register 13 (TCPIC13) www.ti.com Registers The TCP2 input configuration register 12 (TCPIC12) is shown in Figure 45 and described in Table 19 . Figure 45. TCP2 Input Configuration Register 12 (TCPIC12) 31 24 23 0 Reser...
Page 40 - The TCP2 input configuration register 14 (TCPIC14) is shown in
6.17 TCP2 Input Configuration Register 14 (TCPIC14) Registers www.ti.com The TCP2 input configuration register 14 (TCPIC14) is shown in Figure 47 and described in Table 21 . Figure 47. TCP2 Input Configuration Register 14 (TCPIC14) 31 24 23 0 Reserved EXT_SCALE_8_11 R/W-0 R/W-0 LEGEND: R/W = Read/Wr...
Page 41 - The TCP2 input configuration register 15 (TCPIC15) is shown in; Table 23. Extrinsic Scale Registers
6.18 TCP2 Input Configuration Register 15 (TCPIC15) www.ti.com Registers The TCP2 input configuration register 15 (TCPIC15) is shown in Figure 48 and described in Table 22 . Figure 48. TCP2 Input Configuration Register 15 (TCPIC15) 31 24 23 0 Reserved EXT_SCALE_12_15 R/W-0 R/W-0 LEGEND: R/W = Read/W...
Page 42 - The TCP2 output parameter register 0 (TCPOUT0) is shown in
6.19 TCP2 Output Parameter Register 0 (TCPOUT0) 6.20 TCP2 Output Parameter Register 1 (TCPOUT1) Registers www.ti.com The TCP2 output parameter register 0 (TCPOUT0) is shown in Figure 49 and described in Table 24 . Figure 49. TCP2 Output Parameter Register 0 (TCPOUT0) 31 29 28 24 23 20 19 0 Reserved ...
Page 43 - The TCP2 output parameter register 2 (TCPOUT2) is shown in; Table 27. TCP2 Execution Register (TCPEXE) Field Descriptions
6.21 TCP2 Output Parameter Register 2 (TCPOUT2) 6.22 TCP2 Execution Register (TCPEXE) www.ti.com Registers The TCP2 output parameter register 2 (TCPOUT2) is shown in Figure 51 and described in Table 26 . Figure 51. TCP2 Output Parameter Register 2 (TCPOUT2) 31 16 15 0 CNT_RE_MAP1 CNT_RE_MAP0 R/W-0 R...
Page 44 - The TCP2 endian register (TCPEND) is shown in
6.23 TCP2 Endian Register (TCPEND) Registers www.ti.com The TCP2 endian register (TCPEND) is shown in Figure 53 and described in Table 28 . TCPEND should only be used when the DSP is set to big-endian mode. Figure 53. TCP2 Endian Register (TCPEND) 31 8 Reserved R/W-0 7 2 1 0 ENDIAN_ ENDIAN_ Reserved...
Page 45 - The TCP2 error register (TCPERR) is shown in
6.24 TCP2 Error Register (TCPERR) www.ti.com Registers The TCP2 error register (TCPERR) is shown in Figure 54 and described in Table 29 . In case of an error, the coprocessor sends an interrupt to the C6457 CPU. The following errors are feedback in the error word. Figure 54. TCP2 Error Register (TCP...
Page 47 - The TCP2 status register (TCPSTAT) is shown in
6.25 TCP2 Status Register (TCPSTAT) www.ti.com Registers The TCP2 status register (TCPSTAT) is shown in Figure 55 and described in Table 30 . Figure 55. TCP2 Status Register (TCPSTAT) 31 28 27 24 Reserved TCP_STATE R-0 R-0 23 22 21 20 16 CRC_PASS SNR_EXCEED ACTIVE_ITER R-0 R-0 R-0 15 12 11 10 9 8 AC...
Page 49 - Table 31. TCP2 Emulation Register (TCPEMU) Field Descriptions
6.26 TCP2 Emulation Register (TCPEMU) www.ti.com Registers In emulation mode, the access to TCP2 memories can be done in read or write. TCP2 supports emulationmode. Emulation support helps in system debug. Emulation modes are achieved with the programmableSOFT and FREE bits in the TCP2 Emulation Reg...
Page 50 - Data Memory for Systematic; Endianness; This architecture supports both big- and little-endian operation.
7 Endianness 7.1 Data Memory for Systematic Endianness www.ti.com The TCP2 is halted (or paused) after processing the ongoing frame. Any current frame processing mustcomplete. Sync vents for the new frame will be hold until TCP_EMUSUSP is released. The TCP2 isrestarted from the paused state and begi...
Page 51 - Figure 61. Data Memory
www.ti.com Endianness Figure 61. Data Memory 63:62 61:56 55:50 49:44 43:38 37:32 31:30 29:24 23:18 17:12 11:6 5:0 RSVD SP9 SP8 SP7 SP6 SP5 RSVD SP4 SP3 SP2 SP1 SP0 Figure 62. EN = 1 (Little-Endian Mode) Rate = 1/2 Word Word N + 1 N SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP3 SP3 SP0 0 A1' 0 0 X1 0 0 0 0 X0 Word...
Page 53 - Hard Decision Data
7.1.1 Hard Decision Data www.ti.com Endianness Figure 71. EN = 0 (Big-Endian Mode) Rate = 3/4 Word Word N N + 1 SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5 0 0 0 A0 X0 0 0 0 0 X1 Word Word N + 2 N + 3 SP4 SP3 SP2 SP1 SP0 SP9 SP8 SP7 SP6 SP5 0 0 0 0 X2 0 A3' 0 0 X3 Word Word N + 4 N + 5 SP4 SP3 SP2 SP1 S...
Page 54 - TCP_ENDIAN Register for Endianness Manager; Table 32. Hard Decisions in DSP Memory; They have to be swapped as described in
7.1.2 TCP_ENDIAN Register for Endianness Manager Endianness www.ti.com Figure 77. Destination of Endianness Manager (OUT_ORDER = 0) 63 62 32 31 1 0 Stage Stage Stage Stage Stage Stage N - 32 N - 33 N - 63 N N - 30 N - 31 4. OUT_ORDER = 1 EN = 1 (Little-Endian Mode) Figure 78. Trellis Stage Ordering ...
Page 55 - Interleaver Data; Table 33. TCP_ENDIAN Programming Register; Table 34. Interleaver Data
7.1.3 Interleaver Data 7.1.3.1 ENDIAN_INTR = 1 www.ti.com Endianness Figure 82. TCP_ENDIAN Register 31 16 Reserved R/W 15 2 1 0 ENDIAN_ ENDIAN_ Reserved EXTR INTR R/W R/W R/W LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 33. TCP_ENDIAN Programming Register Data Native Format...
Page 56 - Table 36. Interleaver Indexes in DSP Memory
INTER0 INTER1 INTER3 INTER2 Base 0 Base 2 Base 4 Base 6 INTER2 INTER3 INTER1 INTER0 EDMA3 63 0 INTER3 INTER2 INTER1 INTER0 Kernel 63 0 TCP Memory Endian_Intr=1 Endianness manager 7.1.3.2 ENDIAN_INTR = 0 INTER1 INTER0 INTER2 INTER3 Base 0 Base 2 Base 4 Base 6 INTER3 INTER2 INTER0 INTER1 EDMA3 63 0 IN...
Page 57 - Extrinsic Data; Table 37. Extrinsic Data
7.1.4 Extrinsic Data 7.1.4.1 ENDIAN_EXTR = 1 XT0 XT1 XT2 XT3 XT4 XT6 XT7 XT5 Base 0 Base 7 Endian_Extr=1 XT7 XT6 XT5 XT4 XT0 XT2 XT3 XT1 Endianness manager XT7 XT6 XT5 XT4 XT3 XT2 XT1 XT0 63 0 63 0 EDMA3 TCP Kernel Memory www.ti.com Endianness Figure 87. Data Source - EDMA3 (ENDIAN_INTR = 0) 63 48 4...
Page 59 - Architecture
7.1.4.2 ENDIAN_EXTR = 0 XT3 XT2 XT1 XT0 XT7 XT5 XT4 XT6 Base 0 Base 7 Endian_Extr=0 XT7 XT6 XT5 XT4 XT0 XT2 XT3 XT1 Endianness manager XT7 XT6 XT5 XT4 XT3 XT2 XT1 XT0 63 0 63 0 EDMA3 TCP Kernel Memory 8 Architecture www.ti.com Architecture If ENDIAN_EXTR = 0, data are saved in word format (32 bits) ...
Page 60 - Sub-block and Sliding Window Segmentation; Figure 95. MAP Unit Block Diagram; Alpha prolog portion
Beta memory Beta memory Scratch Alpha Extrinsic Extrinsicsignals Data from memory 8.1 Sub-block and Sliding Window Segmentation Architecture www.ti.com Figure 95. MAP Unit Block Diagram The TCP2 can enable or disable the max star function by modifying the E_MAX_STAR bit in the TCPIC3register. • E_MA...
Page 61 - for the number of sub-blocks and sliding windows.
Subblock : 1, 2 or 4 sliding windows Frame or subframe (length < 5114) First subblock Middle subblock Middle subblock Middle subblock Last subblock Beta Prolog portion Alpla Prolog portion Reliability portion Prolog Only used in SP mode.in SA mode, start fromknown state 0 Prolog Only used in SP m...
Page 62 - Reliability and Prolog Length Calculation
Shared-processing frame (length > 20730) First subframe Middle subframe Middle subframe Middle subframe Last subframe Prolog Must point tovalid address Tail Subframe (length ≤ 20480) 8.3 Reliability and Prolog Length Calculation Architecture www.ti.com Figure 97. Shared Processing Subframe Segmen...
Page 63 - Ǔ w; Added Features; Code Rates; Figure 98. Example R Formula
R MAX + 128 while ǒ ǒ N SB R N SW * N Ǔ w (R * 48) Ǔ R + WIN_SIZE N SB IF ǒ R N SB t WIN_SIZE Ǔ R ) ) if(N v 128) NSW + 1, R + N ELSE NSW + 2 IF ǒ N SW + 2 Ǔ { { WIN_SIZE + CEIL ƪ N ń N SW ƫ N SB + CEIL ƪ WIN_SIZE R MAX ƫ R MAX + R MAX * 1 } N SW + N SW * 1 8.4 Added Features 8.4.1 Code Rates www.ti...
Page 64 - Programming; Table 41. Valid Re-Encode Symbols Used for Comparison
8.4.2 Input Sign 8.4.3 Log Equation 8.4.4 Re-Encode 9 Programming Programming www.ti.com The TCP assumes that the encoded bits are converted into signed binary symbols using the followingmapping: 0 → -1, 1 → +1 and scaled by -2*a/ Σ 2 where a is the fading factor and Σ is the noise variance. Many re...
Page 65 - EDMA3 Resources; TCP2 Dedicated EDMA3 Resources; The EDMA3 parameters consists of eight words as shown in; Figure 99. EDMA3 Parameters Structure
9.1 EDMA3 Resources 9.1.1 TCP2 Dedicated EDMA3 Resources 9.1.2 Special TCP2 EDMA3 Programming Considerations www.ti.com Programming Note that several user channels can be programmed prior to starting the TCP2. Table 42. EDMA3 Parameters in Standalone (SA) Mode DirectionTransmit (DSP → TCP) Receive (...
Page 66 - EDMA3 Programming; Input Configuration Parameters Transfer; SPRUGK6
9.2 Programming Standalone (SA) Mode 9.2.1 EDMA3 Programming 9.2.1.1 Input Configuration Parameters Transfer 9.2.1.2 Systematics and Parities Transfer Programming www.ti.com Table 42 highlights the required EDMA3 resources to perform a standalone (SA) mode decoding. Each set of EDMA3 parameters uses...
Page 67 - Interleaver Indexes Transfer; information on how to setup a dummy Xfer, see the
9.2.1.3 Interleaver Indexes Transfer www.ti.com Programming – TCINTEN = 0 (Transfer complete interrupt is disabled) – TCC = 1 to 63 (Transfer Complete Code) – TCCMODE = 0 (Normal Completion) – FWID = Don't care – STAT = 0 (Entry is updated as normal) – SYNCDIM = 0 (AB-Sync, Each event triggers the t...
Page 68 - Hard-Decisions Transfer; Access (EDMA3) Controller Reference Guide
9.2.1.4 Hard-Decisions Transfer Programming www.ti.com • SRCBIDX = 0 (Source 2nd Dimension Index) • DSTBIDX = 0 (Destination 2nd Dimension Index • SRCCIDX = 0 (Source 3rd Dimension Index) • DSTCIDX = 0 (Destination 3rd Dimension Index) • CCNT = 1 (No of frames in a block) • BCNTRLD: Don't care • LIN...
Page 69 - Output Parameters Transfer; Input Configurations Parameters Programming; decoded and the OUTF bit is cleared.
9.2.1.5 Output Parameters Transfer 9.2.2 Input Configurations Parameters Programming www.ti.com Programming 3. Null EDMA3 transfer parameters (with all zeros), if there are no more user channels ready to be decoded and the OUTF bit is cleared. This EDMA3 transfer is optional and depends on the OUTF ...
Page 70 - through; To decode the whole frame, follow these steps:
9.3 Programming Shared-Processing (SP) Mode Programming www.ti.com The minimum number of iterations (MINIT bits in TCPIC3) should be selected as a function of the overallsystem performance (minimum iterations 1 to 31) when SNR stopping criteria is used. The INPUTSIGN bit can be enabled or disabled i...
Page 71 - ITCCEN = 0 (Intermediate transfer complete chaining is disabled)
9.3.1 EDMA3 Programming 9.3.1.1 Input Configuration Parameters Transfer 9.3.1.2 Systematics and Parities Transfer www.ti.com Programming This EDMA3 transfer to the input configuration parameters is a 16-word TCPXEVT frame-synchronizedtransfer. The parameters should be set as: • OPTIONS: – ITCCEN = 0...
Page 72 - A Priori Transfer; LINK ADDRESS: See cases 1 and 2 below
9.3.1.3 A Priori Transfer Programming www.ti.com • Word count = 2 * ceil (frame_length/2) • BCNT = (Word count /2) (No of arrays of length ACNT) • DESTINATION ADDRESS: TCPSP (5001 0000h) • SRCBIDX = 8 (Source 2nd Dimension Index) • DSTBIDX = 8 (Destination 2nd Dimension Index) • SRCCIDX = 8 (Source ...
Page 73 - Extrinsics Transfer
9.3.1.4 Extrinsics Transfer 9.3.2 Input Configurations Parameters Programming www.ti.com Programming 1. The EDMA3 input configuration parameters transfer parameters of the next user-channel MAP, if there is one ready to be decoded. 2. Dummy EDMA3 transfer parameters, if there are no more user channe...
Page 74 - Output Parameters; Mode; The various output parameters are described in
10 Output Parameters 11 Events Generation Write to TCPEND Write toTCPEXE Soft reset XEVT Write input params XEVT XEVT Write input data coefficients interleaver Write MAP0 decode MAP decode REVT REVT XEVT decisions hard Read registers Read output T CPU/DMA operations TCP operations Output Parameters ...
Page 75 - Debug Mode: Pause After Each Map; = debug mode. Normal initialization and wait in MAP state 0.
Input config params Syst&Par SF1 SF1 Extrinsics TCP processing TCPXEVT TCPXEVT TCPREVT TCPXEVT MAP1 TCP processing TCPXEVT Input config params TCPXEVT TCPREVT SF2 Syst&Par Extrinsics SF2 TCPXEVT 2 subframes TCPXEVT Input config params TCPXEVT SF1 Syst&Par Apriori SF1 TCPXEVT TCPREVT Extr...
Page 76 - Errors and Status
13.1.2 Unexpected Frame Length: F 13.1.3 Unexpected Prolog Length: P 13.1.4 Unexpected Subframe Length: SF 13.1.5 Unexpected Reliability Length: R 13.1.6 Unexpected Signal to Noise Ratio: SNR 13.1.7 Unexpected Interleaver Table Load: INT 13.1.8 Unexpected Output Parameters Load: OP 13.1.9 Unexpected...
Page 77 - The TCP2 status register (TCPSTAT) reflects the state of the TCP2.
13.1.10 Unexpected Max and Min Iterations: MAXMINITER 13.2 Status 13.2.1 TCP2 Decoder Status: dec_busy 13.2.2 TCP2 Stopped Due to Error: ERR 13.2.3 TCP2 Waiting for Input Control Parameters Write: WIC 13.2.4 TCP2 Waiting for Interleaver Table Write: WINT 13.2.5 TCP2 Waiting for Systematics and Parit...
Page 78 - The Active_state indicates active MAP decoder state.
13.2.12 TCP2 Active State Status: Active_state 13.2.13 TCP2 Active Iteration Status: Active_iter 13.2.14 TCP2 SNR Status: snr_exceed 13.2.15 TCP2 CRC Status: Crc_pass 13.2.16 TCP2 State: TCP_STATE Errors and Status www.ti.com The Active_state indicates active MAP decoder state. The Active_iter indic...
Page 79 - IMPORTANT NOTICE
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers shouldobtain the l...
Texas Instruments 60X
Manual
Texas Instruments TAS5508-5142K7EVM
Manual
Texas Instruments SLUU083A
Manual
Texas Instruments TSC2007EVM-PDK
Manual
Texas Instruments TNETE211
Manual
Texas Instruments TI-83 PLUS
Manual
Texas Instruments TPS53125EVM-599
Manual
Texas Instruments 47
Manual
Texas Instruments TI-83
Manual
Texas Instruments ADS5102 EVM
Manual
Texas Instruments TMS320F2801
Manual
Texas Instruments TPA6139A2 EVM
Manual
Texas Instruments 2000
Manual
Texas Instruments 3000
Manual
Texas Instruments UCC38500EVM
Manual
Texas Instruments CS-FX300MS PLUS
Manual
Texas Instruments SPRAA56
Manual
Texas Instruments TMS320DM646X DMSOC
Manual