Page 2 - PRODUCT PREVIEW
www.ti.com PRODUCT PREVIEW 1.1.1 ZTZ/GTZ BGA Package (Bottom View) ZTZ/GTZ 697-PIN BALL GRID ARRAY (BGA) PACKAGE ( BOTTOM VIEW ) A 2 B 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 27 28 29 AG AH AJ NOTE: The ZTZ mechanical p...
Page 3 - Fixed-Point Digital Signal Processor
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The C64x+ DSP core employs eight functional units, two register files, and two data paths. Like the earlierC6000 devices, two of these eight functional units are multipliers or ....
Page 4 - Functional Block Diagram; shows the functional block diagram of the C6454 device.
www.ti.com PRODUCT PREVIEW 1.3 Functional Block Diagram L2 Memory Controller (Memory Protect/ Bandwidth Mgmt) DDR2 Mem Ctlr System (B ) C64x+ DSP Core Data Path B B Register File B31−B16 B15−B0 Instruction Fetch Data Path A A Register File A31−A16 A15−A0 Device Configuration Logic .L1 .S1 .M1 xxxx ....
Page 5 - Contents
www.ti.com PRODUCT PREVIEW Contents TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 1 TMS320C6454 Fixed-Point Digital Signal 5.5 Megamodule Resets ................................ 81 Processor .................................................. 1 5.6 Meg...
Page 6 - Device Overview; Device Characteristics; Table 2-1. Characteristics of the C6454 Processor; HARDWARE FEATURES
www.ti.com PRODUCT PREVIEW 2 Device Overview 2.1 Device Characteristics TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-1 , provides an overview of the C6454 DSP. The tables show significant features of the C6454 device, including the capacity of...
Page 8 - Other new features include:
www.ti.com PRODUCT PREVIEW TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Other new features include: • SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops wheremultiple iterations of a loop are executed in ...
Page 9 - Data path A
www.ti.com PRODUCT PREVIEW src2 src2 Á Á Á Á Á Á Á .D1 .M1 Á Á Á Á Á Á Á Á Á Á Á Á Á .S1 Á Á Á Á Á Á Á Á Á Á .L1 long src odd dst src2 src1 Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á src1 src1 src1 even dst even dst odd dst dst1 dst src2 src2 src2 long src DA1 ST1b LD1b LD1a ST1a Data path A Odd regi...
Page 10 - Memory Map Summary; MEMORY BLOCK DESCRIPTION
www.ti.com PRODUCT PREVIEW 2.3 Memory Map Summary TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-2 shows the memory map address ranges of the C6454 device. The external memory configuration register address ranges in the C6454 device begin at th...
Page 12 - Boot Modes Supported; Supported, describes each boot mode in more detail.
www.ti.com PRODUCT PREVIEW 2.4 Boot Sequence 2.4.1 Boot Modes Supported TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The boot sequence is a process by which the DSP's internal memory is loaded with program and datasections and the DSP's internal regis...
Page 13 - nd-Level Bootloaders; such as Code Composer Studio.
www.ti.com PRODUCT PREVIEW 2.4.2 2nd-Level Bootloaders TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 such as Code Composer Studio. For the PCI host boot, the CPU is out of reset, but it executes an IDLE instruction until a DSP interruptis generated by...
Page 14 - Pin Map; through
www.ti.com PRODUCT PREVIEW 2.5 Pin Assignments 2.5.1 Pin Map AG AF AE AD AC AB AA Y W V U T R 13 12 11 10 9 8 7 6 5 4 3 2 1 13 12 11 10 9 8 7 6 5 4 3 2 1 CLKR1/ GP[0] HD15/ AD15 HD2/ AD2 PGNT/ GP[12] HD22/ AD22 DV DD33 RSV15 PIDSEL RSV16 HDS1/ PSERR HINT/ PFRAME DV DD33 HHWIL/ PCLK V SS HD12/ AD12 H...
Page 18 - Signal Groups Description
www.ti.com PRODUCT PREVIEW 2.6 Signal Groups Description TRST IEEE Standard 1149.1 (JTAG) Emulation Reserved Reset and Interrupts Control/Status TDI TDO TMS TCK NMI RESET RSV03RSV04 Clock/PLL1 and PLL Controller CLKIN1 EMU0EMU1 SYSCLK4/GP[1] (A) EMU14EMU15EMU16 EMU17 RSV02 EMU18 RSV06RSV07 RSV05 RSV...
Page 24 - Terminal Functions; The terminal functions table (
www.ti.com PRODUCT PREVIEW 2.7 Terminal Functions TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The terminal functions table ( Table 2-3 ) identifies the external signal names, the associated pin (ball) numbers along with the mechanical package designa...
Page 25 - SIGNAL
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. Nonmaskable interrupt, edge-driven (rising edge)Any noise on the NMI pin may trigger an...
Page 35 - RESERVED FOR TEST
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. This pin is the EMAC collision sense (MCDL) (I) for MII [default] or GMII. MCOL K3 I/O/...
Page 42 - GROUND PINS
www.ti.com PRODUCT PREVIEW TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. R18 T11 T13 T15 T17 T19 U12 CV DD S 1.2-V core supply voltage U14 U18 V11 V13 V19 W12 W1...
Page 47 - Development Support; Device development evolutionary flow:
www.ti.com PRODUCT PREVIEW 2.8 Development 2.8.1 Development Support 2.8.2 Device Support TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 In case the customer would like to develop their own features and software on the C6454 device, TI offersan extensi...
Page 48 - ) or contact your TI sales representative.; Documentation Support; . Tip: Enter the literature number in the
www.ti.com PRODUCT PREVIEW C64x+ t DSP:C6454 PREFIX TMX 320 C6454 ZTZ TMX = Experimental deviceTMS = Qualified device DEVICE FAMILY 320 = TMS320 t DSP family PACKAGE TYPE (A) ZTZ = 697-pin plastic BGA, with Pb-Free solder ballsGTZ = 697-pin plastic BGA, with Pb-ed solder balls DEVICE A. BGA = Ball G...
Page 50 - Device Configuration at Device Reset; NOTE; CONFIGURATION
www.ti.com PRODUCT PREVIEW 3 Device Configuration 3.1 Device Configuration at Device Reset TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 On the C6454 device, certain device configurations like boot mode, pin multiplexing, and endianess, areselected at ...
Page 52 - Peripheral Configuration at Device Reset
www.ti.com PRODUCT PREVIEW 3.2 Peripheral Configuration at Device Reset TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 3-1. C6454 Device Configuration Pins (AEA[19:0], ABA[1:0], and PCI_EN) (continued) CONFIGURATION IPD/ NO. FUNCTIONAL DESCRIPTION...
Page 53 - Peripheral Selection After Device Reset
www.ti.com PRODUCT PREVIEW 3.3 Peripheral Selection After Device Reset TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 3-2. PCI_EN, PCI66, PCI_EEAI, and HPI_WIDTH Peripheral Selection (HPI and PCI) (continued) CONFIGURATION PIN SETTING (1) PERIPHE...
Page 54 - Figure 3-1. Peripheral Transitions Between States
www.ti.com PRODUCT PREVIEW Reset Static Powerdown Disabled Enable In Progress Enabled Unlock the PERCFG0 register by using the PERLOCK register. Write to the PERCFG0 register within 16 SYSCLK3 clock cycles to change the state of the peripherals. Poll the PERSTAT registers to verify state change. TMS...
Page 55 - Device State Control Registers; and described in the next sections.; Table 3-5. Device State Control Registers; HEX ADDRESS RANGE
www.ti.com PRODUCT PREVIEW 3.4 Device State Control Registers TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The C6454 device has a set of registers that are used to control the status of its peripherals. Theseregisters are shown in Table 3-5 and descr...
Page 56 - Peripheral Lock Register Description; Bit
www.ti.com PRODUCT PREVIEW 3.4.1 Peripheral Lock Register Description TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 When written with correct 32-bit key (0x0F0A0B00), the Peripheral Lock Register (PERLOCK) allows onewrite to the PERCFG0 register within...
Page 57 - Peripheral Configuration Register 0 Description
www.ti.com PRODUCT PREVIEW 3.4.2 Peripheral Configuration Register 0 Description TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The Peripheral Configuration Register (PERCFG0) is used to change the state of the peripherals. Onewrite is allowed to this ...
Page 59 - Peripheral Configuration Register 1 Description
www.ti.com PRODUCT PREVIEW 3.4.3 Peripheral Configuration Register 1 Description TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The Peripheral Configuration Register (PERCFG1) is used to enable the EMIFA and DDR2 MemoryController. EMIFA and the DDR2 Me...
Page 60 - Peripheral Status Registers Description
www.ti.com PRODUCT PREVIEW 3.4.4 Peripheral Status Registers Description TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The Peripheral Status Registers (PERSTAT0 and PERSTAT1) show the status of the C6454 peripherals. 31 30 29 27 26 24 Reserved HPISTAT ...
Page 63 - EMAC Configuration Register (EMACCFG) Description
www.ti.com PRODUCT PREVIEW 3.4.5 EMAC Configuration Register (EMACCFG) Description TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The EMAC Configuration Register (EMACCFG) is used to assert and deassert the reset of the ReducedMedia Independent Interfa...
Page 64 - Emulator Buffer Powerdown Register (EMUBUFPD) Description
www.ti.com PRODUCT PREVIEW 3.4.6 Emulator Buffer Powerdown Register (EMUBUFPD) Description TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The Emulator Buffer Powerdown Register (EMUBUFPD) is used to control the state of the pin buffers ofemulator pins E...
Page 65 - Device Status Register Description; and
www.ti.com PRODUCT PREVIEW 3.5 Device Status Register Description TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The device status register depicts the device configuration selected upon device reset. Once set, thesebits will remain set until a device ...
Page 68 - Voltage and Operating Case Temperature.
www.ti.com PRODUCT PREVIEW TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 • Other Input Pins: If the IPU/IPD does not match the desired value/state, use an externalpullup/pulldown resistor to pull the signal to the opposite rail. For the device configur...
Page 69 - Configuration Examples
www.ti.com PRODUCT PREVIEW 3.8 Configuration Examples Shading denotes a peripheral module not available for this configuration. McBSP0 TIMER0 EMIFA GPIO PLL2 and PLL2 Controller TIMER1 PLL1 and PLL1 Controller DDR2 EMIF AED[63:0] 64 AECLKIN, AARDY, AHOLD AEA[22:3], ACE[3:0], ABE[7:0],AECLKOUT, ASDCK...
Page 71 - System Interconnect; Bridges perform a variety of functions:
www.ti.com PRODUCT PREVIEW 4 System Interconnect 4.1 Internal Buses, Bridges, and Switch Fabrics TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 On the C6454 device, the C64x+ Megamodule, the EDMA3 transfer controllers, and the systemperipherals are int...
Page 72 - Data Switch Fabric Connections
www.ti.com PRODUCT PREVIEW 4.2 Data Switch Fabric Connections TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Figure 4-1 shows the connection between slaves and masters through the data switched central resource (SCR). Masters are shown on the right and ...
Page 73 - Figure 4-1. Switched Central Resource Block Diagram
www.ti.com PRODUCT PREVIEW EMAC HPI M M 128-bit (SYSCLK2) M3 M0 S M M M McBSPs S DDR2 Memory Controller S EMIFA S PCI S MASTER S M Bridge CFGSCR S Bridge PCI M EDMA3 Channel Controller EDMA3 Transfer Controllers Megamodule M1 M2 S3 S0 S1 S2 S S Events M Megamodule Data SCR 128 (SYSCLK2) 128 (SYSCLK2...
Page 74 - Configuration Switch Fabric
www.ti.com PRODUCT PREVIEW 4.3 Configuration Switch Fabric TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 4-1. SCR Connection Matrix DDR2 MEMORY McBSPs CONFIGURATION SCR PCI EMIFA MEGAMODULE CONTROLLER TC0 N N N Y Y Y TC1 Y Y Y Y Y Y TC2 N N Y Y Y...
Page 76 - Priority Allocation; . The priority is enforced when several
www.ti.com PRODUCT PREVIEW 4.4 Priority Allocation TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 On the C6454 device, each of the masters (excluding the C64x+ Megamodule) are assigned a priority viathe Priority Allocation Register (PRI_ALLOC), see Figu...
Page 77 - Memory Architecture; shows a block diagram of the C64x+ Megamodule.
www.ti.com PRODUCT PREVIEW 5 C64x+ Megamodule A register file Data path 1 Data path 2 B register file D2 S2 xx xx M2 L2 Instruction decode M1 xx xx L1 S1 D1 16/32−bit instruction dispatch Instruction fetch SPLOOP buffer 64 64 C64x+ CPU 256 32 L1D cache/SRAM Bandwidth management Memory protection L1 ...
Page 78 - Region 1 size is 32K bytes with no wait states.
www.ti.com PRODUCT PREVIEW 4K bytes 8K bytes 16K bytes L1P memory 00E0 0000h 00E0 4000h 00E0 6000h 00E0 7000h 00E0 8000h direct mapped SRAM 1/2 dm 3/4 SRAM SRAM 7/8 All SRAM 000 001 010 011 100 Block baseaddress L1P mode bits cache 4K bytes cache direct mapped cache direct mapped cache 4K bytes 8K b...
Page 80 - Memory Protection; Table 5-1. Available Memory Page Protection Schemes; AID0 Bit; Memory-mapped registers configuration bus
www.ti.com PRODUCT PREVIEW 5.2 Memory Protection 5.3 Bandwidth Management TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Memory protection allows an operating system to define who or what is authorized to access L1D, L1P,and L2 memory. To accomplish thi...
Page 81 - Megamodule Resets; Megamodule, either both globally or just locally.; ). And for more detailed information on device
www.ti.com PRODUCT PREVIEW 5.4 Power-Down Control 5.5 Megamodule Resets TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The C64x+ Megamodule supports the ability to power-down various parts of the C64x+ Megamodule. Thepower-down controller (PDC) of the ...
Page 82 - Megamodule Revision; and described in
www.ti.com PRODUCT PREVIEW 5.6 Megamodule Revision TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The version and revision of the C64x+ Megamodule can be read from the Megamodule Revision IDRegister (MM_REVID) located at address 0181 2000h. The MM_REVID...
Page 83 - Table 5-4. Megamodule Interrupt Registers
www.ti.com PRODUCT PREVIEW 5.7 C64x+ Megamodule Register Description(s) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 5-4. Megamodule Interrupt Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0180 0000 EVTFLAG0 Event Flag Register 0 (Events [3...
Page 84 - Table 5-5. Megamodule Powerdown Control Registers
www.ti.com PRODUCT PREVIEW TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 5-4. Megamodule Interrupt Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0180 0184 INTXCLR Interrupt Exception Clear Register 0180 0188 INTDMASK Dropped Inter...
Page 85 - Table 5-8. Megamodule Cache Configuration Registers
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 5-8. Megamodule Cache Configuration Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0184 0000 L2CFG L2 Cache Configuration Register 0184 0004 - 0184 001F - Reserved 0184 ...
Page 89 - Table 5-10. CPU Megamodule Bandwidth Management Registers
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 5-9. Megamodule L1/L2 Memory Protection Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0184 AD08 L1DMPLK2 L1D memory protection lock key bits [95:64] 0184 AD...
Page 90 - Recommended Operating Conditions; MIN
www.ti.com PRODUCT PREVIEW 6 Device Operating Conditions 6.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise 6.2 Recommended Operating Conditions TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Noted) (1) Supply voltage r...
Page 91 - Recommended Operating Conditions (continued)
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Recommended Operating Conditions (continued) MIN NOM MAX UNIT 3.3 V pins (exceptPCI-capable and 0.8 V I2C pins) PCI-capable pins -0.5 0.3DV DD33 V V IL Low-level input voltage I2...
Page 92 - Case Temperature (Unless Otherwise Noted)
www.ti.com PRODUCT PREVIEW 6.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Case Temperature (Unless Otherwise Noted) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT 3.3...
Page 94 - Parameter Information; Tester Pin Electronics; Figure 7-1. Test Load Circuit for AC Timing Measurements; MAX and V; MIN for input clocks,; MAX and V; MIN for output clocks.; Figure 7-3. Rise and Fall Transition Time Voltage Reference Levels
www.ti.com PRODUCT PREVIEW 7 C64x+ Peripheral Information and Electrical Specifications 7.1 Parameter Information Transmission Line 4.0 pF 1.85 pF Z0 = 50 Ω (see Note) Tester Pin Electronics Data Sheet Timing Reference Point OutputUnderTest NOTE: The data sheet provides timing at the device pin. For...
Page 95 - Timing Parameters and Board Routing Analysis; buffers may be used to compensate any timing differences.; DESCRIPTION
www.ti.com PRODUCT PREVIEW 7.1.3 Timing Parameters and Board Routing Analysis 1 2 3 4 5 6 7 8 10 11 AECLKOUT (Output from DSP) AECLKOUT (Input to External Device) Control Signals (A) (Output from DSP) Control Signals (Input to External Device) Data Signals (B) (Output from External Device) Data Sign...
Page 96 - Recommended Clock and Control Signal Transition Behavior; Power-Supply Sequencing; Power-Supply Decoupling; UNIT
www.ti.com PRODUCT PREVIEW 7.2 Recommended Clock and Control Signal Transition Behavior 7.3 Power Supplies 7.3.1 Power-Supply Sequencing DV DD33 CV DD12 All other power supplies 1 2 7.3.2 Power-Supply Decoupling 7.3.3 Power-Down Operation TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – AP...
Page 98 - EDMA3 Device-Specific Information
www.ti.com PRODUCT PREVIEW 7.4 Enhanced Direct Memory Access (EDMA3) Controller 7.4.1 EDMA3 Device-Specific Information TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The primary purpose of the EDMA3 is to service user-programmed data transfers between ...
Page 99 - EDMA3 Channel Synchronization Events; Table 7-3. C6454 EDMA3 Channel Synchronization Events; EDMA
www.ti.com PRODUCT PREVIEW 7.4.2 EDMA3 Channel Synchronization Events TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The EDMA3 supports up to 64 DMA channels that can be used to service system peripherals and to movedata between system memories. DMA ch...
Page 100 - Table 7-4. EDMA3 Channel Controller Registers
www.ti.com PRODUCT PREVIEW 7.4.3 EDMA3 Peripheral Register Description(s) TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-3. C6454 EDMA3 Channel Synchronization Events (continued) EDMA BINARY EVENT NAME EVENT DESCRIPTION CHANNEL 58 011 1010 GPINT...
Page 106 - Table 7-6. EDMA3 Transfer Controller 0 Registers
www.ti.com PRODUCT PREVIEW TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-5. EDMA3 Parameter RAM (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME ... ... 02A0 47E0 - 02A0 47FF - Parameter Set 63 02A0 4800 - 02A0 481F - Parameter Set 64 02A0 4...
Page 107 - Table 7-7. EDMA3 Transfer Controller 1 Registers
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-6. EDMA3 Transfer Controller 0 Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A2 0348 DFCNT1 Destination FIFO Count Register 1 02A2 034C DFDST1 Destinati...
Page 108 - Table 7-8. EDMA3 Transfer Controller 2 Registers
www.ti.com PRODUCT PREVIEW TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-7. EDMA3 Transfer Controller 1 Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A2 8284 DFSRCBREF Destination FIFO Set Destination Address B Reference Regis...
Page 110 - Table 7-9. EDMA3 Transfer Controller 3 Registers
www.ti.com PRODUCT PREVIEW TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-9. EDMA3 Transfer Controller 3 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A3 8000 PID Peripheral Identification Register 02A3 8004 TCCFG EDMA3TC Configuration Reg...
Page 112 - Interrupt Sources and Interrupt Controller; EVENT NUMBER
www.ti.com PRODUCT PREVIEW 7.5 Interrupts 7.5.1 Interrupt Sources and Interrupt Controller TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The CPU interrupts on the C6454 device are configured through the C64x+ Megamodule InterruptController. The interru...
Page 115 - External Interrupts Electrical Data/Timing; Table 7-11. Timing Requirements for External Interrupts
www.ti.com PRODUCT PREVIEW 7.5.2 External Interrupts Electrical Data/Timing 2 1 NMI TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-11. Timing Requirements for External Interrupts (1) (see Figure 7-6 ) -720-850 NO. UNIT -1000 MIN MAX 1 t w(NMIL)...
Page 116 - TYPE; The following sequence must be followed during a Power-on Reset:
www.ti.com PRODUCT PREVIEW 7.6 Reset Controller 7.6.1 Power-on Reset (POR Pin) TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The reset controller detects the different type of resets supported on the C6454 device and manages thedistribution of those re...
Page 117 - all the system clocks are invalid at this point.; The following sequence must be followed during a Warm Reset:
www.ti.com PRODUCT PREVIEW 7.6.2 Warm Reset (RESET Pin) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 all the system clocks are invalid at this point. • The RESETSTAT pin stays asserted (low), indicating the device is in reset. 3. The POR pin may now ...
Page 118 - System Reset; During a System Reset, the following happens:
www.ti.com PRODUCT PREVIEW 7.6.3 System Reset 7.6.4 CPU Reset TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 4. The device is now out of reset, device execution begins as dictated by the selected boot mode (see Section 2.4 , Boot Sequence). NOTE The POR...
Page 119 - Reset Priority; Maximum Reset
www.ti.com PRODUCT PREVIEW 7.6.5 Reset Priority 7.6.6 Reset Controller Register TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 If any of the above reset sources occur simultaneously, the PLLCTRL only processes the highest priorityreset request. The res...
Page 120 - Reset Electrical Data/Timing; Table 7-14. Timing Requirements for Reset; For
www.ti.com PRODUCT PREVIEW 7.6.7 Reset Electrical Data/Timing TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 NOTE If a configuration pin must be routed out from the device and 3-stated (not driven), theinternal pullup/pulldown (IPU/IPD) resistor should ...
Page 123 - PLL1 and PLL1 Controller; As shown in; DSP
www.ti.com PRODUCT PREVIEW 7.7 PLL1 and PLL1 Controller TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The primary PLL controller generates the input clock to the C64x+ megamodule (including the CPU) aswell as most of the system peripherals such as the...
Page 124 - PLL1 Controller Device-Specific Information
www.ti.com PRODUCT PREVIEW 1 0 0 1 DIVIDER D4 CLKIN1 (B) PLLEN (PLLCTL.[0]) SYSCLK2 SYSCLK3 AECLKIN (External EMIF Clock Input) EMIFA DIVIDER PREDIV DIVIDER D2 (A) DIVIDER D3 (A) AECLKOUT PLLV1 C2 C1 EMI Filter +1.8 V 560 pF 0.1 m F SYSCLK5(Emulation and Trace) SYSREFCLK(C64x+ MegaModule) AECLKINSEL...
Page 125 - SYSCLK5 clocks the emulation and trace logic of the DSP.; CLOCK SIGNAL
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 • SYSCLK4 is used as the internal clock for the EMIFA. It is also used to clock other logic within theDSP. • SYSCLK5 clocks the emulation and trace logic of the DSP. The divider ...
Page 126 - PLL1 Controller Memory Map; The memory map of the PLL1 controller is shown in
www.ti.com PRODUCT PREVIEW 7.7.2 PLL1 Controller Memory Map TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 1with PLLEN = 0) to when to when the PLL controll...
Page 127 - PLL1 Controller Register Descriptions; The PLL control register (PLLCTL) is shown in
www.ti.com PRODUCT PREVIEW 7.7.3 PLL1 Controller Register Descriptions TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 This section provides a description of the PLL1 controller registers. For details on the operation of the PLLcontroller module, see th...
Page 128 - The PLL multiplier control register (PLLM) is shown in
www.ti.com PRODUCT PREVIEW TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.7.3.2 PLL Multiplier Control Register The PLL multiplier control register (PLLM) is shown in Figure 7-12 and described in Table 7-20 . The PLLM register defines the input refere...
Page 130 - The PLL controller divider 4 register (PLLDIV4) is shown in
www.ti.com PRODUCT PREVIEW TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.7.3.4 PLL Controller Divider 4 Register The PLL controller divider 4 register (PLLDIV4) is shown in Figure 7-14 and described in Table 7-22 . Besides being used as the EMIFA int...
Page 131 - The PLL controller divider 5 register (PLLDIV5) is shown in
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.7.3.5 PLL Controller Divider 5 Register The PLL controller divider 5 register (PLLDIV5) is shown in Figure 7-15 and described in Table 7-23 . 31 16 Reserved R-0 15 14 5 4 0 D5E...
Page 137 - PLL1 Controller Input and Output Clock Electrical Data/Timing; Table 7-29. Timing Requirements for CLKIN1 Devices
www.ti.com PRODUCT PREVIEW 7.7.4 PLL1 Controller Input and Output Clock Electrical Data/Timing CLKIN1 2 3 4 4 5 1 SYSCLK4 3 4 4 2 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-29. Timing Requirements for CLKIN1 Devices (1) (2) (3) (see Figure ...
Page 138 - PLL2 and PLL2 Controller
www.ti.com PRODUCT PREVIEW 7.8 PLL2 and PLL2 Controller PLLV2 PLL2 SYSCLK2 (From PLL1 Controller) SYSCLK1 DDR2 Memory Controller EMAC CLKIN2 (B)(C) C162 560 pF EMI Filter +1.8 V C161 0.1 pF PLL2 Controller TMS320C6454 DSP PLLM x20 /2 1 0 /x (A) 1 SYSREFCLK SYSCLK3 (From PLL1 Controller) PLLREF PLLOU...
Page 139 - PLL2 Controller Device-Specific Information; PLL2 is only unlocked during the power-up sequence (see
www.ti.com PRODUCT PREVIEW 7.8.1 PLL2 Controller Device-Specific Information TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.8.1.1 Internal Clocks and Maximum Operating Frequencies As shown in Figure 7-23 , the output of PLL2, PLLOUT, is divided by 2 ...
Page 140 - PLL2 Controller Memory Map; The memory map of the PLL2 controller is shown in
www.ti.com PRODUCT PREVIEW 7.8.2 PLL2 Controller Memory Map 7.8.3 PLL2 Controller Register Descriptions TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The memory map of the PLL2 controller is shown in Table 7-32 . Note that only registers documented her...
Page 141 - The PLL controller divider 1 register (PLLDIV1) is shown in
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.8.3.1 PLL Controller Divider 1 Register The PLL controller divider 1 register (PLLDIV1) is shown in Figure 7-24 and described in Table 7-33 . 31 16 Reserved R-0 15 14 5 4 0 D1E...
Page 145 - Table 7-38. SYSCLK Status Register Field Descriptions
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.8.3.6 SYSCLK Status Register The SYSCLK status register (SYSTAT) shows the status of the system clock (SYSCLK1). SYSTAT isshown in Figure 7-29 and described in Table 7-38 . 31 ...
Page 146 - PLL2 Controller Input Clock Electrical Data/Timing; Table 7-39. Timing Requirements for CLKIN2
www.ti.com PRODUCT PREVIEW 7.8.4 PLL2 Controller Input Clock Electrical Data/Timing CLKIN2 2 3 4 4 5 1 TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-39. Timing Requirements for CLKIN2 (1) (2) (3) (see Figure 7-30 ) -720-850 NO. UNIT -1000 MIN M...
Page 147 - DDR2 Memory Controller; DDR2 Memory Controller Device-Specific Information; SPRAAA7
www.ti.com PRODUCT PREVIEW 7.9 DDR2 Memory Controller 7.9.1 DDR2 Memory Controller Device-Specific Information TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The 32-bit DDR2 Memory Controller bus of the C6454 is used to interface to JESD79D-2Astandard-...
Page 148 - DDR2 Memory Controller Peripheral Register Description(s); Table 7-40. DDR2 Memory Controller Registers
www.ti.com PRODUCT PREVIEW 7.9.2 DDR2 Memory Controller Peripheral Register Description(s) 7.9.3 DDR2 Memory Controller Electrical Data/Timing TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-40. DDR2 Memory Controller Registers HEX ADDRESS RANGE ...
Page 149 - ZBT (Zero Bus Turnaround) SRAM and Late Write SRAM
www.ti.com PRODUCT PREVIEW 7.10 External Memory Interface A (EMIFA) 7.10.1 EMIFA Device-Specific Information TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The EMIFA can interface to a variety of external devices or ASICs, including: • Pipelined and fl...
Page 151 - Table 7-42. Timing Requirements for AECLKIN for EMIFA
www.ti.com PRODUCT PREVIEW 7.10.3 EMIFA Electrical Data/Timing AECLKIN 2 3 4 4 5 1 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-42. Timing Requirements for AECLKIN for EMIFA (1) (2) (see Figure 7-31 ) -720-850 NO. UNIT -1000 MIN MAX 1 t c(EKI...
Page 152 - EMIFA Module; Figure 7-32. AECLKOUT Timing for the EMIFA Module
www.ti.com PRODUCT PREVIEW 4 5 1 2 AECLKIN AECLKOUT1 3 3 TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-43. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT for the EMIFA Module (1) (2) (3) (see Figure 7-32 ) -720-850...
Page 153 - Memory Cycles for EMIFA Module; PARAMETER; Figure 7-33. Asynchronous Memory Read Timing for EMIFA
www.ti.com PRODUCT PREVIEW AECLKOUT ACEx ABE[7:0] AEA[19:0]/ ABA[1:0] AED[63:0] AAOE/ASOE (A) AR/W AAWE/ASWE (A) AARDY (B) Byte Enables Address Read Data Hold = 1 2 Strobe = 4 Setup = 1 2 2 4 10 10 1 1 1 3 A AAOE/ASOE and AAWE/ASWE operate as AAOE (identified under select signals) and AAWE, respecti...
Page 154 - Figure 7-34. Asynchronous Memory Write Timing for EMIFA
www.ti.com PRODUCT PREVIEW AECLKOUT ACEx ABE[7:0] AEA[19:0]/ ABA[1:0] AED[63:0] AAOE/ASOE (A) AR/W AAWE/ASWE (A) AARDY (B) Byte Enables Address Write Data Hold = 1 12 Strobe = 4 Setup = 1 12 12 12 12 13 13 11 11 11 11 11 A AAOE/ASOE and AAWE/ASWE operate as AAOE (identified under select signals) and...
Page 155 - Programmable Synchronous Interface Timing
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.10.3.2 Programmable Synchronous Interface Timing Table 7-46. Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module (see Figure 7-36 ) -720-850 NO. ...
Page 158 - Cycles for EMIFA Module
www.ti.com PRODUCT PREVIEW 7.10.4 HOLD/HOLDA Timing HOLD HOLDA EMIF Bus (A) DSP Owns Bus External Requestor Owns Bus DSP Owns Bus DSP DSP 1 3 2 5 4 AECLKOUT TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-48. Timing Requirements for the HOLD/HOLD...
Page 159 - for EMIFA Module (see
www.ti.com PRODUCT PREVIEW 7.10.5 BUSREQ Timing AECLKOUTx 1 ABUSREQ 1 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-50. Switching Characteristics Over Recommended Operating Conditions for the BUSREQ Cycles for EMIFA Module (see Figure 7-40 ) -...
Page 163 - Table 7-52. Timing Requirements for I2C Timings
www.ti.com PRODUCT PREVIEW 7.11.3 I2C Electrical Data/Timing TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.11.3.1 Inter-Integrated Circuits (I2C) Timing Table 7-52. Timing Requirements for I2C Timings (1) (see Figure 7-42 ) -720-850 -1000 NO. UNIT S...
Page 164 - Table 7-53. Switching Characteristics for I2C Timings
www.ti.com PRODUCT PREVIEW 10 8 4 3 7 12 5 6 14 2 3 13 Stop Start Repeated Start Stop SDA SCL 1 11 9 TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Figure 7-42. I2C Receive Timings Table 7-53. Switching Characteristics for I2C Timings (1) (see Figure 7-...
Page 167 - Table 7-55. Timing Requirements for Host-Port Interface Cycles
www.ti.com PRODUCT PREVIEW 7.12.3 HPI Electrical Data/Timing TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-55. Timing Requirements for Host-Port Interface Cycles (1) (2) (see Table 7-56 through Figure 7-51 ) -720-850 NO. UNIT -1000 MIN MAX 9 t...
Page 177 - The McBSP provides these functions:
www.ti.com PRODUCT PREVIEW 7.13 Multichannel Buffered Serial Port (McBSP) TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The McBSP provides these functions: • Full-duplex communication • Double-buffered data registers, which allow a continuous data str...
Page 180 - Multichannel Buffered Serial Port (McBSP) Timing
www.ti.com PRODUCT PREVIEW 7.13.2 McBSP Electrical Data/Timing TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.13.2.1 Multichannel Buffered Serial Port (McBSP) Timing Table 7-59. Timing Requirements for McBSP (1) (see Figure 7-52 ) -720-850 NO. UNIT -1...
Page 188 - Interface Modes
www.ti.com PRODUCT PREVIEW 7.14.1 EMAC Device-Specific Information TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Interface Modes The EMAC module on the TMS320C6454 supports four interface modes: Media Independent Interface(MII), Reduced Media Independe...
Page 189 - BALL NUMBER; Using the RMII Mode of the EMAC
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-70. EMAC/MDIO Multiplexed Pins (MII, RMII, and GMII Modes) BALL NUMBER DEVICE PIN NAME MII RMII GMII (MAC_SEL = (MAC_SEL = (MAC_SEL = 00b) 01b) 10b) J2 MRXD0/RMRXD0 MRXD0...
Page 190 - Interface Mode Clocking
www.ti.com PRODUCT PREVIEW TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Interface Mode Clocking The on-chip PLL2 and PLL2 Controller generate all the clocks to the EMAC module. When enabled, theinput clock to the PLL2 Controller (CLKIN2) must have a 2...
Page 194 - Table 7-73. EMAC Control Module Registers
www.ti.com PRODUCT PREVIEW TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-72. EMAC Statistics Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02C8 0228 RXFILTERED Filtered Receive Frames Register 02C8 022C RXQOSFILTERED Received QO...
Page 195 - EMAC MII and GMII Electrical Data/Timing
www.ti.com PRODUCT PREVIEW 7.14.3 EMAC Electrical Data/Timing MRCLK (Input) 2 3 1 4 4 MTCLK (Input) 2 3 1 4 4 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 7.14.3.1 EMAC MII and GMII Electrical Data/Timing Table 7-75. Timing Requirements for MRCLK - M...
Page 202 - Transmit
www.ti.com PRODUCT PREVIEW TXC (at DSP) (B) TXD[3:0] (A) TXCTL (A) 5 6 1st Half-byte TXERR TXEN 2nd Half-byte 1 2 Internal TXC TXC at DSP pins 4 4 2 3 1 TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-88. Switching Characteristics Over Recommende...
Page 206 - Table 7-94. Timing Requirements for Timer Inputs
www.ti.com PRODUCT PREVIEW 7.15.3 Timers Electrical Data/Timing TINPLx TOUTLx 4 3 2 1 TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-94. Timing Requirements for Timer Inputs (1) (see Figure 7-73 ) -720-850 NO. UNIT -1000 MIN MAX 1 t w(TINPH) Pul...
Page 207 - Section 4; Table 7-96. Default Values for PCI Configuration; DEFAULT
www.ti.com PRODUCT PREVIEW 7.16 Peripheral Component Interconnect (PCI) 7.16.1 PCI Device-Specific Information TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 The C6454 DSP supports connections to a PCI backplane via the integrated PCI master/slave busi...
Page 208 - PCI HOST ACCESS
www.ti.com PRODUCT PREVIEW 7.16.2 PCI Peripheral Register Description(s) TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-97. PCI Configuration Registers PCI HOST ACCESS ACRONYM PCI HOST ACCESS REGISTER NAME HEX ADDRESS OFFSET 0x00 PCIVENDEV Vendo...
Page 209 - Table 7-98. PCI Back End Configuration Registers; DSP ACCESS
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-98. PCI Back End Configuration Registers DSP ACCESS ACRONYM DSP ACCESS REGISTER NAME HEX ADDRESS RANGE 02C0 0000 - 02C0 000F - Reserved 02C0 0010 PCISTATSET PCI Status Se...
Page 211 - Table 7-100. PCI Hook Configuration Registers
www.ti.com PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-100. PCI Hook Configuration Registers DSP ACCESS ACRONYM DSP ACCESS REGISTER NAME HEX ADDRESS RANGE 02C0 0394 PCIVENDEVPRG PCI Vendor ID and Device ID Program Register 02...
Page 212 - HEX ADDRESS OFFSET
www.ti.com PRODUCT PREVIEW TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-101. PCI External Memory Space (continued) HEX ADDRESS OFFSET ACRONYM REGISTER NAME 4780 0000 - 47FF FFFF - PCI Master Window 15 4800 0000 - 487F FFFF - PCI Master Window ...
Page 215 - Table 7-103. Timing Requirements for GPIO Inputs
www.ti.com PRODUCT PREVIEW 7.17.3 GPIO Electrical Data/Timing GPIx GPOx 4 3 2 1 TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 7-103. Timing Requirements for GPIO Inputs (1) (2) (see Figure 7-74 ) -720-850 NO. UNIT -1000 MIN MAX 1 t w(GPIH) Pulse...
Page 217 - Mechanical Data; Packaging Information; AIR FLOW
www.ti.com PRODUCT PREVIEW 8 Mechanical Data 8.1 Thermal Data 8.2 Packaging Information TMS320C6454 Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 Table 8-1 shows the thermal resistance characteristics for the PBGA - ZTZ/GTZ mechanical package. Table 8-1. Thermal ...
Page 218 - SEE
www.ti.com PRODUCT PREVIEW Revision History TMS320C6454Fixed-Point Digital Signal Processor SPRS311A – APRIL 2006 – REVISED DECEMBER 2006 This data sheet revision history highlights the technical changes made to the SPRS311 device-specificdata sheet to make it an SPRS311A revision. Scope: Applicable...
Page 222 - PACKAGING INFORMATION; PACKAGE OPTION ADDENDUM
PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) TMS320C6454BZTZ ACTIVE FCBGA ZTZ 697 44 Pb-Free (RoHS Exempt) SNAGCU Level-4-260C-72HR TMS320C6454BZTZ7 ACTIVE FCBGA ZTZ 697 44 Pb-Free (RoHS Exempt) SNAGCU...
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