Texas Instruments TMS320C6202 - Manuals

Page 3 - FIXED-POINT DIGITAL SIGNAL PROCESSOR; description; debugger interface for visibility into source code; device characteristics; Table 1. Characteristics of the ’C6202 Processors; ADV

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 3 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 description The TMS320C62x DSPs (including the TMS320C6202 device) are the fixed-point DSP family in theTMS320C6000 platform. The TMS320C6202 (’C6202) devi...

Page 4 - functional block diagram

TMS320C6202FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 functional block diagram EMIF Timers Interrupt Selector McBSPs XB Control DMA Control EMIF Control Expansion Bus (XB) Interface PLL Power Down Boot- Config....

Page 5 - CPU description

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 5 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 CPU description The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight32-bit instructions to the eight ...

Page 8 - signal groups description; Figure 3. CPU Signals

TMS320C6202FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 signal groups description TRST EXT_INT7 Clock/PLL IEEE Standard 1149.1 (JTAG) Emulation Reserved Reset and Interrupts DMA Status Power-Down Status Control/S...

Page 9 - Figure 4. Peripheral Signals

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 9 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 signal groups description (continued) CE3 ARE ED[31:0] CE2CE1CE0 EA[21:2] BE3BE2BE1BE0 HOLDHOLDA TOUT1 CLKX1 FSX1 DX1 CLKR1 FSR1 DR1 CLKS1 AOEAWEARDY SDA10...

Page 11 - Signal Descriptions

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 11 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Signal Descriptions SIGNAL PIN NO. TYPE† DESCRIPTION NAME GJL GLS TYPE† DESCRIPTION CLOCK/PLL CLKIN C12 B10 I Clock Input CLKOUT1 AD20 Y18 O Clock output ...

Page 22 - development support; The; Table 2. TMS320C6xx Development-Support Tools

TMS320C6202FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 development support Texas Instruments offers an extensive line of development tools for the ’C6200 generation of DSPs, includingtools to evaluate the perfo...

Page 23 - Device development evolutionary flow:

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 23 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 device and development-support tool nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all ...

Page 25 - documentation support

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 25 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 documentation support Extensive documentation supports all TMS320 family generations of devices from product announcementthrough applications development....

Page 27 - clock PLL; input and output clocks section for input; Figure 6. PLL Block Diagram; power-supply sequencing

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 27 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 clock PLL All of the internal ’C6202 clocks are generated from a single source through the CLKIN pin. This source clockeither drives the PLL, which genera...

Page 28 - recommended operating conditions

TMS320C6202FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 absolute maximum ratings over operating case temperature range (unless otherwise noted) † Supply voltage range, CV DD (see Note 1) – 0.3 V to 2.3 V . . . ....

Page 29 - PARAMETER MEASUREMENT INFORMATION; signal transition levels

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 29 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 PARAMETER MEASUREMENT INFORMATION Tester Pin Electronics Vref IOL CT = 30 pF† IOH OutputUnderTest 50 Ω † Typical distributed load circuit capacitance sign...

Page 30 - Figure 8. CLKIN Timings; timing requirements for XCLKIN; Figure 9. XCLKIN Timings

TMS320C6202FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 30 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 INPUT AND OUTPUT CLOCKS timing requirements for CLKIN † (see Figure 8) ’C6202-200 ’C6202-233 ’C6202-250 NO. CLKMODE = x4 CLKMODE = x1 CLKMODE = x4 CLKMODE ...

Page 31 - switching characteristics for CLKOUT1; Figure 10. CLKOUT1 Timings; switching characteristics for CLKOUT2; Figure 11. CLKOUT2 Timings

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 31 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics for CLKOUT1 †‡ (see Figure 10) NO. PARAMETER ’C6202-200’C6202-233’C6202-250 UNIT NO. PARAMET...

Page 32 - switching characteristics for XFCLK; Figure 12. XFCLK Timings

TMS320C6202FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics for XFCLK †‡ (see Figure 12) NO. PARAMETER ’C6202-200’C6202-233’C6202-250 UNIT MIN MAX 1 tc(X...

Page 33 - ASYNCHRONOUS MEMORY TIMING

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 33 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cycles † (see Figure 13 – Figure 14) NO. ’C6202-200’C6202-233’C6202-250 UNIT MIN MA...

Page 35 - SYNCHRONOUS-BURST MEMORY TIMING

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 35 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SYNCHRONOUS-BURST MEMORY TIMING timing requirements for synchronous-burst SRAM cycles (see Figure 15) NO ’C6202-200 ’C6202-233 ’C6202-250 UNIT NO. MIN MAX...

Page 36 - Figure 15. SBSRAM Read Timing; Figure 16. SBSRAM Write Timing

TMS320C6202FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) CLKOUT2 CEx BE[3:0] EA[21:2] ED[31:0] SDCAS/SSADS† SDRAS/SSOE† SDWE/SSWE† BE1 BE2 BE3 BE4 A1 A2 A3 A4 Q1 Q2 Q3 ...

Page 37 - SYNCHRONOUS DRAM TIMING

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 37 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SYNCHRONOUS DRAM TIMING timing requirements for synchronous DRAM cycles (see Figure 17) NO ’C6202-200 ’C6202-233 ’C6202-250 UNIT NO. MIN MAX MIN MAX MIN M...

Page 39 - Figure 19. SDRAM ACTV Command

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 39 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SYNCHRONOUS DRAM TIMING (CONTINUED) CLKOUT2 CEx BE[3:0] EA[15:2] ED[31:0] SDA10 SDRAS/SSOE† SDCAS/SSADS† SDWE/SSWE† Bank Activate/Row Address Row Address ...

Page 41 - timing requirements for the HOLD/HOLDA cycles

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 41 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 HOLD/HOLDA TIMING timing requirements for the HOLD/HOLDA cycles † (see Figure 23) NO. ’C6202-200’C6202-233’C6202-250 UNIT MIN MAX 3 toh(HOLDAL-HOLDL)Hold ...

Page 43 - Figure 24. Reset Timing

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 43 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 RESET TIMING (CONTINUED) 1 2 2 10 9 8 7 4 3 CLKOUT1 RESET CLKOUT2 HIGH GROUP† LOW GROUP† Z GROUP† 6 5 12 11 XD[31:0]‡ † High group consists of: XFCLK Low ...

Page 44 - Figure 25. Interrupt Timing

TMS320C6202FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 EXTERNAL INTERRUPT TIMING timing requirements for interrupt response cycles † (see Figure 25) NO. ’C6202-200’C6202-233’C6202-250 UNIT MIN MAX 2 tw(ILOW) Wi...

Page 45 - EXPANSION BUS SYNCHRONOUS FIFO TIMING

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 45 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 EXPANSION BUS SYNCHRONOUS FIFO TIMING timing requirements for synchronous FIFO interface (see Figure 26, Figure 27, and Figure 28) NO. MIN MAX UNIT 5 tsu(...

Page 46 - EXPANSION BUS SYNCHRONOUS FIFO TIMING (CONTINUED); Figure 27. FIFO Read Timing

TMS320C6202FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 EXPANSION BUS SYNCHRONOUS FIFO TIMING (CONTINUED) XA1 XA2 XA3 XA4 D1 D2 D3 D4 6 5 4 4 3 3 2 2 1 1 XFCLK XCEx XBE[3:0]/XA[5:2]† XOE XRE XWE/XWAIT‡ XD[31:0] ...

Page 47 - EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 47 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING timing requirements for asynchronous peripheral cycles † (see Figure 29–Figure 30) NO. ’C6202-200’C6202-233’C...

Page 48 - EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING (CONTINUED); Figure 29. Expansion Bus Asynchronous Peripheral Read Timing

TMS320C6202FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING (CONTINUED) 9 9 8 8 7 7 6 6 5 4 3 2 1 1 CLKOUT1 XCEx XBE[3:0]/XA[5:2]† XD[31:0] XOE XRE XWE/XWAIT‡ XRDY§ Setup...

Page 49 - EXPANSION BUS SYNCHRONOUS HOST PORT TIMING

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 49 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 EXPANSION BUS SYNCHRONOUS HOST PORT TIMING timing requirements with external device as bus master (see Figure 31 and Figure 32) NO. MIN MAX UNIT 1 tsu(XCS...

Page 50 - EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED); Figure 31. External Host as Bus Master—Read

TMS320C6202FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED) D1 D2 D3 D4 15 13 12 11 10 9 10 9 8 7 8 7 6 5 4 3 2 1 XCLKIN XCS XAS XCNTL XW/R† XW/R† XBE[3:0]/XA[5...

Page 51 - Figure 32. External Host as Bus Master—Write

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 51 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED) XBE1 XBE2 XBE3 XBE4 D1 D2 D3 D4 19 18 10 9 10 9 17 16 6 5 4 3 2 1 XCLKIN XCS XAS XCNTL XW/R† XW/R† ...

Page 54 - Figure 35. ’C6202 as Bus Master—BOFF Operation

TMS320C6202FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 54 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED) Addr D1 D2 15 14 12 11 8 7 6 5 4 4 2 2 1 1 XCLKIN XAS XW/R† XW/R† XBLAST‡ XD[31:0] XRDY XBOFF XHOLD¶...

Page 55 - EXPANSION BUS ASYNCHRONOUS HOST PORT TIMING; Figure 36. External Device as Asynchronous Master—Read

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 55 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 EXPANSION BUS ASYNCHRONOUS HOST PORT TIMING timing requirements with external device as asynchronous bus master † (see Figure 36 and Figure 37) NO. MIN MA...

Page 56 - EXPANSION BUS ASYNCHRONOUS HOST PORT TIMING (CONTINUED); Figure 37. External Device as Asynchronous Master—Write

TMS320C6202FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 56 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 EXPANSION BUS ASYNCHRONOUS HOST PORT TIMING (CONTINUED) word 9 9 14 13 14 13 4 3 4 3 4 3 4 3 12 11 12 11 4 3 4 3 10 10 XCS XCNTL XBE[3:0]/XA[5:2]† XR/W‡ XR...

Page 57 - Figure 38. Expansion Bus Arbitration—Internal Arbiter Enabled

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 57 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 XHOLD/XHOLDA TIMING timing requirements for expansion bus arbitration (internal arbiter enabled) † (see Figure 38) NO. MIN MAX UNIT 3 toh(XHDAH-XHDH) Outp...

Page 58 - Figure 39. Expansion Bus Arbitration—Internal Arbiter Disabled

TMS320C6202FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 58 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 XHOLD/XHOLDA TIMING (CONTINUED) switching characteristics for expansion bus arbitration (internal arbiter disabled) † (see Figure 39) NO. PARAMETER MIN MAX...

Page 59 - MULTICHANNEL BUFFERED SERIAL PORT TIMING

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 59 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MULTICHANNEL BUFFERED SERIAL PORT TIMING timing requirements for McBSP †‡ (see Figure 40) NO. ’C6202-200’C6202-233’C6202-250 UNIT MIN MAX 2 tc(CKRX) Cycle...

Page 61 - MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED); Figure 40. McBSP Timings

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 61 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) Bit(n-1) (n-2) (n-3) Bit 0 Bit(n-1) (n-2) (n-3) 14 13 12 11 10 9 3 3 2 8 7 6 5 4 4 3 1 3 2 CLKS CLKR ...

Page 69 - switching characteristics for DMAC outputs; Figure 46. DMAC Timing; timing requirements for timer inputs; Figure 47. Timer Timing

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 69 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 DMAC, TIMER, POWER-DOWN TIMING switching characteristics for DMAC outputs † (see Figure 46) NO. PARAMETER ’C6202-200’C6202-233’C6202-250 UNIT MIN MAX 1 tw...

Page 70 - switching characteristics for power-down outputs

TMS320C6202FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 70 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 DMAC, TIMER, POWER-DOWN TIMING (CONTINUED) switching characteristics for power-down outputs † (see Figure 48) NO. PARAMETER ’C6202-200’C6202-233’C6202-250 ...

Page 71 - JTAG TEST-PORT TIMING; switching characteristics for JTAG test port (see Figure 49)

TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 71 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 JTAG TEST-PORT TIMING timing requirements for JTAG test port (see Figure 49) NO. ’C6202-200’C6202-233’C6202-250 UNIT MIN MAX 1 tc(TCK) Cycle time, TCK 50 ...

Page 72 - MECHANICAL DATA; PLASTIC BALL GRID ARRAY

TMS320C6202FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 72 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MECHANICAL DATA GJL (S-PBGA-N352) PLASTIC BALL GRID ARRAY 25,00 TYP 0,50 AC W U AA AE R N L J G E A C 26 22 20 16 12 14 18 10 8 6 2 Seating Plane 4 4173516...

Page 74 - IMPORTANT NOTICE; Copyright

IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinueany product or service without notice, and advise customers to obtain the latest version of relevant informationto verify, before placing orders, that information being r...