Texas Instruments SPRU938B - Manuals

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Manual Texas Instruments SPRU938B

Summary

Page 3 - Contents

Contents Preface ............................................................................................................................... 7 1 Introduction ................................................................................................................ 8 1.1 Purpose of the Peri...

Page 7 - Read This First; About This Manual; This document uses the following conventions.; Related Documentation From Texas Instruments; . Tip: Enter the literature number in the search box; Trademarks; VLYNQ is a trademark of Texas Instruments.

Preface SPRU938B – September 2007 Read This First About This Manual This document describes the VLYNQ port in the TMS320DM643x Digital Media Processor (DMP). Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the follo...

Page 8 - Introduction; Purpose of the Peripheral

1 Introduction 1.1 Purpose of the Peripheral 1.2 Features User's Guide SPRU938B – September 2007 VLYNQ Port The VLYNQ™ communications interface port is a low pin count, high-speed, point-to-point serial interfacein the TMS320DM643x Digital Media Processor (DMP) used for connecting to host processors...

Page 9 - Figure 1; Figure 1. VLYNQ Port Functional Block Diagram

www.ti.com 1.3 Functional Block Diagram Slave config bus Interface Master config Interface bus VLYNQ module VLYNQ register access CPU/EDMA initiated transfers to remote device Off chip (remote) device access System CPU/EDMA memory System VLYNQ_SCRUN VLYNQ_CLOCK VLYNQ_RXD[3:0] VLYNQ_TXD[3:0] INT55 in...

Page 10 - Clock Control; VLYNQ; Peripheral Architecture; The reset value of the CLKDIR bit is 0 (external clock source).; Figure 2. External Clock Block Diagram

www.ti.com 2 Peripheral Architecture 2.1 Clock Control VLYNQ CLKDIR=0 DMxxx device VLYNQ_CLK VLYNQ CLKDIR=0 VLYNQ device VLYNQ CLKDIR=1 DMxxx device VLYNQ_CLK VLYNQ CLKDIR=1 VLYNQ device VLYNQ internal sys clk Don’tcare Peripheral Architecture This section discusses the architecture and basic functi...

Page 11 - The VLYNQ interface signals are shown in; Table 1. VLYNQ Signal Descriptions; Pin Name; Appendix A

www.ti.com 2.2 Signal Descriptions 2.3 Pin Multiplexing 2.4 Protocol Description Peripheral Architecture The VLYNQ module on the DM643x device supports 1 to 4 bit-wide RX/TX configurations. Chip-level pinmultiplexing registers control the configuration. See the pin multiplexing information in the de...

Page 12 - VLYNQ Functional Description; Figure 4; Figure 4. VLYNQ Module Structure

www.ti.com 2.5 VLYNQ Functional Description Address translation commands Outbound Outboundcommand FIFO data Return FIFO data FIFO Return command Inbound FIFO Registers translation Address TxSM 8B/10B encoding Serializer commands Inbound RxSM Deserializer decoding 8B/10B SerialTxData SerialTxClk Seri...

Page 13 - Write Operations; The data flow between two VLYNQs that are connected is shown in; Figure 5. Write Operations

www.ti.com 2.5.1 Write Operations Address translation commands Outbound Outboundcommand FIFO data Return FIFO data FIFO Return command Inbound FIFO Registers translation Address TxSM 8B/10B encoding Serializer commands Inbound RxSM Deserializer decoding 8B/10B SerialTxData SerialRxData System clock ...

Page 14 - Read Operations; Figure 6; Figure 6. Read Operations

www.ti.com 2.5.2 Read Operations Address translation commands Outbound Outboundcommand FIFO data Return FIFO data FIFO Return command Inbound FIFO Registers translation Address TxSM 8B/10B encoding Serializer commands Inbound RxSM Deserializer decoding 8B/10B SerialTxData SerialRxData System clock A...

Page 15 - Initialization; Appendix B

www.ti.com 2.6 Initialization 2.7 Auto-Negotiation Peripheral Architecture Note: Not servicing read operations results in deadlock. The only way to recover from a deadlocksituation is to perform a hard reset. Read operations are typically not serviced due to readrequests that are issued to a non-exi...

Page 16 - Address Translation; Figure 7

www.ti.com 2.8 Address Translation Peripheral Architecture Remote VLYNQ device(s) are memory mapped to the local (host) device’s address space when a link isestablished (this is similar to any other on-chip peripherals). Enumerating the VLYNQ devices (single ormultiple) into a coherent memory map fo...

Page 17 - Figure 7. Example Address Memory Map; Table 2; Register

www.ti.com Map region 1 Map region 2 Map region 3 Map region 4 0400:0000h (4C00:0000h on DM643x device) 0800:0000h 07FF:FFFFh 0800:0100h 0800:00FFh 0801:0100h 0801:00FFh 0841:00FFh Map region 1 Map region 2 Map region 3 Map region 4 DMxxx device (local) Remote VLYNQ device 0000:0000h 03FF:FFFFh0400:...

Page 18 - Table 3

www.ti.com Peripheral Architecture DM643x VLYNQ Module: 4C00 : 0054h Initial address at the slave configuration bus 0000 : 0054h Initial address [25:0] at the slave configuration bus interface subtract 0000 : 0000h TX address map register (there is no need to change the reset value of theDM643x devi...

Page 19 - Flow Control; Example 1. Address Translation Example

www.ti.com 2.9 Flow Control Peripheral Architecture Example 1. Address Translation Example The remote address 0400:0154h (or 0000 0054h) was translated to 8200:0054h on the DM643x (local)device in this example. The translated address for packets received on the serial interface is determined as foll...

Page 20 - Reset Considerations; Software Reset Considerations; Interrupt Support; Interrupt Events and Requests; . Additionally, there is a software reset; CAUTION; Writing directly to the INTPENDSET

www.ti.com 2.10 Reset Considerations 2.10.1 Software Reset Considerations 2.10.2 Hardware Reset Considerations 2.11 Interrupt Support 2.11.1 Interrupt Events and Requests Peripheral Architecture Peripheral clock and reset control is done through the power and sleep controller (PSC) module that isinc...

Page 21 - Writes to Interrupt Pending/Set Register; The VLYNQ interrupt generation mechanism is shown in; Figure 8. Interrupt Generation Mechanism Block Diagram

www.ti.com VLYNQ interrupt pending/set register (INTPENDSET) VLYNQ Status/clear register (INTSTATCLR) OR Transmit serialinterrupt packet VLQINT (INT55) 14 0 INTLOCAL VLYNQ control register (CTRL) Serial bus error (LERROR/RERROR) CPU writes Serial interruptpacket fromremote device INTLOCAL=1 INTLOCAL...

Page 22 - EDMA Event Support; Set the INT2CFG bit to 1 in the VLYNQ control register (CTRL).

www.ti.com 2.11.3 Remote Interrupts 2.11.4 Serial Bus Error Interrupts 2.12 EDMA Event Support Peripheral Architecture Remote interrupts occur when an interrupt packet is received over the serial interface from a remotedevice. The interrupt status is extracted from the packet and written to a locati...

Page 23 - The power conservation modes that are available via the PSC are:

www.ti.com 2.13 Power Management 2.14 Endianness Considerations 2.15 Emulation Considerations Peripheral Architecture The VLYNQ module can be placed in reduced-power modes to conserve power during periods of lowactivity. The power management of the VLYNQ module is controlled by the processor Power a...

Page 24 - VLYNQ Port Registers; Table 4; Table 4. VLYNQ Register Address Space; Table 5; Table 5. VLYNQ Port Controller Registers

www.ti.com 3 VLYNQ Port Registers VLYNQ Port Registers Table 4 describes the address space for the VLYNQ registers and memory. Table 4. VLYNQ Register Address Space Block Name Start Address End Address Size VLYNQ Control Registers 01E0 1000h 01E0 11FFh 512 bytes Reserved 01E0 1200h 01E0 1FFFh - VLYN...

Page 25 - Figure 9; Bit

www.ti.com 3.1 Revision Register (REVID) VLYNQ Port Registers The revision register (REVID) contains the major and minor revisions for the VLYNQ module. The REVIDis shown in Figure 9 and described in Table 6 . Figure 9. Revision Register (REVID) 31 16 ID R-1h 15 8 7 0 REVMAJ REVMIN R-2h R-6h LEGEND:...

Page 26 - and described in

www.ti.com 3.2 Control Register (CTRL) VLYNQ Port Registers The control register (CTRL) determines operation of the VLYNQ module. The CTRL is shown in Figure 10 and described in Table 7 . Figure 10. Control Register (CTRL) 31 30 29 27 26 24 23 22 21 20 19 18 16 PMEN SCLKPUDIS Reserved RXSAMPELVAL RT...

Page 31 - Table 12. Interrupt Pointer Register (INTPTR) Field Descriptions

www.ti.com 3.6 Interrupt Pending/Set Register (INTPENDSET) 3.7 Interrupt Pointer Register (INTPTR) VLYNQ Port Registers The interrupt pending/set register (INTPENDSET) indicates the pending interrupt status when theINTLOCAL bit in the control register (CTRL) is not set. When the interrupt packet is ...

Page 33 - Receive Address Map Size 1 Register (RAMS1)

www.ti.com 3.9 Receive Address Map Size 1 Register (RAMS1) 3.10 Receive Address Map Offset 1 Register (RAMO1) VLYNQ Port Registers The receive address map size 1 register (RAMS1) is used to identify the intended destination of inboundserial packets. The RAMS1 is shown in Figure 17 and described in T...

Page 37 - Table 23. Auto Negotiation Register (AUTNGO) Field Descriptions

www.ti.com 3.17 Chip Version Register (CHIPVER) 3.18 Auto Negotiation Register (AUTNGO) VLYNQ Port Registers VLYNQ allows inter-connection of many VLYNQ devices. In order for software to control the devicefunctions, there must be a mechanism that allows the software to identify VLYNQ devices. Each d...

Page 38 - Remote Configuration Registers; The remote configuration registers listed in; Table 24. VLYNQ Port Remote Controller Registers; Offset

www.ti.com 4 Remote Configuration Registers Remote Configuration Registers The remote configuration registers listed in Table 24 are the same registers as previously described, but they are for the remote VLYNQ device. Note: Before attempting to access the remote registers (offsets 80h through C0h) ...

Page 39 - Appendix A VLYNQ Protocol Specifications

www.ti.com Appendix A VLYNQ Protocol Specifications A.1 Introduction A.2 Special 8b/10b Code Groups A.3 Supported Ordered Sets Appendix A VLYNQ relies on 8b/10b block coding to minimize the number of serial pins and allow for in-band packetdelineation and control. The following sections include gene...

Page 40 - VLYNQ 2.0 Packet Format; The byte disable symbol masks bytes for write operations.

www.ti.com A.3.1 Idle (/I/) A.3.2 End of Packet (/T/) A.3.3 Byte Disable (/M/) A.3.4 Flow Control Enable (/P/) A.3.5 Flow Control Disable (/C/) A.3.6 Error Indication (/E/) A.3.7 Init0 (/0/) A.3.8 Init1 (/1/) A.3.9 Link (/L/) A.4 VLYNQ 2.0 Packet Format bytecnt 10 bits cmd 2 10 bits cmd 1 10 bits ad...

Page 41 - Field

www.ti.com VLYNQ 2.0 Packet Format Table A-3. Packet Format (10-bit Symbol Representation) Description Field Value Description PKTTYPE[3:0] This field indicates the packet type. 0000 Reserved 0001 Write with address increment. 0010 Reserved 0011 Write 32-bit word with address increment. 0100 Reserve...

Page 42 - . This protocol can be extended to apply to multiple channels

www.ti.com A.5 VLYNQ 2.X Packets VLYNQ 2.X Packets An example of what can happen to a write burst due to remote and local FIFO state changes and the linkpulse timer expiring is shown in Example A-1 . This protocol can be extended to apply to multiple channels; therefore, the data return channel is l...

Page 44 - Appendix B Write/Read Performance; encoding is removed, the maximum write rate is 396

www.ti.com Appendix B Write/Read Performance B.1 Introduction B.2 Write Performance Appendix B The following sections discuss the write versus read performance and how the throughput (read or write)should be calculated for a given data width and serial clock frequency. Note: The data and throughput ...

Page 45 - Write Performance

www.ti.com Write Performance Table B-1. Scaling Factors Burst Size in 32-bit words Data Bytes Overhead Bytes Scaling Factor 1 4 6 40% 4 16 7 69.56% 8 32 7 82.05% 16 64 7 90.14% Table B-2. Expected Throughput (VLYNQ Interface Running at 76.5 MHZ and 99 MHZ) Interface Running at 76.5 MHZ Interface Run...

Page 46 - Read Performance; Table B-3. Relative Performance with Various Latencies; Throughput

www.ti.com B.3 Read Performance Read Performance Since reads must complete a transmit-remote read-receive cycle before starting another read transaction,the data throughput is lower as compared to writes. There is latency involved in reading the data from theremote device; and in some cases, a local...

Page 47 - Appendix C Revision History; Appendix C; Reference

www.ti.com Appendix C Revision History Appendix C Table C-1 lists the changes made since the previous version of this document. Table C-1. Document Revision History Reference Additions/Modifications/Deletions Section 2.8 Changed fourth paragraph. Added NOTE. Section 3.17 Changed paragraph. Figure 25...

Page 48 - IMPORTANT NOTICE; Products

IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.Customers should obtain the l...