Texas Instruments SM320F2812-HT - Manuals

Page 2 - Features

SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Contents 1 Features ........................................................................................................................... 11 1.1 SUPPORTS EXTREME TEMPERATURE APPLICATIONS ...........................................

Page 4 - Mechanical Data

SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 6.20 SPI Slave Mode Timing ................................................................................................. 113 6.21 External Interface (XINTF) Timing ....................................................................

Page 9 - Minimum Required Wait-States at Different Frequencies

SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 6-64 Minimum Required Wait-States at Different Frequencies ................................................................ 149 Copyright © 2009–2010, Texas Instruments Incorporated List of Tables 9

Page 11 - Digital Signal Processor; xxx

SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Digital Signal Processor Check for Samples: SM320F2812-HT 1 Features 12 • High-Performance Static CMOS Technology • 128 Bit Security Key/Lock – 150 MHz (6.67 ns Cycle Time) – Protects Flash/ROM/OTP and L0/L1 SARAM – Low Power (1.8 V ...

Page 12 - SUPPORTS EXTREME TEMPERATURE APPLICATIONS

SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com xxx 1.1 SUPPORTS EXTREME TEMPERATURE APPLICATIONS • Controlled Baseline • One Assembly/Test Site • One Fabrication Site • Available in Extreme (–55°C/220°C) Temperature Range (2) • Extended Product Life Cycle • Extended Product-Chang...

Page 13 - Introduction; Description

SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 2 Introduction This section provides a summary of the device features, lists the pin assignments, and describes thefunction of each pin. This document also provides detailed descriptions of peripherals, electricalspecifications, para...

Page 14 - Device Summary; provides a summary of the device features.; FEATURE

SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 2.2 Device Summary Table 2-1 provides a summary of the device features. Table 2-1. Hardware Features FEATURE F2812 Instruction Cycle (at 150 MHz) 6.67 ns Single-Access RAM (SARAM) (16 bit word) 18K 3.3 V On-Chip Flash (16 bit word) 1...

Page 15 - Die Layout; for a description of each pad's

SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 2.3 Die Layout The SM320F2812 die layout is shown in Figure 2-1 . See Table 2-3 for a description of each pad's function. Figure 2-1. SM320F2812 Die Layout Table 2-2. Bare Die Information DIE PAD DIE PAD DIE BACKSIDE BACKSIDE DIE SIZ...

Page 16 - Pin Assignments; See

V D D AIO 1 130 172 ADCINB0 ADCINB1 ADCINB2 ADCINB3 ADCINB4 ADCINB5 ADCINB6 ADCINB7 ADCREFM ADCREFP A VSSREFBG A VDDREFBG V DD A1 V SSA1 ADCRESEXT MC XMP/ XA[0] MDRA XD[0] MDXA V DD XD[1] MCLKRA MFSXA XD[2] MCLKXA MFSRA XD[3] V DDIO V SS XD[4] SPICLKA SPISTEA XD[5] V DD V SS XD[6] SPISIMO A SPISOMIA...

Page 17 - Signal Descriptions

SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 2.5 Signal Descriptions Table 2-3 specifies the signals on the F2812 device. All digital inputs are TTL-compatible. All outputs are 3.3 V with CMOS levels. Inputs are not 5 V tolerant. A 100 m A (or 20 m A) pullup/pulldown is used. T...

Page 26 - NOTE

SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Signal Descriptions (Continued) (1) (continued) PIN NO. PERIPHERAL DIE PAD DIE PAD GPIO DIE PAD NO. I/O/Z (2) PU/PD (3) DESCRIPTION 172-PIN SIGNAL X-CENTER Y-CENTER HFG GPIOG OR SCI-B SIGNALS GPIO or SCI GPIOG4 SCITXDB (O) 88 102 509...

Page 28 - Memory Map

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Page 29 - Table 3-1. Addresses of Flash Sectors in F2812; ADDRESS RANGE

SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 3-1. Addresses of Flash Sectors in F2812 ADDRESS RANGE PROGRAM AND DATA SPACE 0x3D 8000 Sector J, 8K × 16 0x3D 9FFF 0x3D A000 Sector I, 8K × 16 0x3D BFFF 0x3D C000 Sector H, 16K × 16 0x3D FFFF 0x3E 0000 Sector G, 16K × 16 0x3E ...

Page 30 - I/O space is not supported on the F2812 XINTF.; AREA

SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com memory such that the vector table is fetched externally. The Boot ROM is disabled in this mode. Inmicrocomputer mode, Zone 7 is disabled such that the vectors are fetched from Boot ROM. This allowsthe user to either boot from on-chip...

Page 31 - Brief Descriptions; Data Writes; Peripheral Bus

SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 3.2 Brief Descriptions 3.2.1 C28x CPU The C28x™ DSP generation is the newest member of the TMS320C2000™ DSP platform. The C28x issource code compatible to the 24x/240x DSP devices, hence existing 240x users can leverage theirsignific...

Page 32 - Flash; Boot ROM; shows the

SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com single step through non-time critical code while enabling time-critical interrupts to be serviced withoutinterference. The F2812 implements the real-time mode in hardware within the CPU. This is a uniquefeature to the F2812, no softw...

Page 33 - BOOT MODE SELECTED; Security

SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 3-3. Boot Mode Selection GPIOF4 GPIOF12 GPIOF3 GPIOF2 BOOT MODE SELECTED (1) (SCITXDA) (MDXA) (SPISTEA) (SPICLK) (2) GPIO PU status (3) PU No PU No PU No PU Jump to Flash/ROM address 0x3F 7FF6A branch instruction must have been...

Page 36 - Register Map

SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 3.2.20 Serial Port Peripherals The F2812 supports the following serial communication peripherals: eCAN: This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, timestamping of messages, and is CAN 2.0B-compliant...

Page 39 - Device Emulation Registers; NAME; External Interface, XINTF; shows the F2812 XINTF signals.

SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 3.4 Device Emulation Registers These registers are used to control the protection mode of the C28x CPU and to monitor some criticaldevice signals. The registers are defined in Table 3-7 . Table 3-7. Device Emulation Registers NAME AD...

Page 40 - Figure 3-3. External Interface Block Diagram

XD(15:0) XA(18:0) XZCS6 XZCS7 XZCS6AND7 XZCS2 XWE XR/W XREADY XMP/MC XHOLD XHOLDA XCLKOUT XRD XINTF Zone 0 (8K × 16) XINTF Zone 1 (8K × 16) XINTF Zone 6 (512K × 16) XINTF Zone 7 (16K × 16) (mapped here if MP/MC = 1) 0x40 0000 0x3F C000 0x18 0000 0x10 0000 0x00 6000 0x00 4000 0x00 2000 0x00 0000 Data...

Page 41 - Table 3-8. XINTF Configuration and Control Register Mappings; Timing Registers; Table 3-9. XREVISION Register Bit Definitions

SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 The operation and timing of the external interface, can be controlled by the registers listed in Table 3-8 . Table 3-8. XINTF Configuration and Control Register Mappings NAME ADDRESS SIZE (×16) DESCRIPTION XINTF Timing Register, Zone...

Page 42 - MUX; Interrupts

C28x CPU PIE TIMER 2 (for RTOS) TIMER 0 Watchdog Peripherals (SPI, SCI, McBSP, CAN, EV, ADC) (41 Interrupts) 96 Interrupts † TINT0 Interrupt Control XNMICR(15:0) XINT1 Interrupt Control XINT1CR(15:0) XINT2 Interrupt Control XINT2CR(15:0) GPIO MUX WDINT INT1 to INT12 INT13 INT14 NMI XINT1CTR(15:0) XI...

Page 43 - Figure 3-5. Multiplexing of Interrupts Using the PIE Block; PIE INTERRUPTS

INT12 MUX INT11 INT2 INT1 CPU (Enable) (Flag) INTx INTx.8 PIEIERx(8:1) PIEIFRx(8:1) MUX INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1 From Peripherals or External Interrupts (Enable) (Flag) IER(12:1) IFR(12:1) Global Enable INTM 1 0 PIEACKx (Enable/Flag) SM320F2812-HT www.ti.com SGUS062A – JUNE 2...

Page 44 - Table 3-11. PIE Configuration and Control Registers

SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Table 3-11. PIE Configuration and Control Registers (1) NAME ADDRESS SIZE (×16) DESCRIPTION PIECTRL 0x0000-0CE0 1 PIE, Control Register PIEACK 0x0000-0CE1 1 PIE, Acknowledge Register PIEIER1 0x0000-0CE2 1 PIE, INT1 Group Enable Regis...

Page 45 - External Interrupts; Table 3-12. External Interrupts Registers

SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 3.6.1 External Interrupts Table 3-12. External Interrupts Registers NAME ADDRESS SIZE (×16) DESCRIPTION XINT1CR 0x00 7070 1 XINT1 control register XINT2CR 0x00 7071 1 XINT2 control register 0x00 7072 reserved 5 0x00 7076 XNMICR 0x00 ...

Page 46 - See Note A; System Control

See Note A SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 3.7 System Control This section describes the F2812 oscillator, PLL and clocking mechanisms, the watchdog function and thelow power modes. Figure 3-6 shows the various clock and reset domains in the F2812 device that are d...

Page 48 - OSC and PLL Block; shows the OSC and PLL block on the F2812.; Table 3-14. PLLCR Register Bit Definitions

X2 X1/XCLKIN On-Chip Oscillator (OSC) PLL Bypass /2 XF_XPLLDIS OSCCLK (PLL Disabled) Latch XPLLDIS XRS PLL 4-Bit PLL Select SYSCLKOUT 1 0 CLKIN CPU 4-Bit PLL Select XCLKIN PLL Block SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 3.8 OSC and PLL Block Figure 3-7 shows the OSC and ...

Page 49 - External Clock Signal; Crystal; Loss of Input Clock; PLL-Based Clock Module; The PLL-based clock module provides two modes of operation:; Table 3-15. Possible PLL Configuration Modes; PLL MODE; External Reference Oscillator Clock Option; Fundamental mode, parallel resonant

External Clock Signal (Toggling 0 −V DD ) C b1 (see Note A) X2 X1/XCLKIN X1/XCLKIN X2 Crystal C b2 (see Note A) (a) (b) NC SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 3.8.1 Loss of Input Clock In PLL enabled mode, if the input clock XCLKIN or the oscillator clock is removed or...

Page 50 - shows the various functional blocks within the watchdog module.

/512 OSCCLK WDCR (WDPS(2:0)) WDCLK WDCNTR(7:0) WDKEY(7:0) Bad Key Good Key 1 0 1 WDCR (WDCHK(2:0)) BadWDCHKKey WDCR (WDDIS) Clear Counter SCSR (WDENINT) Watchdog Prescaler Generate Output Pulse (512 OSCCLKs) 8-Bit Watchdog Counter CLR WDRST WDINT Watchdog 55 + AA Key Detector XRS Core-reset WDRST (S...

Page 51 - MODE; The various low-power modes operate as follows:

SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 3.12 Low-Power Modes Block The low-power modes on the F2812 are similar to the 240x devices. Table 3-16 summarizes the various modes. Table 3-16. F2812 Low-Power Modes MODE LPM(1:0) OSCCLK CLKIN SYSCLKOUT EXIT (1) Normal X,X on on on...

Page 52 - Enhanced controller area network (eCAN) module

Borrow Reset Timer Reload SYSCLKOUT TCR.4 (Timer Start Status) TINT 16-Bit Timer Divide-Down TDDRH:TDDR 32-Bit Timer Period PRDH:PRD 32-Bit Counter TIMH:TIM 16-Bit Prescale Counter PSCH:PSC Borrow SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 4 Peripherals The integrated periphe...

Page 55 - Table 4-2. Module and Signal Names for EVA and EVB

SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 4.2 Event Manager Modules (EVA, EVB) The event-manager modules include general-purpose (GP) timers, full-compare/PWM units, capture units,and quadrature-encoder pulse (QEP) circuits. EVA and EVB timers, compare units, and capture uni...

Page 58 - Programmable Deadband Generator

SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 4.2.1 General-Purpose (GP) Timers There are two GP timers. The GP timer x (x = 1 or 2 for EVA; x = 3 or 4 for EVB) includes: • A 16-bit timer, up-/down-counter, TxCNT, for reads or writes • A 16-bit timer-compare register, TxCMPR (do...

Page 60 - The digital value of the input analog voltage is derived by:

Input Ana log Voltage ADCLO 4096 , 3 - ´ SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 4.3 Enhanced Analog-to-Digital Converter (ADC) Module A simplified functional block diagram of the ADC module is shown in Figure 4-4. The ADC moduleconsists of a 12-bit ADC with a built-in sam...

Page 61 - Figure 4-4. Block Diagram of the F2812 ADC Module; shows the ADC pin connections for the; signals is as follows:

Result Registers EVB S/W ADCSOC EVA S/W Sequencer 2 Sequencer 1 SOC SOC ADC Control Registers 70B7h 70B0h 70AFh 70A8h Result Reg 15 Result Reg 8 Result Reg 7 Result Reg 1 Result Reg 0 Module ADC 12-Bit Analog MUX ADCINA0 ADCINA7 ADCINB0 ADCINB7 System Control Block High-Speed Prescaler HSPCLK ADCENC...

Page 62 - shows the ADC pin-biasing for internal reference and

ADCINA[7:0]ADCINB[7:0] ADCLO ADCBGREFIN † ADC External Current Bias Resistor ADCRESEXT ADCREFP V DDA1 V DDA2 V SSA1 V SSA2 AVDDREFBG AVSSREFBG V DDAIO V SSAIO V DD1 V SS1 Test Pin ADC Reference Positive Output ADCREFM ADC Reference Medium Output ADC Analog Power ADC Reference Power ADC Analog I/O Po...

Page 63 - Figure 4-6. ADC Pin Connections With External Reference

ADCINA[7:0]ADCINB[7:0] ADCLO ADCBGREFIN ADC External Current Bias Resistor ADCRESEXT ADCREFP V DDA1 V DDA2 V SSA1 V SSA2 AVDDREFBG AVSSREFBG V DDAIO V SSAIO V DD1 V SS1 Test Pin ADC Reference Positive Input ADCREFM ADC Reference Medium Input ADC Analog Power ADC Reference Power ADC Analog I/O Power ...

Page 65 - Enhanced Controller Area Network (eCAN) Module

SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 4.4 Enhanced Controller Area Network (eCAN) Module The CAN module has the following features: • Fully compliant with CAN protocol, version 2.0B • Supports data rates up to 1 Mbps • Thirty-two mailboxes, each with the following proper...

Page 66 - Figure 4-7. eCAN Block Diagram and Interface Circuit

Mailbox RAM (512 Bytes) 32-Message Mailbox of 4 × 32-Bit Words Memory Management Unit CPU Interface, Receive Control Unit, Timer Management Unit eCAN Memory (512 Bytes) Registers and Message Objects Control 32 32 Message Controller 32 32 32 32 32 32 eCAN Protocol Kernel Receive Buffer Transmit Buffe...

Page 68 - REGISTER NAME

SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com The CAN registers listed in Table 4-6 are used by the CPU to configure and control the CAN controller and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAMcan be accessed as 16 bits or...

Page 69 - Multichannel Buffered Serial Port (McBSP) Module

CLKSRG McBSP clock rate CLKG , 1 CLKGDIV = = + SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 4.5 Multichannel Buffered Serial Port (McBSP) Module The McBSP module has the following features: • Compatible to McBSP in TMS320C54x™/ TMS320C55x™ DSP devices, except the DMA features •...

Page 71 - provides a summary of the McBSP registers.

SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 4-7 provides a summary of the McBSP registers. Table 4-7. McBSP Register Summary ADDRESS TYPE RESET VALUE NAME DESCRIPTION 0x00 78xxh (R/W) (HEX) DATA REGISTERS, RECEIVE, TRANSMIT (1) – – – 0x0000 McBSP Receive Buffer Register ...

Page 73 - Serial Communications Interface (SCI) Module; Both pins can be used as GPIO if not used for SCI.

LSPCLK , (BRR 1) 8 + · LSPCLK , 16 6 150 MHz Max bit rate 9.375 10 b / s 2 8 = = ´ ´ SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 4.6 Serial Communications Interface (SCI) Module The F2812 device include two serial communications interface (SCI) modules. The SCI modules support...

Page 74 - Auto baud-detect hardware logic

SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com NOTE All registers in this module are 8-bit registers that are connected to Peripheral Frame 2.When a register is accessed, the register data is in the lower byte (7–0), and the upper byte(15–8) is read as zeros. Writing to the upper...

Page 75 - shows the SCI module block diagram.

TX FIFO _0 LSPCLK WUT Frame Format and Mode Even/Odd Enable Parity SCI RX Interrupt select logic BRKDT RXRDY SCIRXST.6 SCICTL1.3 8 SCICTL2.1 RX/BK INT ENA SCIRXD SCIRXST.1 TXENA SCI TX Interrupt select logic TX EMPTY TXRDY SCICTL2.0 TX INT ENA SCITXD RXENA SCIRXD RXWAKE SCICTL1.6 RX ERR INT ENA TXWA...

Page 76 - All four pins can be used as GPIO, if the SPI module is not used.

LSPCLK , (SPIBRR 1) + L S P C L K , 4 SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 4.7 Serial Peripheral Interface (SPI) Module The F2812 device includes the four-pin serial peripheral interface (SPI) module. The SPI is a high-speed,synchronous serial I/O port that allows a ser...

Page 77 - Delayed transmit control

SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Enhanced feature: • 16-level transmit/receive FIFO • Delayed transmit control The SPI port operation is configured and controlled by the registers listed in Table 4-10 . Table 4-10. SPI Registers (1) NAME ADDRESS SIZE (×16) DESCRIPTI...

Page 78 - is a block diagram of the SPI in slave mode.

S SPICTL.0 SPI INT FLAG SPI INT ENA SPISTS.6 S Clock Polarity Talk LSPCLK 4 5 6 1 2 3 0 0 1 2 3 SPI Bit Rate State Control SPIRXBUF Buffer Register Clock Phase Receiver Overrun Flag SPICTL.4 Overrun INT ENA SPICCR.3 − 0 SPIBRR.6 − 0 SPICCR.6 SPICTL.3 SPIDAT.15 − 0 SPICTL.1 M S M Master/Slave SPISTS....

Page 79 - GPIO MUX; lists the GPIO Mux Registers.; lists the GPIO Data Registers. For more information, see the

SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 4.8 GPIO MUX The GPIO Mux registers are used to select the operation of shared pins on the F2812 device. The pinscan be individually selected to operate as Digital I/O or connected to Peripheral I/O signals (via theGPxMUX registers)....

Page 82 - Software Development Tools; Device and Development Support Tool Nomenclature; TMS/SM—Fully qualified production device

SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 5 Development Support Texas Instruments (TI) offers an extensive line of development tools for the C28x™ generation of DSPs,including tools to evaluate the performance of the processors, generate code, develop algorithmimplementation...

Page 83 - Documentation Support

PREFIX SM 320 F 2812 HFG TMX = experimental deviceTMP = prototype deviceTMS = qualified deviceSM = commercial processing SMJ = MIL-PRF-38535 (QML) DEVICE FAMILY 320 = TMS320  DSP Family TECHNOLOGY PACKAGE TYPE † HFG = 172-pin CQFPKGD = Die DEVICE 2810 TEMPERATURE RANGE M S = -55°C to 220°C F = Flas...

Page 85 - Absolute Maximum Ratings; VALUE

SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Updated information on the TMS320™ DSP controllers can be found on the worldwide web at: http://www.ti.com . To send comments regarding this TMS320F281x/TMS320C281x data manual (literature numberSPRS174), use the commentsatbooks.sc.t...

Page 86 - Recommended Operating Conditions; Electrical Characteristics; Over recommended operating conditions (unless otherwise noted)

SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 6.2 Recommended Operating Conditions See (1) MIN NOM MAX UNIT V DDIO Device supply voltage, I/O 3.14 3.3 3.47 V 1.8 V (135 MHz) 1.71 1.8 1.89 V DD , V DD1 Device supply voltage, CPU V 1.9 V (150 MHz) 1.81 1.9 2 V SS Supply ground 0 V...

Page 87 - Hour

1.00E+06 1.00E+05 1.00E+04 1.00E+03 1.00E+02 70 150 200 220 Die Junction Temperature (°C) Hour s SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Figure 6-1. SM320F2812-HT Life Expectancy Curve Notes: 1. See data sheet for absolute maximum and minimum recommended operating conditio...

Page 88 - HALT and STANDBY modes cannot be used when the PLL is disabled.

SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 6.4 Current Consumption by Power-Supply Pins Over Recommended OperatingConditions During Low-Power Modes at 150-MHz SYSCLKOUT T A = –55°C to 125°C T A = 220°C MODE TEST CONDITIONS I DD I DDIO I DD3VFL I DDA (1) I DD I DDIO I DD3VFL I...

Page 89 - Current Consumption Graphs; Figure 6-2. Typical Current Consumption Over Frequency

0 50 100 150 200 250 0 20 40 60 80 100 120 140 160 SYSCLKOUT (MHz) IDD IDDIO IDD3VFL IDDA Total 3.3−V current Current (mA) 0 100 200 300 400 500 600 700 0 20 40 60 80 100 120 140 160 SYSCLKOUT (MHz) TOTAL POWER Power (mW) SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 6.5 Current...

Page 90 - Reducing Current Consumption; the clocks to various peripherals.; PERIPHERAL MODULE; Power Sequencing Requirements; and V

SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 6.6 Reducing Current Consumption 28x DSPs incorporate a unique method to reduce the device current consumption. A reduction in currentconsumption can be achieved by turning off the clock to any peripheral module which is not used in ...

Page 91 - The GPIO pins are undefined until V; Signal Transition Levels

See Figure 6-8, SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 6-2. Recommended Low-Dropout Regulators SUPPLIER PART NUMBER Texas Instruments TPS767D301 NOTE The GPIO pins are undefined until V DD = 1 V and V DDIO = 2.5 V. Figure 6-4. F2812 Typical Power-Up and Power-Down S...

Page 92 - Timing Parameter Symbology

0.4 V (V OL ) 20% 2.4 V (V OH ) 80% 0.8 V (V IL ) 10% 2.0 V (V IH ) 90% SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Figure 6-5. Output Levels Output transition times are specified as follows: • For a high-to-low transition, the level at which the output is said to be no longer...

Page 93 - Transmission Line; Tester Pin Electronics; Data Sheet Timing Reference Point; General Notes on Timing Parameters

Transmission Line 4.0 pF 1.85 pF Z0 = 50 Ω (see note) Tester Pin Electronics Data Sheet Timing Reference Point OutputUnderTest NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. ...

Page 94 - Device Clock Table; lists the cycle times of various clocks.; Clock Requirements and Characteristics

SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 6.12 Device Clock Table This section provides the timing requirements and switching characteristics for the various clock optionsavailable on the F2812 DSP. Table 6-3 lists the cycle times of various clocks. Table 6-3. Clock Table an...

Page 96 - MIN

See Note A See Note B SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown in Figure 6-8 is intended to illustrate the timing parameters only and may differ based on configurat...

Page 100 - is also the IDLE Mode Wake-Up Timing Requirements table.; Table 6-10. IDLE Mode Switching Characteristics

WAKE INT (see Note B) XCLKOUT (see Note A) A0−A15 t d(WAKE−IDLE) t w(WAKE−INT) SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 6.15 Low-Power Mode Wakeup Timing Table 6-10 is also the IDLE Mode Wake-Up Timing Requirements table. Table 6-10. IDLE Mode Switching Characteristics (1) ...

Page 101 - is also the STANDBY Mode Wake-Up Timing Requirements table.; Table 6-11. STANDBY Mode Switching Characteristics

SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 6-11 is also the STANDBY Mode Wake-Up Timing Requirements table. Table 6-11. STANDBY Mode Switching Characteristics (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Delay time, IDLE instruction t d(IDLE-XCOH) 32 × t c(SCO) 12 × t...

Page 102 - Figure 6-14. STANDBY Entry and Exit Timing

t w(WAKE-INT) t d(WAKE-STBY) t d(IDLE−XCOH) 32 SYSCLKOUT Cycles Wake−up Signal X1/XCLKIN XCLKOUT † STANDBY Normal Execution STANDBY Flushing Pipeline A B C D E F Device Status NOTES: A. IDLE instruction is executed to put the device into STANDBY mode. B. The PLL block responds to the STANDBY signal....

Page 103 - Table 6-12. HALT Mode Switching Characteristics; PARAMETER

SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 6-12. HALT Mode Switching Characteristics (1) PARAMETER MIN TYP MAX UNIT Delay time, IDLE instruction executed to XCLKOUT t d(IDLE-XCOH) 32 × t c(SCO) 45 × t c(SCO) Cycles high t w(WAKE-XNMI) Pulse duration, XNMI wakeup signal ...

Page 104 - Event Manager Interface; PWM refers to all PWM outputs on EVA and EVB.

SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com A. IDLE instruction is executed to put the device into HALT mode. B. The PLL block responds to the HALT signal. SYSCLKOUT is held for another 32 cycles before the oscillator is turnedoff and the CLKIN to the core is stopped. This 32-...

Page 105 - Table 6-13. PWM Switching Characteristics

t w(PWM) t d(PWM)XCO PWMx XCLKOUT (see Note A) XCLKOUT (see Note A) t w(TDIR) TDIRx SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 6-13. PWM Switching Characteristics (1) (2) PARAMETER TEST CONDITIONS MIN MAX UNIT t w(PWM) (3) (4) Pulse duration, PWMx output high/low 25 ns ...

Page 106 - Table 6-17. Interrupt Switching Characteristics

XCLKOUT t d(XCOH-EVASOCL) EVASOC t w(EVASOCL) XCLKOUT t d(XCOH-EVBSOCL) EVBSOC t w(EVBSOCL) SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Table 6-15. External ADC Start-of-Conversion – EVA – Switching Characteristics (1) (2) PARAMETER MIN MAX UNIT t d(XCOH-EVASOCL) Delay time, X...

Page 107 - Table 6-18. Interrupt Timing Requirements

PWM (see Note C) TxCTRIP, CxTRIP, PDPINTx (see Note B) XCLKOUT (see Note A) t w(PDP) , t w(CxTRIP) , t w(TxCTRIP) t d(PDP-PWM)HZ , t d(TRIP-PWM)HZ XNMI, XINT1, XINT2 t w(INT) Interrupt Vector t d(INT) A0−A15 SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 6-18. Interrupt Tim...

Page 108 - Figure 6-22. GPIO Input Qualifier – Example Diagram for QUALPRD = 1

t d(XCOH-GPO) GPIO XCLKOUT t r(GPO) t f(GPO) GPIO Signal 1 Sampling Window QUALPRD Output From Qualifier 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 SYSCLKOUT QUALPRD = 1 (2 x SYSCLKOUT cycles) x 5 NOTES: A. This glitch is ignored by the input qualifier. The QUALPRD bit field specifies the qualificati...

Page 109 - SPI Master Mode Timing

t c(SPC) + SPI clock cycle time + LSPCLK 4 or LSPCLK (SPIBRR ) 1) + t c(LCO) + LSPCLK cycle time GPIOxn XCLKOUT t w(GPI) (2) SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Figure 6-23. General-Purpose Input Timing NOTE The pulse width requirement for general-purpose input is appl...

Page 113 - SPI Slave Mode Timing

t c(SPC) + SPI clock cycle time + LSPCLK 4 or LSPCLK (SPIBRR ) 1) + t c(LCO) + LSPCLK cycle time 20 15 SPISIMO SPISOMI SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) SPISIMO Data Must Be Valid SPISOMI Data Is Valid 19 16 14 13 12 SPISTE (see Note A) (2) SM320F2812-HT www.ti.com SGUS062A – J...

Page 117 - Table 6-26. XTIMING Register Configuration Restrictions

SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 6.21 External Interface (XINTF) Timing Each XINTF access consists of three parts: Lead, Active, and Trail. The user configures theLead/Active/Trail wait states in the XTIMING registers. There is one XTIMING register for each XINTFzon...

Page 118 - LR; Restriction does not include external hardware wait states

SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com NOTE Restriction does not include external hardware wait states These requirements result in the following XTIMING register configuration restrictions: Table 6-28. XTIMING Register Configuration Restrictions (1) (2) XRDLEAD XRDACTIVE...

Page 119 - or; Table 6-31. XTIMING Register Configuration Restrictions

SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 or Table 6-31. XTIMING Register Configuration Restrictions (1) (2) XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING ≥ 2 ≥ 1 0 ≥ 2 ≥ 1 0 0, 1 (1) Not production tested. (2) No hardware to detect illegal XTIMING configura...

Page 120 - The relationship between SYSCLKOUT and XTIMCLK is shown in; Figure 6-28. Relationship Between XTIMCLK and SYSCLKOUT

XTIMING0 XTIMING1 XTIMING2 XTIMING6 XTIMING7 XBANK LEAD/ACTIVE/TRAIL 1 † 0 XCLKOUT /2 XTIMCLK 1 † 0 /2 C28x CPU XINTCNF2 (CLKMODE) XINTCNF2 (XTIMCLK) † Default Value after reset SYSCLKOUT XINTCNF2 (CLKOFF) 1 0 0 SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com The relationship betw...

Page 121 - XINTF Signal Alignment to XCLKOUT

SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 6.22 XINTF Signal Alignment to XCLKOUT For each XINTF access, the number of lead, active, and trail cycles is based on the internal clockXTIMCLK. Strobes such as XRD, XWE, and zone chip-select (XZCS) change state in relationship to t...

Page 122 - External Interface Read Timing; Table 6-35. External Memory Interface Read Timing Requirements

Lead Active Trail DIN t d(XCOHL-XRDL) t d(XCOH-XA) t d(XCOH-XZCSL) t d(XCOHL-XRDH) t h(XD)XRD t d(XCOHL-XZCSH) XCLKOUT=XTIMCLK XCLKOUT= 1/2 XTIMCLK XZCS0AND1, XZCS2, XZCS6AND7 XA[0:18] XRD XWE XR/W XD[0:15] NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessar...

Page 123 - XTIMING register parameters used for this example:; External Interface Write Timing

Lead Active Trail t d(XCOH-XZCSL) t d(XCOH-XA) t d(XCOHL-XWEL) t d(XCOHL-XWEH) t d(XCOHL-XZCSH) t en(XD)XWEL t h(XD)XWEH t dis(XD)XRNW XCLKOUT=XTIMCLK XCLKOUT= 1/2 XTIMCLK XZCS0AND1, XZCS2, XZCS6AND7 XA[0:18] XRD XWE XR/W XD[0:15] NOTES: A. All XINTF accesses (lead period) begin on the rising edge o...

Page 126 - Figure 6-31. Example Read With Synchronous XREADY Access

Lead Active Trail DIN t d(XCOH-XZCSL) t d(XCOH-XA) t d(XCOHL-XRDL) t d(XCOHL-XZCSH) t d(XCOHL-XRDH) WS (Synch) XCLKOUT=XTIMCLK XCLKOUT= 1/2 XTIMCLK XZCS0AND1, XZCS2, XZCS6AND7 XA[0:18] XRD XWE XR/W XD[0:15] XREADY(Synch) NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT....

Page 127 - Figure 6-32. Example Read With Asynchronous XREADY Access

t su(XD)XRD Lead Active Trail DIN t d(XCOH-XZCSL) t d(XCOH-XA) t d(XCOHL-XRDL) t d(XCOHL-XZCSH) t d(XCOHL-XRDH) WS (Asynch) XCLKOUT=XTIMCLK XCLKOUT= 1/2 XTIMCLK XZCS0AND1, XZCS2, XZCS6AND7 XA[0:18] XRD XWE XR/W XD[0:15] XREADY(Asynch) NOTES: A. All XINTF accesses (lead period) begin on the rising ed...

Page 129 - Figure 6-33. Write With Synchronous XREADY Access

Lead 1 Active Trail XCLKOUT = XTIMCLK XCLKOUT = 1/2 XTIMCLK XA[0:18] XD[0:15] XREADY(Synch) t d(XCOHL-XWEL) t d(XCOHL-XWEH) t d(XCOHL-XZCSH) t d(XCOH-XA) WS (Synch) XZCS0AND1, XZCS2, XZCS6AND7 XRD XWE XR/W t d(XCOH-XZCSL) NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT...

Page 130 - Figure 6-34. Write With Asynchronous XREADY Access

Lead 1 Active Trail XCLKOUT = XTIMCLK XCLKOUT = 1/2 XTIMCLK XA[0:18] XD[0:15] t d(XCOHL-XWEH) t d(XCOHL-XZCSH) t d(XCOH-XA) WS (Asynch) XZCS0AND1, XZCS2, XZCS6AND7 XRD XWE XR/W t d(XCOH-XZCSL) NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device ...

Page 131 - XHOLD and XHOLDA

SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 6.27 XHOLD and XHOLDA f the HOLD mode bit is set while XHOLD and XHOLDA are both low (external bus accesses granted), theXHOLDA signal is forced high (at the end of the current cycle) and the external interface is taken out ofhigh-im...

Page 132 - Figure 6-35. External Interface Hold Waveform

XCLKOUT (/1 Mode) XHOLD XR/W, XZCS0AND1, XZCS2, XZCS6AND7 XD[15:0] Valid XHOLDA t d(HL-Hiz) t d(HH-HAH) High-Impedance XA[18:0] Valid Valid High-Impedance t d(HH-BV) t d(HL-HAL) See Note A See Note B SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com 6.28 XHOLD/XHOLDA Timing Table 6-...

Page 137 - Figure 6-37. ADC Analog Input Impedance Model

ac R s ADCIN0 C p 10 pF R on 1 k Ω 1.25 pF C h Switch Typical Values of the Input Circuit Components: Switch Resistance (R on ): 1 k Ω Sampling Capacitor (C h ): 1.25 pF Parasitic Capacitance (C p ): 10 pF Source Resistance (R s ): 50 Ω 28x DSP Source Signal ADC Power Up Delay ADC Ready for Conversi...

Page 139 - Table 6-50. Sequential Sampling Mode Timing; SAMPLE n

SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 6-50. Sequential Sampling Mode Timing (1) AT 25–MHz ADC SAMPLE n SAMPLE n + 1 CLOCK, REMARKS t c(ADCCLK) = 40 ns Delay time from event trigger to t d(SH) 2.5t c(ADCCLK) sampling (1 + Acqps) × Acqps value = 0-15 t SH Sample/Hold...

Page 141 - Table 6-51. Simultaneous Sampling Mode Timing; Definitions of Specifications and Terminology

(SINAD 1.76) N 6.02 - = SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 6-51. Simultaneous Sampling Mode Timing (1) (continued) AT 25-MHz ADC SAMPLE n SAMPLE n + 1 CLOCK, REMARKS t c(ADCCLK) = 40 ns Delay time for successive (3 + Acqps) × t d(schB0_n+1) results to appear in ...

Page 143 - Table 6-53. McBSP Switching Characteristics

SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 Table 6-53. McBSP Switching Characteristics (1) (2) (3) NO. PARAMETER MIN MAX UNIT M1 t c(CKRX) Cycle time, CLKR/X CLKR/X int 2P ns M2 t w(CKRXH) Pulse duration, CLKR/X high CLKR/X int D – 5 (4) D + 5 (4) ns M3 t w(CKRXL) Pulse durat...

Page 145 - McBSP as SPI Master or Slave Timing

Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) CLKX FSX DX M30 M31 DR M28 M24 M29 M25 LSB MSB M32 M33 SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 6.30.2 McBSP as SPI Master or Slave Timing Table 6-54. McBSP as SPI Master or Slave Timing Requirements (CLKSTP ...

Page 149 - Table 6-64. Minimum Required Wait-States at Different Frequencies

SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 6.31 Flash Timing 6.31.1 Recommended Operating Conditions (4) MIN NOM MAX UNIT N f Flash endurance for the array (Write/erase cycles) 0°C to 85°C 100 1000 cycles Maximum One-Time Programmable (OTP) endurance for the array (Write N OT...

Page 150 - RANDOM WAIT STATE

SM320F2812-HT SGUS062A – JUNE 2009 – REVISED APRIL 2010 www.ti.com Table 6-64. Minimum Required Wait-States at Different Frequencies (1) (continued) SYSCLKOUT (MHz) SYSCLKOUT (ns) PAGE WAIT-STATE (2) RANDOM WAIT STATE (2) (3) 4 250 0 1 150 Electrical Specifications Copyright © 2009–2010, Texas Instr...

Page 152 - PACKAGE OPTION ADDENDUM; PACKAGING INFORMATION

PACKAGE OPTION ADDENDUM www.ti.com 28-May-2010 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) SM320F2812HFGS150 ACTIVE CFP HFG 172 1 TBD AU N / A for Pkg Type Co...

Page 154 - IMPORTANT NOTICE; Products

IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers shouldobtain the l...