Page 2 - FIXED-POINT DIGITAL SIGNAL PROCESSOR; Data Manual
SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR Data Manual Literature Number: SPRS462B SEPTEMBER 2007 – Revised JANUARY 2008 PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of the TexasInstruments standard warranty. Production proces...
Page 3 - Features
Contents SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 1 Features .............................................................................................................................. 7 1.1 ZTZ/GTZ BGA Package (Bottom View) ................
Page 4 - C64x+ Peripheral Information and Electrical Specifications
SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 6.2 Recommended Operating Conditions .................................................................................. 101 6.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and ...
Page 8 - Description; System PLL and PLL Controller
www.ti.com 1.1 ZTZ/GTZ BGA Package (Bottom View) ZTZ/GTZ 697-PIN BALL GRID ARRAY (BGA) PACKAGE ( BOTTOM VIEW ) A 2 B 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 27 28 29 AG AH AJ NOTE: The ZTZ mechanical package designator ...
Page 10 - Functional Block Diagram; shows the functional block diagram of the C6455 device.
www.ti.com 1.3 Functional Block Diagram L2 Memory Controller (Memory Protect/ Bandwidth Mgmt) Serial Rapid I/O DDR2 Mem Ctlr System (B ) C64x+ DSP Core Data Path B B Register File B31−B16 B15−B0 Instruction Fetch Data Path A A Register File A31−A16 A15−A0 Device Configuration Logic .L1 .S1 .M1 xxxx ...
Page 11 - Device Overview; Device Characteristics; Table 2-1. Characteristics of the C6455 Processor; HARDWARE FEATURES
www.ti.com 2 Device Overview 2.1 Device Characteristics SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-1 , provides an overview of the C6455 DSP. The tables show significant features of the C6455 device, including the capacity of on-chip R...
Page 13 - Other new features include:; SPLOOP; - As noted above, there are new instructions such as 32 bit; Exception Handling; free-running time-stamp counter is implemented in the CPU which is
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Other new features include: • SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel....
Page 15 - Memory Map Summary; MEMORY BLOCK DESCRIPTION
www.ti.com 2.3 Memory Map Summary SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-2 shows the memory map address ranges of the C6455 device. The external memory configuration register address ranges in the C6455 device begin at the hex addr...
Page 17 - Boot Sequence; Boot Modes Supported; Reset Controller
www.ti.com 2.4 Boot Sequence 2.4.1 Boot Modes Supported SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The boot sequence is a process by which the DSP's internal memory is loaded with program and datasections and the DSP's internal registers are p...
Page 19 - nd-Level Bootloaders; The SRIO boot is a software boot mode.
www.ti.com 2.4.2 2nd-Level Bootloaders SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The SRIO boot is a software boot mode. Any of the boot modes can be used to download a 2nd-level bootloader. A 2nd-level bootloader allows forany level of custom...
Page 20 - Pin Assignments; Pin Map; through
www.ti.com 2.5 Pin Assignments 2.5.1 Pin Map AG AF AE AD AC AB AA Y W V U T R 13 12 11 10 9 8 7 6 5 4 3 2 1 13 12 11 10 9 8 7 6 5 4 3 2 1 CLKR1/ GP[0] HD15/ AD15 HD2/ AD2 URADDR0/ PGNT/ GP[12] HD22/ AD22 DV DD33 RSV15 UXADDR1/ PIDSEL RSV16 HDS1/ PSERR HINT/ PFRAME DV DD33 HHWIL/ PCLK V SS HD12/ AD12...
Page 24 - Signal Groups Description
www.ti.com 2.6 Signal Groups Description • TRST IEEE Standard 1149.1 (JTAG) Emulation Reserved Reset and Interrupts Control/Status TDI TDO TMS TCK NMI RESET RSV03RSV04 Clock/PLL1 and PLL Controller CLKIN1 EMU0EMU1 SYSCLK4/GP[1] (A) EMU14EMU15EMU16 EMU17 RSV02 EMU18 RSV07RSV09 RSV05 RSV43RSV44 RSV42 ...
Page 30 - Terminal Functions; The terminal functions table (
www.ti.com 2.7 Terminal Functions SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The terminal functions table ( Table 2-3 ) identifies the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pi...
Page 31 - SIGNAL
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS RESET AG14 I Device reset Nonmaskable interr...
Page 44 - RESERVED FOR TEST
www.ti.com SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. ETHERNET MAC (EMAC) [RGMII] If the Ethernet MAC (EMAC) and MDIO are enabled (AEA12 driven low [UTOP...
Page 50 - GROUND PINS
www.ti.com SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. R18 T11 T13 T15 T17 T19 U12 1.25-V core supply voltage (-1000 and -1200 devices) CV DD S 1.2-V core...
Page 55 - Development; Development Support; Code Composer StudioTM Integrated Development Environment (IDE):
www.ti.com 2.8 Development 2.8.1 Development Support 2.8.2 Device Support 2.8.2.1 Device and Development-Support Tool Nomenclature SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 In case the customer would like to develop their own features and sof...
Page 56 - Documentation Support; TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide.
www.ti.com SM = Qualified device SM = HiRel (non-38535) A = 40 C to 105 C (extended temperature) - º º S = 55 C to 105 C (extended temperature) - º º 2.8.2.2 Documentation Support SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 TI device nomenclatur...
Page 57 - TMS320C645x DSP DDR2 Memory Controller User's Guide.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 C6000 DSP platforms. SPRU970 TMS320C645x DSP DDR2 Memory Controller User's Guide. This document describes the DDR2 memory controller in the C645x digital-signal processors (DSPs). SPRU966 T...
Page 59 - Device Configuration at Device Reset; NOTE; CONFIGURATION
www.ti.com 3 Device Configuration 3.1 Device Configuration at Device Reset SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 On the C6455 device, certain device configurations like boot mode, pin multiplexing, and endianess, areselected at device res...
Page 61 - Peripheral Configuration at Device Reset
www.ti.com 3.2 Peripheral Configuration at Device Reset SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 3-1. C6455 Device Configuration Pins (AEA[19:0], ABA[1:0], and PCI_EN) (continued) CONFIGURATION IPD/ NO. FUNCTIONAL DESCRIPTION PIN IPU (...
Page 62 - describes the
www.ti.com SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 3-2. PCI_EN, PCI66, PCI_EEAI, and HPI_WIDTH Peripheral Selection (HPI and PCI) CONFIGURATION PIN SETTING (1) PERIPHERAL FUNCTION SELECTED PCI66 PCI_EEAI HPI_WIDTH PCI_EN PIN HPI DATA H...
Page 63 - Peripheral Selection After Device Reset; PERIPHERALS THAT CAN BE
www.ti.com 3.3 Peripheral Selection After Device Reset SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 On the C6455 device, peripherals can be in one of several states. These states are listed in Table 3-4 . Table 3-4. Peripheral States PERIPHERALS...
Page 64 - Figure 3-1. Peripheral Transitions Between States
www.ti.com Reset Static Powerdown Disabled Enable In Progress Enabled Unlock the PERCFG0 register by using the PERLOCK register. Write to the PERCFG0 register within 16 SYSCLK3 clock cycles to change the state of the peripherals. Poll the PERSTAT registers to verify state change. SM320C6455-EPFIXED-...
Page 65 - Device State Control Registers; and described in the next sections.; Table 3-5. Device State Control Registers; HEX ADDRESS RANGE
www.ti.com 3.4 Device State Control Registers SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The C6455 device has a set of registers that are used to control the status of its peripherals. Theseregisters are shown in Table 3-5 and described in the...
Page 66 - Peripheral Lock Register Description; Bit
www.ti.com 3.4.1 Peripheral Lock Register Description SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 When written with correct 32 bit key (0x0F0A0B00), the Peripheral Lock Register (PERLOCK) allows onewrite to the PERCFG0 register within 16 SYSCLK3...
Page 67 - Peripheral Configuration Register 0 Description
www.ti.com 3.4.2 Peripheral Configuration Register 0 Description SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The Peripheral Configuration Register (PERCFG0) is used to change the state of the peripherals. Onewrite is allowed to this register wi...
Page 69 - Peripheral Configuration Register 1 Description
www.ti.com 3.4.3 Peripheral Configuration Register 1 Description SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The Peripheral Configuration Register (PERCFG1) is used to enable the EMIFA and DDR2 MemoryController. EMIFA and the DDR2 Memory Contro...
Page 70 - Peripheral Status Registers Description
www.ti.com 3.4.4 Peripheral Status Registers Description SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The Peripheral Status Registers (PERSTAT0 and PERSTAT1) show the status of the C6455 peripherals. 31 30 29 27 26 24 Reserved HPISTAT McBSP1STAT ...
Page 73 - EMAC Configuration Register (EMACCFG) Description
www.ti.com 3.4.5 EMAC Configuration Register (EMACCFG) Description SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The EMAC Configuration Register (EMACCFG) is used to assert and deassert the reset of the ReducedMedia Independent Interface (RMII) l...
Page 74 - Emulator Buffer Powerdown Register (EMUBUFPD) Description
www.ti.com 3.4.6 Emulator Buffer Powerdown Register (EMUBUFPD) Description SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The Emulator Buffer Powerdown Register (EMUBUFPD) is used to control the state of the pin buffers ofemulator pins EMU[18:2]. T...
Page 75 - Device Status Register Description; and
www.ti.com 3.5 Device Status Register Description SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The device status register depicts the device configuration selected upon device reset. Once set, thesebits will remain set until a device reset. For ...
Page 78 - Device Configuration Pins
www.ti.com 3.7 Pullup/Pulldown Resistors 3.8 Configuration Examples SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Proper board design should ensure that input pins to the C6455 device always be at a valid logic level andnot floating. This may be a...
Page 81 - System Interconnect; Internal Buses, Bridges, and Switch Fabrics; Bridges perform a variety of functions:
www.ti.com 4 System Interconnect 4.1 Internal Buses, Bridges, and Switch Fabrics SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 On the C6455 device, the C64x+ Megamodule, the EDMA3 transfer controllers, and the systemperipherals are interconnected...
Page 82 - Data Switch Fabric Connections
www.ti.com 4.2 Data Switch Fabric Connections SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Figure 4-1 shows the connection between slaves and masters through the data switched central resource (SCR). Masters are shown on the right and slaves on t...
Page 83 - Figure 4-1. Switched Central Resource Block Diagram
www.ti.com Serial RapidIO (Descriptor) EMAC HPI M M M 128-bit (SYSCLK2) M3 M0 S S M M M M S TCP2 VCP2 S McBSPs S UTOPIA S DDR2 Memory Controller S EMIFA S PCI S MASTER SLAVE S M Bridge CFGSCR S Bridge PCI M EDMA3 Channel Controller EDMA3 Transfer Controllers Megamodule M1 M2 S3 S0 S1 S2 M Serial Rap...
Page 84 - Configuration Switch Fabric
www.ti.com 4.3 Configuration Switch Fabric SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 4-1. SCR Connection Matrix DDR2 MEMORY TCP2 VCP2 McBSPs UTOPIA2 CONFIGURATION SCR PCI EMIFA MEGAMODULE CONTROLLER TC0 Y Y N N N N Y Y Y TC1 N N Y Y Y Y ...
Page 86 - Bus Priorities; . The priority levels should be tuned to obtain; Table 4-2. C6455 Default Bus Master Priorities; DEFAULT
www.ti.com 4.4 Bus Priorities SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 On the C6455 device, bus priority is programmable for each master. The register bit fields and defaultpriority levels for C6455 bus masters are shown in Table 4-2 . The pr...
Page 87 - Memory Architecture; shows a block diagram of the C64x+ Megamodule.
www.ti.com 5 C64x+ Megamodule A register file Data path 1 Data path 2 B register file D2 S2 xx xx M2 L2 Instruction decode M1 xx xx L1 S1 D1 16/32−bit instruction dispatch Instruction fetch SPLOOP buffer 64 64 C64x+ CPU 256 32 L1D cache/SRAM Bandwidth management Memory protection L1 data memory cont...
Page 89 - Guide
www.ti.com 32K bytes 32K bytes 64K bytes 128K bytes 1840K bytes L2 memory 0080 0000h 009C 0000h 009E 0000h 009F 0000h009F 8000h00A0 0000h 7/8 SRAM 4-waycache 4-waycache SRAM 15/16 4-way 31/32 SRAM 4-way SRAM 63/64 All SRAM 000 001 010 011 111 Block baseaddress L2 mode bits cache SM320C6455-EP FIXED-...
Page 90 - Table 5-1. Available Memory Page Protection Schemes; AID0 Bit; Reference Guide
www.ti.com 5.2 Memory Protection 5.3 Bandwidth Management SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Memory protection allows an operating system to define who or what is authorized to access L1D, L1P,and L2 memory. To accomplish this, the L1D,...
Page 91 - Megamodule Resets; TMS320C64x+ Megamodule Reference Guide; Megamodule Reference Guide
www.ti.com 5.4 Power-Down Control 5.5 Megamodule Resets SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The C64x+ Megamodule supports the ability to power-down various parts of the C64x+ Megamodule. Thepower-down controller (PDC) of the C64x+ Megam...
Page 92 - Megamodule Revision; and described in
www.ti.com 5.6 Megamodule Revision SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The version and revision of the C64x+ Megamodule can be read from the Megamodule Revision IDRegister (MM_REVID) located at address 0181 2000h. The MM_REVID register i...
Page 93 - Table 5-4. Megamodule Interrupt Registers
www.ti.com 5.7 C64x+ Megamodule Register Description(s) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 5-4. Megamodule Interrupt Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0180 0000 EVTFLAG0 Event Flag Register 0 (Events [31:0]) 0180 ...
Page 94 - Table 5-5. Megamodule Powerdown Control Registers
www.ti.com SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 5-4. Megamodule Interrupt Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0180 0188 INTDMASK Dropped Interrupt Mask Register 0180 0188 - 0180 01BC - Reserved 0180 01C0 EV...
Page 95 - Table 5-8. Megamodule Cache Configuration Registers
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 5-8. Megamodule Cache Configuration Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0184 0000 L2CFG L2 Cache Configuration Register 0184 0004 - 0184 001F - Reserved 0184 0020 L1PCFG...
Page 100 - Table 5-10. CPU Megamodule Bandwidth Management Registers
www.ti.com SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 5-10. CPU Megamodule Bandwidth Management Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0182 0200 EMCCPUARBE EMC CPU Arbitration Control Register 0182 0204 EMCIDMAARBE EMC IDMA Arb...
Page 101 - Device Operating Conditions; MIN
www.ti.com 6 Device Operating Conditions 6.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless 6.2 Recommended Operating Conditions SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Otherwise Noted) (1) Supply voltage range: CV D...
Page 102 - Recommended Operating Conditions (continued)
www.ti.com SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Recommended Operating Conditions (continued) MIN NOM MAX UNIT V SS Supply ground 0 0 0 V 3.3 V pins (exceptPCI-capable and 2 V I2C pins) PCI-capable 0.5DV DD33 DV DD33 + 0.5 V pins (1) V IH ...
Page 103 - Operating Case Temperature (Unless Otherwise Noted)
www.ti.com 6.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Operating Case Temperature (Unless Otherwise Noted) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT 3.3-V pins (e...
Page 105 - Parameter Information; Tester Pin Electronics; Figure 7-1. Test Load Circuit for AC Timing Measurements; MIN for input clocks,; MAX and V; MIN for output clocks.; Figure 7-3. Rise and Fall Transition Time Voltage Reference Levels
www.ti.com 7 C64x+ Peripheral Information and Electrical Specifications 7.1 Parameter Information Transmission Line 4.0 pF 1.85 pF Z0 = 50 Ω (see Note) Tester Pin Electronics Data Sheet Timing Reference Point OutputUnderTest NOTE: This data sheet provides timing at the device pin. For output timing ...
Page 106 - Timing Parameters and Board Routing Analysis; The timing parameter values specified in this data sheet do; DESCRIPTION
www.ti.com 7.1.3 Timing Parameters and Board Routing Analysis 1 2 3 4 5 6 7 8 10 11 AECLKOUT (Output from DSP) AECLKOUT (Input to External Device) Control Signals (A) (Output from DSP) Control Signals (Input to External Device) Data Signals (B) (Output from External Device) Data Signals (B) (Input t...
Page 107 - Power-Supply Sequencing; Power-Supply Decoupling; must; UNIT
www.ti.com 7.2 Recommended Clock and Control Signal Transition Behavior 7.3 Power Supplies 7.3.1 Power-Supply Sequencing DV DD33 CV DD12 All other power supplies 1 2 7.3.2 Power-Supply Decoupling 7.3.3 Power-Down Operation SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 ...
Page 109 - Enhanced Direct Memory Access (EDMA3) Controller; lists the device resources that can be accessed by each of the
www.ti.com 7.4 Enhanced Direct Memory Access (EDMA3) Controller SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The primary purpose of the EDMA3 is to service user-programmed data transfers between twomemory-mapped slave endpoints on the device. Th...
Page 110 - Controller User's Guide; Table 7-3. C6455 EDMA3 Channel Synchronization Events; EDMA
www.ti.com 7.4.1 EDMA3 Device-Specific Information 7.4.2 EDMA3 Channel Synchronization Events SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The EDMA supports two addressing modes: constant addressing and increment addressing mode.Constant addressi...
Page 111 - Table 7-4. EDMA3 Channel Controller Registers
www.ti.com 7.4.3 EDMA3 Peripheral Register Description(s) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-3. C6455 EDMA3 Channel Synchronization Events (continued) EDMA BINARY EVENT NAME EVENT DESCRIPTION CHANNEL 18-19 - - None 20 001 0100 ...
Page 118 - Table 7-6. EDMA3 Transfer Controller 0 Registers
www.ti.com SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-5. EDMA3 Parameter RAM (1) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A0 4000 - 02A0 401F - Parameter Set 0 02A0 4020 - 02A0 403F - Parameter Set 1 02A0 4040 - 02A0 405F - Parameter S...
Page 119 - Table 7-7. EDMA3 Transfer Controller 1 Registers
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-6. EDMA3 Transfer Controller 0 Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A2 0284 DFSRCBREF Destination FIFO Set Destination Address B Reference Register 02A2 0...
Page 120 - Table 7-8. EDMA3 Transfer Controller 2 Registers
www.ti.com SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-7. EDMA3 Transfer Controller 1 Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A2 8240 SAOPT Source Active Options Register 02A2 8244 SASRC Source Active Source Addre...
Page 122 - Table 7-9. EDMA3 Transfer Controller 3 Registers
www.ti.com SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-8. EDMA3 Transfer Controller 2 Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A3 03C4 DFSRC3 Destination FIFO Source Address Register 3 02A3 03C8 DFCNT3 Destination ...
Page 124 - Interrupts; Interrupt Sources and Interrupt Controller; shows the mapping of system events. For more; EVENT NUMBER
www.ti.com 7.5 Interrupts 7.5.1 Interrupt Sources and Interrupt Controller SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The CPU interrupts on the C6455 device are configured through the C64x+ Megamodule InterruptController. The interrupt controll...
Page 127 - External Interrupts Electrical Data/Timing; Table 7-11. Timing Requirements for External Interrupts
www.ti.com 7.5.2 External Interrupts Electrical Data/Timing 2 1 NMI SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-11. Timing Requirements for External Interrupts (1) (see Figure 7-6 ) -720-850 A-1000/-1000 NO. UNIT -1200 MIN MAX 1 t w(NMI...
Page 128 - Reset Electrical Data/Timing; TYPE; The following sequence must be followed during a Power-on Reset:
www.ti.com 7.6 Reset Controller 7.6.1 Power-on Reset (POR Pin) SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The reset controller detects the different type of resets supported on the C6455 device and manages thedistribution of those resets throug...
Page 129 - all the system clocks are invalid at this point.; The following sequence must be followed during a Warm Reset:
www.ti.com 7.6.2 Warm Reset (RESET Pin) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 all the system clocks are invalid at this point. – The RESETSTAT pin stays asserted (low), indicating the device is in reset. 3. The POR pin may now be deassert...
Page 131 - Reset Priority; Maximum Reset
www.ti.com 7.6.6 Reset Priority SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 If any of the above reset sources occur simultaneously, the PLLCTRL only processes the highest priorityreset request. The rest request priorities are as follows (high t...
Page 132 - Reset Controller Register
www.ti.com 7.6.7 Reset Controller Register 7.6.7.1 Reset Type Status Register Description SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The reset type status (RSTYPE) register (029A 00E4) is the only register for the reset controller. Thisregister...
Page 133 - Table 7-14. Timing Requirements for Reset; For
www.ti.com 7.6.8 Reset Electrical Data/Timing SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-14. Timing Requirements for Reset (1) (2) (3) (see Figure 7-8 and Figure 7-9 ) -720-850 A-1000/-1000 NO. UNIT -1200 MIN MAX 5 t w(POR) Pulse durat...
Page 135 - Figure 7-9. Warm Reset and Max Reset Timing
www.ti.com CLKIN1 CLKIN2 POR RESET (A)(B) RESETSTAT Boot and Device Configuration Pins (C) 9 7 6 8 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 A. RESET should only be used after device has been powered up. For more details on the use of the RES...
Page 136 - PLL1 and PLL1 Controller; As shown in; DSP
www.ti.com 7.7 PLL1 and PLL1 Controller SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The primary PLL controller generates the input clock to the C64x+ megamodule (including the CPU) aswell as most of the system peripherals such as the multichanne...
Page 137 - PLL1 Controller Device-Specific Information
www.ti.com 1 0 0 1 DIVIDER D4 CLKIN1 (B) PLLEN (PLLCTL.[0]) SYSCLK2 SYSCLK3 AECLKIN (External EMIF Clock Input) EMIFA DIVIDER PREDIV DIVIDER D2 (A) DIVIDER D3 (A) AECLKOUT PLLV1 C2 C1 EMI Filter +1.8 V 560 pF 0.1 m F SYSCLK5(Emulation and Trace) SYSREFCLK(C64x+ MegaModule) AECLKINSEL(AEA[15] pin) DI...
Page 138 - There; CLOCK SIGNAL
www.ti.com 7.7.1.2 PLL1 Controller Operating Modes 7.7.1.3 PLL1 Stabilization, Lock, and Reset Times SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 • SYSCLK4 is used as the internal clock for the EMIFA. It is also used to clock other logic within t...
Page 139 - PLL1 Controller Memory Map; The memory map of the PLL1 controller is shown in
www.ti.com 7.7.2 PLL1 Controller Memory Map SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 1with PLLEN = 0) to when to when the PLL controller can be ...
Page 140 - PLL1 Controller Register Descriptions
www.ti.com 7.7.3 PLL1 Controller Register Descriptions 7.7.3.1 PLL1 Control Register SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 This section provides a description of the PLL1 controller registers. For details on the operation of the PLLcontrol...
Page 141 - The PLL multiplier control register (PLLM) is shown in
www.ti.com 7.7.3.2 PLL Multiplier Control Register SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The PLL multiplier control register (PLLM) is shown in Figure 7-12 and described in Table 7-20 . The PLLM register defines the input reference clock ...
Page 143 - The PLL controller divider 4 register (PLLDIV4) is shown in
www.ti.com 7.7.3.4 PLL Controller Divider 4 Register SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The PLL controller divider 4 register (PLLDIV4) is shown in Figure 7-14 and described in Table 7-22 . Besides being used as the EMIFA internal cloc...
Page 149 - shown in
www.ti.com 7.7.3.10 SYSCLK Status Register SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The SYSCLK status register (SYSTAT) shows the status of the system clocks (SYSCLK n ). SYSTAT is shown in Figure 7-20 and described in Table 7-28 . 31 16 Res...
Page 150 - PLL1 Controller Input and Output Clock Electrical Data/Timing; Table 7-29. Timing Requirements for CLKIN1 Devices
www.ti.com 7.7.4 PLL1 Controller Input and Output Clock Electrical Data/Timing CLKIN1 2 3 4 4 5 1 SYSCLK4 3 4 4 2 SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-29. Timing Requirements for CLKIN1 Devices (1) (2) (3) (see Figure 7-21 ) -720-...
Page 151 - PLL2 and PLL2 Controller
www.ti.com 7.8 PLL2 and PLL2 Controller PLLV2 PLL2 SYSCLK2 (From PLL1 Controller) SYSCLK1 DDR2 Memory Controller EMAC CLKIN2 (B)(C) C162 560 pF EMI Filter +1.8 V C161 0.1 F m PLL2 Controller TMS320C6455 DSP PLLM x20 /2 1 0 /x (A) 1 SYSREFCLK SYSCLK3 (From PLL1 Controller) PLLREF PLLOUT DIVIDER D1 SM...
Page 152 - PLL2 Controller Device-Specific Information
www.ti.com 7.8.1 PLL2 Controller Device-Specific Information 7.8.1.1 Internal Clocks and Maximum Operating Frequencies 7.8.1.2 PLL2 Controller Operating Modes SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 As shown in Figure 7-23 , the output of PL...
Page 153 - The memory map of the PLL2 controller is shown in
www.ti.com 7.8.2 PLL2 Controller Memory Map 7.8.3 PLL2 Controller Register Descriptions SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The memory map of the PLL2 controller is shown in Table 7-32 . Note that only registers documented here are acce...
Page 158 - Table 7-38. SYSCLK Status Register Field Descriptions
www.ti.com 7.8.3.6 SYSCLK Status Register SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The SYSCLK status register (SYSTAT) shows the status of the system clock (SYSCLK1). SYSTAT isshown in Figure 7-29 and described in Table 7-38 . 31 16 Reserved ...
Page 159 - PLL2 Controller Input Clock Electrical Data/Timing; Table 7-39. Timing Requirements for CLKIN2
www.ti.com 7.8.4 PLL2 Controller Input Clock Electrical Data/Timing CLKIN2 2 3 4 4 5 1 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-39. Timing Requirements for CLKIN2 (1) (2) (3) (see Figure 7-30 ) -720-850 A-1000/-1000 NO. UNIT -1200 MI...
Page 160 - DDR2 Memory Controller; DDR2 Memory Controller Device-Specific Information; Implementing DDR2 PCB Layout on
www.ti.com 7.9 DDR2 Memory Controller 7.9.1 DDR2 Memory Controller Device-Specific Information SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The 32 bit, 533-MHz (data rate) DDR2 Memory Controller bus of the C6455 is used to interface toJESD79D-2A ...
Page 161 - Table 7-40. DDR2 Memory Controller Registers; The
www.ti.com 7.9.2 DDR2 Memory Controller Peripheral Register Description(s) 7.9.3 DDR2 Memory Controller Electrical Data/Timing SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-40. DDR2 Memory Controller Registers HEX ADDRESS RANGE ACRONYM RE...
Page 164 - Table 7-42. Timing Requirements for AECLKIN for EMIFA
www.ti.com 7.10.3 EMIFA Electrical Data/Timing AECLKIN 2 3 4 4 5 1 SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-42. Timing Requirements for AECLKIN for EMIFA (1) (2) (see Figure 7-31 ) -720-850 A-1000/-1000 NO. UNIT -1200 MIN MAX 1 t c(EK...
Page 165 - Asynchronous Memory Timing; EMIFA Module; Figure 7-32. AECLKOUT Timing for the EMIFA Module
www.ti.com 5 6 2 AECLKIN AECLKOUT1 4 4 1 3 7.10.3.1 Asynchronous Memory Timing SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-43. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT for the EMIFA Module (1) (2) (3)...
Page 166 - PARAMETER; Figure 7-33. Asynchronous Memory Read Timing for EMIFA
www.ti.com AECLKOUT ACEx ABE[7:0] AEA[19:0]/ ABA[1:0] AED[63:0] AAOE/ASOE (A) AR/W AAWE/ASWE (A) AARDY (B) Byte Enables Address Read Data Hold = 1 2 Strobe = 4 Setup = 1 2 2 4 10 10 1 1 1 3 A AAOE/ASOE and AAWE/ASWE operate as AAOE (identified under select signals) and AAWE, respectively, during asy...
Page 167 - Figure 7-34. Asynchronous Memory Write Timing for EMIFA
www.ti.com AECLKOUT ACEx ABE[7:0] AEA[19:0]/ ABA[1:0] AED[63:0] AAOE/ASOE (A) AR/W AAWE/ASWE (A) AARDY (B) Byte Enables Address Write Data Hold = 1 12 Strobe = 4 Setup = 1 12 12 12 12 13 13 11 11 11 11 11 A AAOE/ASOE and AAWE/ASWE operate as AAOE (identified under select signals) and AAWE, respectiv...
Page 171 - Cycles for EMIFA Module
www.ti.com 7.10.4 HOLD/HOLDA Timing HOLD HOLDA EMIF Bus (A) DSP Owns Bus External Requestor Owns Bus DSP Owns Bus DSP DSP 1 3 2 5 4 AECLKOUT SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-48. Timing Requirements for the HOLD/HOLDA Cycles f...
Page 172 - for EMIFA Module (see
www.ti.com 7.10.5 BUSREQ Timing AECLKOUTx 1 ABUSREQ 1 SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-50. Switching Characteristics Over Recommended Operating Conditions for the BUSREQ Cycles for EMIFA Module (see Figure 7-40 ) -720-850 A-10...
Page 176 - Table 7-52. Timing Requirements for I2C Timings
www.ti.com 7.11.3 I2C Electrical Data/Timing 7.11.3.1 Inter-Integrated Circuits (I2C) Timing SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-52. Timing Requirements for I2C Timings (1) (see Figure 7-42 ) -720-850 A-1000/-1000 NO. UNIT -1200 ...
Page 177 - Table 7-53. Switching Characteristics for I2C Timings
www.ti.com 10 8 4 3 7 12 5 6 14 2 3 13 Stop Start Repeated Start Stop SDA SCL 1 11 9 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Figure 7-42. I2C Receive Timings Table 7-53. Switching Characteristics for I2C Timings (1) (see Figure 7-43 ) -720-...
Page 193 - Multichannel Buffered Serial Port (McBSP) Timing; Table 7-59. Timing Requirements for McBSP
www.ti.com 7.13.2 McBSP Electrical Data/Timing 7.13.2.1 Multichannel Buffered Serial Port (McBSP) Timing SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-59. Timing Requirements for McBSP (1) (see Figure 7-52 ) -720-850 A-1000/-1000 NO. UNIT...
Page 201 - Interface Modes
www.ti.com 7.14.1 EMAC Device-Specific Information SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Interface Modes The EMAC module on the C6455 supports four interface modes: Media Independent Interface (MII),Reduced Media Independent Interface (RM...
Page 202 - Using the RMII Mode of the EMAC
www.ti.com SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-70. EMAC/MDIO Multiplexed Pins (MII, RMII, and GMII Modes) BALL NUMBER DEVICE PIN NAME MII RMII GMII (MAC_SEL = (MAC_SEL = (MAC_SEL = 00b) 01b) 10b) J2 URDATA0/MRXD0/RMRXD0 MRXD0 RMR...
Page 203 - Interface Mode Clocking
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Interface Mode Clocking The on-chip PLL2 and PLL2 Controller generate the clocks to the EMAC module in RGMII or GMII mode.When the EMAC is enabled with these modes, the input clock to the P...
Page 207 - Table 7-73. EMAC Control Module Registers
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-72. EMAC Statistics Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME Receive Octet Frames Register 02C8 0230 RXOCTETS (Total number of received bytes in good frames) Go...
Page 208 - EMAC MII and GMII Electrical Data/Timing
www.ti.com 7.14.3 EMAC Electrical Data/Timing 7.14.3.1 EMAC MII and GMII Electrical Data/Timing MRCLK (Input) 2 3 1 4 4 MTCLK (Input) 2 3 1 4 4 SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-75. Timing Requirements for MRCLK - MII and GMII ...
Page 215 - Transmit
www.ti.com TXC (at DSP) (B) TXD[3:0] (A) TXCTL (A) 5 6 1st Half-byte TXERR TXEN 2nd Half-byte 1 2 Internal TXC TXC at DSP pins 4 4 2 3 1 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-88. Switching Characteristics Over Recommended Operatin...
Page 219 - Table 7-94. Timing Requirements for Timer Inputs
www.ti.com 7.15.3 Timers Electrical Data/Timing TINPLx TOUTLx 4 3 2 1 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-94. Timing Requirements for Timer Inputs (1) (see Figure 7-73 ) -720-850 A-1000/-1000 NO. UNIT -1200 MIN MAX 1 t w(TINPH) ...
Page 223 - Section 4; Table 7-98. Default Values for PCI Configuration
www.ti.com 7.18 Peripheral Component Interconnect (PCI) 7.18.1 PCI Device-Specific Information SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The C6455 DSP supports connections to a PCI backplane via the integrated PCI master/slave businterface. T...
Page 225 - Table 7-100. PCI Back End Configuration Registers; DSP ACCESS
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-100. PCI Back End Configuration Registers DSP ACCESS ACRONYM DSP ACCESS REGISTER NAME HEX ADDRESS RANGE 02C0 0000 - 02C0 000F - Reserved 02C0 0010 PCISTATSET PCI Status Set Register...
Page 227 - Table 7-102. PCI Hook Configuration Registers
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-102. PCI Hook Configuration Registers DSP ACCESS ACRONYM DSP ACCESS REGISTER NAME HEX ADDRESS RANGE 02C0 0394 PCIVENDEVPRG PCI Vendor ID and Device ID Program Register 02C0 0398 PCI...
Page 230 - For more detailed information on the UTOPIA peripheral, see the
www.ti.com 7.19 UTOPIA 7.19.1 UTOPIA Device-Specific Information 7.19.2 UTOPIA Peripheral Register Description(s) SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The Universal Test and Operations PHY Interface for ATM (UTOPIA) peripheral is a 50 MHz...
Page 231 - Table 7-106. Timing Requirements for UXCLK; Table 7-107. Timing Requirements for URCLK
www.ti.com 7.19.3 UTOPIA Electrical Data/Timing UXCLK 1 2 3 4 4 URCLK 1 2 3 4 4 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-106. Timing Requirements for UXCLK (1) (see Figure 7-74 ) -720-850 A-1000/-1000 NO. UNIT -1200 MIN MAX 1 t c(UXC...
Page 232 - Table 7-108. Timing Requirements for UTOPIA Slave Transmit (see
www.ti.com P47 P48 H1 N 0x1F N 0x1F N + 1 0x1F N N 10 8 4 3 2 1 UXCLK UXDATA[7:0] UXADDR[4:0] UXCLAV UXENB UXSOC 9 P46 P45 0 x1F A. The UTOPIA Slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the UXCLAV and UXSOC signals). 5 6 7 SM320C6455-EPFIXED-POINT...
Page 233 - Table 7-110. Timing Requirements for UTOPIA Slave Receive (see
www.ti.com P48 H1 H2 H3 N 0x1F N+1 0x1F N+2 0x1F N N+1 N+2 12 11 9 10 5 4 3 2 1 URCLK URDATA[7:0] URADDR[4:0] URCLAV URENB URSOC A. The UTOPIA Slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the URCLAV and URSOC signals). 8 6 7 SM320C6455-EP FIXED-POIN...
Page 247 - Table 7-114. Timing Requirements for GPIO Inputs
www.ti.com 7.21.3 GPIO Electrical Data/Timing GPIx GPOx 4 3 2 1 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-114. Timing Requirements for GPIO Inputs (1) (2) (see Figure 7-78 ) -720-850 A-1000/-1000 NO. UNIT -1200 MIN MAX 1 t w(GPIH) Pul...
Page 248 - Emulation Features and Capability; Hardware Program Breakpoints:
www.ti.com 7.22 Emulation Features and Capability 7.22.1 Advanced Event Triggering (AET) 7.22.2 Trace SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The C6455 device supports Advanced Event Triggering (AET). This capability can be used to debugcomp...
Page 250 - Revision History; have been incorporated.; SEE
www.ti.com Revision History SM320C6455-EPFIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 NOTE: Page numbers for previous revisions may differ from page numbers in the current version. This data sheet revision history highlights the technical changes made to the ...
Page 251 - Mechanical Data; Thermal Data; AIR FLOW
www.ti.com 8 Mechanical Data 8.1 Thermal Data 8.2 Packaging Information SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 8-1 shows the thermal resistance characteristics for the PBGA - ZTZ/GTZ mechanical package. Table 8-1. Thermal Resistance ...
Page 252 - PACKAGING INFORMATION; PACKAGE OPTION ADDENDUM
PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) SM320C6455BGTZEP ACTIVE FCBGA GTZ 697 44 TBD SNPB Level-4-220C-72 HR SM320C6455BGTZSEP ACTIVE FCBGA GTZ 697 44 TBD SNPB Level-4-220C-72 HR V62/07649-01XA AC...
Page 254 - IMPORTANT NOTICE; Products
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers shouldobtain the l...
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