Page 4 - NOTES FOR CMOS DEVICES
Preliminary User’s Manual S15543EJ1V0UM 4 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of stati...
Page 6 - PREFACE
6 Preliminary User’s Manual S15543EJ1V0UM PREFACE Readers This manual is intended for engineers who need to be familiar with the capability of the µ PD98502 in order to develop application systems based on it. Purpose The purpose of this manual is to help users understand the hardware capabilities (...
Page 7 - CONTENTS; CHAPTER 2 V
Preliminary User’s Manual S15543EJ1V0UM 7 CONTENTS CHAPTER 1 INTRODUCTION ............................................................................................................... 23 1.1 Features .....................................................................................................
Page 8 - Management
8 Preliminary User’s Manual S15543EJ1V0UM 2.1.6 Floating-point unit (FPU) ................................................................................................................64 2.1.7 CPU core memory management system (MMU) ....................................................................
Page 13 - SOF
Preliminary User’s Manual S15543EJ1V0UM 13 6.2.20 U_RP1IR (USB Rx Pool1 Information Register) .......................................................................... 327 6.2.21 U_RP1AR (USB Rx Pool1 Address Register) ............................................................................. 32...
Page 15 - APPENDIX B V
Preliminary User’s Manual S15543EJ1V0UM 15 8.3.4 UARTIER (UART Interrupt Enable Register) ............................................................................... 416 8.3.5 UARTDLL (UART Divisor Latch LSB Register) ........................................................................... 41...
Page 24 - System Configuration
CHAPTER 1 INTRODUCTION 24 Preliminary User’s Manual S15543EJ1V0UM 1.3 System Configuration The µ PD98502 can perform bridging and routing function between ADSL/ATM interface and USB/Ethernet interface and provides this function in a single chip. By selecting user interface, examples of system config...
Page 28 - S y s t e m C o n t r o l l e r; I B U S
CHAPTER 1 INTRODUCTION 28 Preliminary User’s Manual S15543EJ1V0UM 1.5.3 System controller System Controller is µ PD98502’s internal system controller. System Controller provides bridging function among the V R 4120A System Bus “SysAD”, NEC original high-speed on-chip bus “IBUS” and memory bus for SD...
Page 29 - ATM Cell Processor; IBUS
CHAPTER 1 INTRODUCTION Preliminary User’s Manual S15543EJ1V0UM 29 1.5.4 ATM cell processor By using NEC proprietary 32-bit controller, we will realize ATM Cell processor Unit. ATM Cell processing by firmware realizes more flexibility than before. Features of ATM Cell Processor are as follows; • Real...
Page 30 - E t h e r n e t C o n t r o l l e r
CHAPTER 1 INTRODUCTION 30 Preliminary User’s Manual S15543EJ1V0UM 1.5.5 Ethernet controller Ethernet Controller supports 2-channel 10 Mbps/100 Mbps Ethernet MAC (Media Access Control) function and MII (Media Independent Interface) function. Features of Ethernet Controller are as follows; • Supports ...
Page 31 - S IE; U S B; M C O N T
CHAPTER 1 INTRODUCTION Preliminary User’s Manual S15543EJ1V0UM 31 1.5.6 USB controller USB Controller provides Full Speed Function device function defined in Universal Serial Bus. Features of USB Controller are as follows; • Compliant to Universal Serial Bus Specification Rev. 1.1 • Supports Device ...
Page 33 - Y W V U T R P N M L K J H G F E D C B A; Index Mark
CHAPTER 1 INTRODUCTION Preliminary User’s Manual S15543EJ1V0UM 33 1.6 Pin Configuration (Bottom View) • 500-pin Tape BGA (Heat spread type) (40 × 40) µ PD98502N7-H6 2625242322212019181716151413121110 987654321 AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 30292827 AK AJ AH AG Index Mark
Page 54 - Reset Configuration
CHAPTER 1 INTRODUCTION 54 Preliminary User’s Manual S15543EJ1V0UM 1.10 Reset Configuration The falling edge of Clock Control Unit (CCU)’s reset line (RST_B) serves as the µ PD98502's internal reset. The System Controller generates the IBUS reset signal using RST_B for the global reset of the µ PD985...
Page 56 - Clock Control Unit
CHAPTER 1 INTRODUCTION 56 Preliminary User’s Manual S15543EJ1V0UM 1.12 Clock Control Unit This section describe µ PD98502’s internal clock is supplied by Clock Control Unit (CCU) with following figure. Figure 1-13. Block Diagram of Clock Control Unit U A R T 2 5 / 1 6 . 7 M H z P L L ( x 6 ) 1 / 2 1...
Page 57 - CHAPTER 2 V
Preliminary User’s Manual S15543EJ1V0UM 57 CHAPTER 2 V R 4120A Caution The µµµµ PD98502 doesn’t support MIPS16 instructions. This chapter describes an V R 4120A RISC Processor Core operation (MIPS instruction, Pipeline, etc.). Following in this Document, it is call for V R 4120A RISC Processor Core ...
Page 66 - MIPS III Instruction Set Summary
CHAPTER 2 V R 4120A 66 Preliminary User’s Manual S15543EJ1V0UM 2.1.11 Instruction pipeline The V R 4120A has a 6-stage instruction pipeline. Under normal circumstances, one instruction is issued each cycle. A detailed description of pipeline is provided in Section 2.3 Pipeline . 2.2 MIPS III Instruc...
Page 101 - Memory Management System
CHAPTER 2 V R 4120A Preliminary User’s Manual S15543EJ1V0UM 101 2.4 Memory Management System The V R 4120A Core provides a memory management unit (MMU) which uses a translation lookaside buffer (TLB) to translate virtual addresses into physical addresses. This chapter describes the virtual and physi...
Page 129 - Exception Processing
CHAPTER 2 V R 4120A Preliminary User’s Manual S15543EJ1V0UM 129 2.5 Exception Processing This chapter describes V R 4120A CPU exception processing, including an explanation of hardware that processes exceptions. 2.5.1 Exception processing operation The processor receives exceptions from a number of ...
Page 165 - Initialization Interface
CHAPTER 2 V R 4120A Preliminary User’s Manual S15543EJ1V0UM 165 2.6 Initialization Interface This section describes the reset sequence of the V R 4120A Core. For details about factors of reset or reset of the whole V R 4120A Core. 2.6.1 Cold reset In the V R 4120A Core, a cold reset sequence is exec...
Page 182 - CPU Core Interrupts
CHAPTER 2 V R 4120A 182 Preliminary User’s Manual S15543EJ1V0UM 2.8 CPU Core Interrupts Four types of interrupt are available on the CPU core. These are: one non-maskable interrupt, NMI five ordinary interrupts two software interrupts one timer interrupt For the interrupt request input to th...
Page 185 - CHAPTER 3 SYSTEM CONTROLLER
Preliminary User’s Manual S15543EJ1V0UM 185 CHAPTER 3 SYSTEM CONTROLLER 3.1 Overview Register map This block is an internal system controller for the µ PD98502. System controller provides bridging function among the CPU system bus “SysAD”, NEC original high-speed on-chip bus “IBUS” and memory bus fo...
Page 204 - Memory Interface
CHAPTER 3 SYSTEM CONTROLLER 204 Preliminary User’s Manual S15543EJ1V0UM 3.4 Memory Interface The V R 4120A accesses memory attached to the controller in the normal way, by addressing the memory space. 3.4.1 Overview • 66 MHz or 100 MHz memory bus • Supports up to 32 MB base memory range for SDRAM • ...
Page 208 - N o r m a l R O M R e a d C y c l e
CHAPTER 3 SYSTEM CONTROLLER 208 Preliminary User’s Manual S15543EJ1V0UM i n v a l i d S M A S D C L K N o r m a l R O M R e a d C y c l e S M D F A T ( = 4 ) S R M C S _ B S R M O E _ B S D W E _ B H V a l i d R e a d A d d r e s s T 0 T 1 T 2 T 3 T 4 T 0 H i - Z R e a d D a t a T 1 T 2 T 3 T 4 T 5 ...
Page 215 - F L A S H /R O M C o n fig u r a tio n
CHAPTER 3 SYSTEM CONTROLLER Preliminary User’s Manual S15543EJ1V0UM 215 3.4.1.4 Boot ROM signal connections S M D [ 3 1 : 0 ] S R M O E _ B S D W E _ B S R M C S _ B E x a m p le ( 8 M B P R O M ) S M A [ 2 0 : 0 ] S M D [ 3 1 : 0 ] µ P D 9 8 5 0 2 ( S y s t e m C o n t r o lle r) µ P D 9 8 5 0 2 ( ...
Page 218 - S D R A M C o n fig u r a tio n; M B
CHAPTER 3 SYSTEM CONTROLLER 218 Preliminary User’s Manual S15543EJ1V0UM R A S _ B S D C A S _ B S M A [1 3 :0 ] S M D [ 3 1 :0 ] 1 M x 1 6 S D R A M A [ 1 1 :0 ] D Q [ 1 5 :0 ] R A S _ B C S _ B µ P D 9 8 5 0 2 (S y s te m C o n t ro lle r) µ P D 9 8 5 0 2 (S y s te m C o n t ro lle r) µ P D 9 8 5 0...
Page 226 - Endian Mode Software Issues
CHAPTER 3 SYSTEM CONTROLLER 226 Preliminary User’s Manual S15543EJ1V0UM 3.7 Endian Mode Software Issues 3.7.1 Overview The native endian mode for MIPS processors, like Motorola and IBM 370 processors, is big endian. However, the native mode for Intel (which developed the PCI standard) and VAX proces...
Page 227 - L i t t l e - E n d i a n
CHAPTER 3 SYSTEM CONTROLLER Preliminary User’s Manual S15543EJ1V0UM 227 Figure 3-1. Bit and Byte Order of Endian Modes B Y T E 0 B Y T E 1 B Y T E 2 B Y T E 3 B Y T E 4 B Y T E 5 B Y T E 6 B Y T E 7 4 0 M S B L S B 3 1 0 M S B = M o s t S i g n i f i c a n t B y t e L S B = L e a s t S i g n i f i c...
Page 229 - CHAPTER 4 ATM CELL PROCESSOR
Preliminary User’s Manual S15543EJ1V0UM 229 CHAPTER 4 ATM CELL PROCESSOR 4.1 Overview This section describes functional specifications of ATM cell processor unit. 4.1.1 Function features Features of ATM Cell Processor with out Firmware (F/W) is as follows: • Data Transmission Capacity Aggregated tra...
Page 232 - U T O P IA
CHAPTER 4 ATM CELL PROCESSOR 232 Preliminary User’s Manual S15543EJ1V0UM 4.1.2.4 Other blocks Work-RAM is 12 K-byte memory. Tables and Pool Descriptors are located in this RAM. It is shared between MCU and UTOPIA Bus Controller block. It also can be accessed by V R 4120A RISC Processor, using Indire...
Page 236 - DRA
CHAPTER 4 ATM CELL PROCESSOR 236 Preliminary User’s Manual S15543EJ1V0UM 4.2 Memory Space Although the RISC Core in the ATM Cell Processor is a 32-bit MPU, its physical memory space is 24-bit width. Figure 4-6. Memory Space from V R 4120A and RISC Core W o rk R A M & R e g is t e r S p a c e I n...
Page 238 - Registers for ATM Cell Processing
CHAPTER 4 ATM CELL PROCESSOR 238 Preliminary User’s Manual S15543EJ1V0UM 4.4 Registers for ATM Cell Processing Registers in ATM Cell Processor block can be classified into 3 groups: SAR registers, DMA registers and FIFO Control registers. These registers can be accessed both V R 4120A and RISC Core ...
Page 263 - W o r k R A M ( 1 0 K b y t e s )
CHAPTER 4 ATM CELL PROCESSOR Preliminary User’s Manual S15543EJ1V0UM 263 Figure 4-24. Work RAM Usage P a c k e t I n f o S tr u c tu r e P o o l ( 4 W o r d s x 6 4 ) F r e e B lo c k P o o l /f o r V C T a b le / ( 1 6 W o r d s x 6 4 ) T e m p o r a r y D a ta 4 0 9 6 b yte s 1 0 2 4 b yte s 6 4 b...
Page 277 - CHAPTER 5 ETHERNET CONTROLLER
Preliminary User’s Manual S15543EJ1V0UM 277 CHAPTER 5 ETHERNET CONTROLLER 5.1 Overview This section describes Ethernet Controller block. This Ethernet Controller block comprises of a 10/100 Mbps Ethernet MAC (Media Access Control), data transmit/receive FIFOs, DMA and internal bus interface. The µ P...
Page 278 - Transceiver; Ethernet Controller Block
CHAPTER 5 ETHERNET CONTROLLER 278 Preliminary User’s Manual S15543EJ1V0UM Figure 5-1. Block Diagram of Ethernet Controller TPO+ TPO– TPI+ TPI– Transceiver M II I/O buf fer MACCore Ethernet Controller Block FIFOCont. Tx FIFO Rx FIFO DMA M a ster I/F Slav e I/F IBUS µµµµ PD98502
Page 306 - Set RCVDP
CHAPTER 5 ETHERNET CONTROLLER 306 Preliminary User’s Manual S15543EJ1V0UM When the receive frame is complete, Ethernet Controller sets the L-bit in the Receive Descriptor, writes the frame status bits into the Receive Descriptor, and sets the OWN-bit. Ethernet Controller generates a maskable interru...
Page 309 - CHAPTER 6 USB CONTROLLER
Preliminary User’s Manual S15543EJ1V0UM 309 CHAPTER 6 USB CONTROLLER 6.1 Overview The USB Controller handles the data communication through USB. The following lists the features of USB Controller. 6.1.1 Features • Conforms to Universal Serial Bus Specification Rev 1.1 • Supports operation conforming...
Page 310 - S I E
CHAPTER 6 USB CONTROLLER 310 Preliminary User’s Manual S15543EJ1V0UM 6.1.2 Internal block diagram USB Controller internal block diagram is as shown below. Figure 6-1. USB Controller Internal Configuration S I E E P C IB U S D + D - U S B B U S I / F R x F IF O M a ste r I /F S la v e I /F I/O B u f ...
Page 330 - USB Attachment Sequence
CHAPTER 6 USB CONTROLLER 330 Preliminary User’s Manual S15543EJ1V0UM 6.3 USB Attachment Sequence This section describes the sequence that is followed when the µ PD98502 is attached to a USB hub. Figure 6-2. USB Attachment Sequence V R 4 1 2 0 A U S B C o n t r o lle r C o n n e c t to a H U B H o s ...
Page 334 - Data Transmit Function; D a ta S e g m e n t; 4 B y te s
CHAPTER 6 USB CONTROLLER 334 Preliminary User’s Manual S15543EJ1V0UM 6.5 Data Transmit Function This section explains USB Controller's data transmit function. 6.5.1 Overview of transmit processing USB Controller divides the data segments in system memory, into USB packets, then transmits them to the...
Page 335 - T x P a c k e t; B u f f e r
CHAPTER 6 USB CONTROLLER Preliminary User’s Manual S15543EJ1V0UM 335 Figure 6-5. Tx Buffer Configuration B u f f e r d e s c r i p t o r B u f f e r d e s c r i p t o r B u f f e r d e s c r i p t o r D a t a B u f f e r D a t a B u f f e r B u f f e r d e s c . ( L = 1 ) D a t a B u f f e r D a t a...
Page 344 - Data Receive Function
CHAPTER 6 USB CONTROLLER 344 Preliminary User’s Manual S15543EJ1V0UM 6.6 Data Receive Function This section explains USB Controller's data receive function. 6.6.1 Overview of receive processing USB Controller receives USB packets from the USB, stores them into system memory, and then assembles a sin...
Page 345 - B u ffe r D ire c to r y
CHAPTER 6 USB CONTROLLER Preliminary User’s Manual S15543EJ1V0UM 345 6.6.2 Rx Buffer configuration Data received from the USB is stored into a receive pool in system memory. USB Controller uses three receive pools. The configuration of the receive pools is shown below. Figure 6-13. Receive Buffer Co...
Page 361 - B u f f e r D ir e c to r y
CHAPTER 6 USB CONTROLLER Preliminary User’s Manual S15543EJ1V0UM 361 Figure 6-25. Example of Buffers Including Corrupted Data B u f f e r d e s c r ip to r B u f f e r d e s c r ip to r B u f f e r d e s c r ip to r V a lid D a t a V a lid D a t a V a lid D a t a V a lid D a t a L in k p o in te r B...
Page 364 - Power Management; H o s t P C
CHAPTER 6 USB CONTROLLER 364 Preliminary User’s Manual S15543EJ1V0UM 6.7 Power Management USB Controller has a built in feature that allows it to use interrupts to inform the V R 4120A of its having received Suspend or Resume signaling from a Host PC. When the V R 4120A receives a Suspend or a Resum...
Page 367 - Receiving SOF Packet
CHAPTER 6 USB CONTROLLER Preliminary User’s Manual S15543EJ1V0UM 367 6.8 Receiving SOF Packet USB Controller can receive SOF Packets, and check if Frame Number is incremented correctly. In addition, USB Controller can detect the timing skew of SOF Packet. 6.8.1 Receiving SOF Packet and updating the ...
Page 369 - Example of Connection
CHAPTER 6 USB CONTROLLER Preliminary User’s Manual S15543EJ1V0UM 369 6.10 Example of Connection USB Controller is connected to the µ PD98502 internal USB I/O buffer as shown in the following Figure 6-32 . Figure 6-32. Example of Connection O S E C o n n e c t t o H U B + 3 . 3 V A µ P D 9 8 5 0 2 D ...
Page 370 - CHAPTER 7 PCI CONTROLLER
370 Preliminary User’s Manual S15543EJ1V0UM CHAPTER 7 PCI CONTROLLER 7.1 Overview The PCI Controller supports both NIC mode and Host mode. With the NIC mode, the PCI Controller does not issue configuration cycle and the arbitration function is not enabled. With the Host mode, the PCI Controller can ...
Page 371 - Bus Bridge Functions
CHAPTER 7 PCI CONTROLLER Preliminary User’s Manual S15543EJ1V0UM 371 7.2 Bus Bridge Functions 7.2.1 Internal bus to PCI transaction 7.2.1.1 Window size The PCI Controller can have a 2-MB length access window in internal memory space. The V R 4120A can access external PCI devices through the access w...
Page 383 - PCI Power Management Interface
CHAPTER 7 PCI CONTROLLER Preliminary User’s Manual S15543EJ1V0UM 383 7.3 PCI Power Management Interface The PCI Controller has the mechanism for power management compliant to PCI Power Management Interface (PPMI) Rev.1.1 as a PCI-device. The PCI Controller does not control the power state of the chi...
Page 384 - P C I
CHAPTER 7 PCI CONTROLLER 384 Preliminary User’s Manual S15543EJ1V0UM 7.3.4 Power state transition 7.3.4.1 Transition by issue from PCI-Host An example of the transition sequence is as follows: 1. When PCI-Host wants to change the power state of the chip, it writes the state code to Power State field...
Page 424 - CHAPTER 9 TIMER
424 Preliminary User’s Manual S15543EJ1V0UM CHAPTER 9 TIMER 9.1 Overview There are two Timers. The timers are clocked at the system clock rate. All two timers are read/writeable by the CPU. Timers can be read by the CPU while they are counting. They can be automatically reloaded with the “Timer Set ...
Page 427 - CHAPTER 10 MICRO WIRE
Preliminary User’s Manual S15543EJ1V0UM 427 CHAPTER 10 MICRO WIRE 10.1 Overview This EEPROM interface is compatible with the Micro Wire serial interface. Connection to the “NM93C46” serial EEPROM, manufactured by National Semiconductor, is recommended. Serial EEPROM memory area is accessed in-direct...
Page 433 - A.2 Load and Store Instructions
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 433 (1) Instruction notation examples The following examples illustrate the application of some of the instruction notation conventions: Example 1: GPR [rt] ← immediate || 0 16 Sixteen zero bits are concatenated with...
Page 434 - A.3 Jump and Branch Instructions
APPENDIX A MIPS III INSTRUCTION SET DETAILS 434 Preliminary User’s Manual S15543EJ1V0UM As shown in Table A-3, the Access Type field indicates the size of the data item to be loaded or stored. Regardless of access type or byte-numbering order (endian), the address specifies the byte that has the sma...
Page 435 - A.5 CPU Instruction
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 435 A.4 System Control Coprocessor (CP0) Instructions There are some special limitations imposed on operations involving CP0 that is incorporated within the CPU. Although load and store instructions to transfer data ...
Page 436 - Add; ADD
APPENDIX A MIPS III INSTRUCTION SET DETAILS 436 Preliminary User’s Manual S15543EJ1V0UM ADD Add ADD rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 ADD 1 0 0 0 0 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 Format: ADD rd, rs, rt Description: The contents of general register rs and the contents of genera...
Page 437 - Add Immediate; ADDI
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 437 ADDI Add Immediate ADDI rs ADDI 0 0 1 0 0 0 rt immediate 31 26 25 21 20 16 15 0 6 5 5 16 Format: ADDI rt, rs, immediate Description: The 16-bit immediate is sign-extended and added to the contents of general regi...
Page 438 - Add Immediate Unsigned; ADDIU
APPENDIX A MIPS III INSTRUCTION SET DETAILS 438 Preliminary User’s Manual S15543EJ1V0UM ADDIU Add Immediate Unsigned ADDIU rs ADDIU 0 0 1 0 0 1 rt immediate 31 26 25 21 20 16 15 0 6 5 5 16 Format: ADDIU rt, rs, immediate Description: The 16-bit immediate is sign-extended and added to the contents of...
Page 439 - Add Unsigned; ADDU
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 439 ADDU Add Unsigned ADDU rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 ADDU 1 0 0 0 0 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 Format: ADDU rd, rs, rt Description: The contents of general register rs and the conte...
Page 440 - And; AND
APPENDIX A MIPS III INSTRUCTION SET DETAILS 440 Preliminary User’s Manual S15543EJ1V0UM AND And AND rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 AND 1 0 0 1 0 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 Format: AND rd, rs, rt Description: The contents of general register rs are combined with the cont...
Page 441 - And Immediate; ANDI
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 441 ANDI And Immediate ANDI rs ANDI 0 0 1 1 0 0 rt immediate 31 26 25 21 20 16 15 0 6 5 5 16 Format: ANDI rt, rs, immediate Description: The 16-bit immediate is zero-extended and combined with the contents of general...
Page 442 - Branch On Coprocessor 0 False
APPENDIX A MIPS III INSTRUCTION SET DETAILS 442 Preliminary User’s Manual S15543EJ1V0UM BC0F Branch On Coprocessor 0 False BC0F BC 0 1 0 0 0 COPz 0 1 0 0 X X Note BCF 0 0 0 0 0 offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: BC0F offset Description: A branch target address is computed from the sum of...
Page 445 - Branch On Coprocessor 0 True
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 445 BC0T Branch On Coprocessor 0 True BC0T BC 0 1 0 0 0 COPz 0 1 0 0 X X Note BCT 0 0 0 0 1 offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: BC0T offset Description: A branch target address is computed from the sum of ...
Page 448 - Branch On Equal; BEQ
APPENDIX A MIPS III INSTRUCTION SET DETAILS 448 Preliminary User’s Manual S15543EJ1V0UM BEQ Branch On Equal BEQ rs BEQ 0 0 0 1 0 0 rt offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: BEQ rs, rt, offset Description: A branch target address is computed from the sum of the address of the instruction in t...
Page 449 - Branch On Equal Likely; BEQL
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 449 BEQL Branch On Equal Likely BEQL rs BEQL 0 1 0 1 0 0 rt offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: BEQL rs, rt, offset Description: A branch target address is computed from the sum of the address of the instr...
Page 450 - Branch On Greater Than Or Equal To Zero; BGEZ
APPENDIX A MIPS III INSTRUCTION SET DETAILS 450 Preliminary User’s Manual S15543EJ1V0UM BGEZ Branch On Greater Than Or Equal To Zero BGEZ rs REGIMM 0 0 0 0 0 1 BGEZ 0 0 0 0 1 offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: BGEZ rs, offset Description: A branch target address is computed from the sum ...
Page 451 - Branch On Greater Than Or Equal To Zero And Link; BGEZAL
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 451 BGEZAL Branch On Greater Than Or Equal To Zero And Link BGEZAL rs REGIMM 0 0 0 0 0 1 BGEZAL 1 0 0 0 1 offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: BGEZAL rs, offset Description: A branch target address is compu...
Page 452 - Branch On Greater Than Or Equal To Zero And Link Likely; BGEZALL
APPENDIX A MIPS III INSTRUCTION SET DETAILS 452 Preliminary User’s Manual S15543EJ1V0UM BGEZALL Branch On Greater Than Or Equal To Zero And Link Likely BGEZALL rs REGIMM 0 0 0 0 0 1 BGEZALL 1 0 0 1 1 offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: BGEZALL rs, offset Description: A branch target addre...
Page 453 - Branch On Greater Than Or Equal To Zero Likely; BGEZL
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 453 BGEZL Branch On Greater Than Or Equal To Zero Likely BGEZL rs REGIMM 0 0 0 0 0 1 BGEZL 0 0 0 1 1 offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: BGEZL rs, offset Description: A branch target address is computed fr...
Page 454 - Branch On Greater Than Zero; BGTZ
APPENDIX A MIPS III INSTRUCTION SET DETAILS 454 Preliminary User’s Manual S15543EJ1V0UM BGTZ Branch On Greater Than Zero BGTZ rs BGTZ 0 0 0 1 1 1 0 0 0 0 0 0 offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: BGTZ rs, offset Description: A branch target address is computed from the sum of the address of...
Page 455 - Branch On Greater Than Zero Likely; BGTZL
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 455 BGTZL Branch On Greater Than Zero Likely BGTZL rs BGTZL 0 1 0 1 1 1 0 0 0 0 0 0 offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: BGTZL rs, offset Description: A branch target address is computed from the sum of the...
Page 456 - Branch On Less Than Or Equal To Zero; BLEZ
APPENDIX A MIPS III INSTRUCTION SET DETAILS 456 Preliminary User’s Manual S15543EJ1V0UM BLEZ Branch On Less Than Or Equal To Zero BLEZ rs BLEZ 0 0 0 1 1 0 0 0 0 0 0 0 offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: BLEZ rs, offset Description: A branch target address is computed from the sum of the a...
Page 457 - Branch On Less Than Or Equal To Zero Likely; BLEZL
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 457 BLEZL Branch On Less Than Or Equal To Zero Likely BLEZL rs BLEZL 0 1 0 1 1 0 0 0 0 0 0 0 offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: BLEZL rs, offset Description: A branch target address is computed from the s...
Page 458 - Branch On Less Than Zero; BLTZ
APPENDIX A MIPS III INSTRUCTION SET DETAILS 458 Preliminary User’s Manual S15543EJ1V0UM BLTZ Branch On Less Than Zero BLTZ rs REGIMM 0 0 0 0 0 1 BLTZ 0 0 0 0 0 offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: BLTZ rs, offset Description: A branch target address is computed from the sum of the address ...
Page 459 - Branch On Less Than Zero And Link; BLTZAL
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 459 BLTZAL Branch On Less Than Zero And Link BLTZAL rs REGIMM 0 0 0 0 0 1 BLTZAL 1 0 0 0 0 offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: BLTZAL rs, offset Description: A branch target address is computed from the su...
Page 460 - Branch On Less Than Zero And Link Likely; BLTZALL
APPENDIX A MIPS III INSTRUCTION SET DETAILS 460 Preliminary User’s Manual S15543EJ1V0UM BLTZALL Branch On Less Than Zero And Link Likely BLTZALL rs REGIMM 0 0 0 0 0 1 BLTZALL 1 0 0 1 0 offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: BLTZALL rs, offset Description: A branch target address is computed ...
Page 461 - Branch On Less Than Zero Likely; BLTZL
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 461 BLTZL Branch On Less Than Zero Likely BLTZL rs REGIMM 0 0 0 0 0 1 BLTZL 0 0 0 1 0 offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: BLTZ rs, offset Description: A branch target address is computed from the sum of th...
Page 462 - Branch On Not Equal; BNE
APPENDIX A MIPS III INSTRUCTION SET DETAILS 462 Preliminary User’s Manual S15543EJ1V0UM BNE Branch On Not Equal BNE rs BNE 0 0 0 1 0 1 rt offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: BNE rs, rt, offset Description: A branch target address is computed from the sum of the address of the instruction ...
Page 463 - Branch On Not Equal Likely; BNEL
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 463 BNEL Branch On Not Equal Likely BNEL rs BNEL 0 1 0 1 0 1 rt offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: BNEL rs, rt, offset Description: A branch target address is computed from the sum of the address of the i...
Page 464 - Breakpoint; BREAK
APPENDIX A MIPS III INSTRUCTION SET DETAILS 464 Preliminary User’s Manual S15543EJ1V0UM BREAK Breakpoint BREAK code SPECIAL 0 0 0 0 0 0 BREAK 0 0 1 1 0 1 31 26 25 6 5 0 6 20 6 Format: BREAK Description: A breakpoint trap occurs, immediately and unconditionally transferring control to the exception h...
Page 465 - CACHE
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 465 CACHE Cache (1/4) CACHE base CACHE 1 0 1 1 1 1 op offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: CACHE op, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general regist...
Page 469 - Doubleword Add; DADD
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 469 DADD Doubleword Add DADD rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 DADD 1 0 1 1 0 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 Format: DADD rd, rs, rt Description: The contents of general register rs and the con...
Page 470 - Doubleword Add Immediate; DADDI
APPENDIX A MIPS III INSTRUCTION SET DETAILS 470 Preliminary User’s Manual S15543EJ1V0UM DADDI Doubleword Add Immediate DADDI rs DADDI 0 1 1 0 0 0 rt immediate 31 26 25 21 20 16 15 0 6 5 5 16 Format: DADDI rt, rs, immediate Description: The 16-bit immediate is sign-extended and added to the contents ...
Page 471 - Doubleword Add Immediate Unsigned; DADDIU
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 471 DADDIU Doubleword Add Immediate Unsigned DADDIU rs DADDIU 0 1 1 0 0 1 rt immediate 31 26 25 21 20 16 15 0 6 5 5 16 Format: DADDIU rt, rs, immediate Description: The 16-bit immediate is sign-extended and added to ...
Page 472 - Doubleword Add Unsigned; DADDU
APPENDIX A MIPS III INSTRUCTION SET DETAILS 472 Preliminary User’s Manual S15543EJ1V0UM DADDU Doubleword Add Unsigned DADDU rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 DADDU 1 0 1 1 0 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 Format: DADDU rd, rs, rt Description: The contents of general register r...
Page 473 - Doubleword Divide; DDIV
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 473 DDIV Doubleword Divide DDIV rs SPECIAL 0 0 0 0 0 0 rt 0 0 0 0 0 0 0 0 0 0 0 DDIV 0 1 1 1 1 0 31 26 25 21 20 16 15 6 5 0 6 5 5 10 6 Format: DDIV rs, rt Description: The contents of general register rs are divided ...
Page 474 - Doubleword Divide Unsigned; DDIVU
APPENDIX A MIPS III INSTRUCTION SET DETAILS 474 Preliminary User’s Manual S15543EJ1V0UM DDIVU Doubleword Divide Unsigned DDIVU rs SPECIAL 0 0 0 0 0 0 rt 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 16 15 0 6 5 5 10 DDIVU 0 1 1 1 1 1 6 5 6 Format: DDIVU rs, rt Description: The contents of general register rs...
Page 475 - Divide; DIV
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 475 DIV Divide DIV rs SPECIAL 0 0 0 0 0 0 rt 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 16 15 0 6 5 5 10 DIV 0 1 1 0 1 0 6 5 6 Format: DIV rs, rt Description: The contents of general register rs are divided by the contents...
Page 476 - Divide Unsigned; DIVU
APPENDIX A MIPS III INSTRUCTION SET DETAILS 476 Preliminary User’s Manual S15543EJ1V0UM DIVU Divide Unsigned DIVU rs SPECIAL 0 0 0 0 0 0 rt 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 16 15 0 6 5 5 10 DIVU 0 1 1 0 1 1 6 5 6 Format: DIVU rs, rt Description: The contents of general register rs are divided by...
Page 477 - DMACC
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 477 DMACC Doubleword Multiply and Accumulate (1/3) DMACC rs SPECIAL 0 0 0 0 0 0 rt 1 31 26 25 21 20 16 15 0 6 5 5 DMACC 1 0 1 0 0 1 6 5 6 rd sat us 0 0 0 1 5 3 11 10 9 7 Format: DMACC rd, rs, rt DMACCU rd, rs, rt DMA...
Page 480 - Doubleword Move From System Control Coprocessor
APPENDIX A MIPS III INSTRUCTION SET DETAILS 480 Preliminary User’s Manual S15543EJ1V0UM DMFC0 Doubleword Move From System Control Coprocessor DMFC0 DMF 0 0 0 0 1 COP0 0 1 0 0 0 0 rt rd 31 26 25 21 20 16 15 0 6 5 5 5 0 0 0 0 0 0 0 0 0 0 0 0 11 10 11 Format: DMFC0 rt, rd Description: The contents of c...
Page 481 - Doubleword Move To System Control Coprocessor
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 481 DMTC0 Doubleword Move To System Control Coprocessor DMTC0 DMT 0 0 1 0 1 COP0 0 1 0 0 0 0 rt rd 31 26 25 21 20 16 15 0 6 5 5 5 0 0 0 0 0 0 0 0 0 0 0 0 11 10 11 Format: DMTC0 rt, rd Description: The contents of gen...
Page 482 - Doubleword Multiply; DMULT
APPENDIX A MIPS III INSTRUCTION SET DETAILS 482 Preliminary User’s Manual S15543EJ1V0UM DMULT Doubleword Multiply DMULT rs SPECIAL 0 0 0 0 0 0 rt 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 16 15 0 6 5 5 10 DMULT 0 1 1 1 0 0 6 5 6 Format: DMULT rs, rt Description: The contents of general registers rs and r...
Page 483 - Doubleword Multiply Unsigned; DMULTU
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 483 DMULTU Doubleword Multiply Unsigned DMULTU rs SPECIAL 0 0 0 0 0 0 rt 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 16 15 0 6 5 5 10 DMULTU 0 1 1 1 0 1 6 5 6 Format: DMULTU rs, rt Description: The contents of general regis...
Page 484 - Doubleword Shift Left Logical; DSLL
APPENDIX A MIPS III INSTRUCTION SET DETAILS 484 Preliminary User’s Manual S15543EJ1V0UM DSLL Doubleword Shift Left Logical DSLL 0 0 0 0 0 0 SPECIAL 0 0 0 0 0 0 rt rd sa DSLL 1 1 1 0 0 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 Format: DSLL rd, rt, sa Description: The contents of general register...
Page 485 - Doubleword Shift Left Logical Variable; DSLLV
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 485 DSLLV Doubleword Shift Left Logical Variable DSLLV rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 DSLLV 0 1 0 1 0 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 Format: DSLLV rd, rt, rs Description: The contents of gen...
Page 486 - Doubleword Shift Left Logical + 32
APPENDIX A MIPS III INSTRUCTION SET DETAILS 486 Preliminary User’s Manual S15543EJ1V0UM DSLL32 Doubleword Shift Left Logical + 32 DSLL32 0 0 0 0 0 0 SPECIAL 0 0 0 0 0 0 rt rd sa DSLL32 1 1 1 1 0 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 Format: DSLL32 rd, rt, sa Description: The contents of gen...
Page 487 - Doubleword Shift Right Arithmetic; DSRA
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 487 DSRA Doubleword Shift Right Arithmetic DSRA 0 0 0 0 0 0 SPECIAL 0 0 0 0 0 0 rt rd sa DSRA 1 1 1 0 1 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 Format: DSRA rd, rt, sa Description: The contents of general regi...
Page 488 - Doubleword Shift Right Arithmetic Variable; DSRAV
APPENDIX A MIPS III INSTRUCTION SET DETAILS 488 Preliminary User’s Manual S15543EJ1V0UM DSRAV Doubleword Shift Right Arithmetic Variable DSRAV rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 DSRAV 0 1 0 1 1 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 Format: DSRAV rd, rt, rs Description: The contents of...
Page 489 - Doubleword Shift Right Arithmetic + 32
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 489 DSRA32 Doubleword Shift Right Arithmetic + 32 DSRA32 0 0 0 0 0 0 SPECIAL 0 0 0 0 0 0 rt rd sa DSRA32 1 1 1 1 1 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 Format: DSRA32 rd, rt, sa Description: The contents of...
Page 490 - Doubleword Shift Right Logical; DSRL
APPENDIX A MIPS III INSTRUCTION SET DETAILS 490 Preliminary User’s Manual S15543EJ1V0UM DSRL Doubleword Shift Right Logical DSRL 0 0 0 0 0 0 SPECIAL 0 0 0 0 0 0 rt rd sa DSRL 1 1 1 0 1 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 Format: DSRL rd, rt, sa Description: The contents of general registe...
Page 491 - Doubleword Shift Right Logical Variable; DSRLV
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 491 DSRLV Doubleword Shift Right Logical Variable DSRLV rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 DSRLV 0 1 0 1 1 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 Format: DSRLV rd, rt, rs Description: The contents of ge...
Page 492 - Doubleword Shift Right Logical + 32
APPENDIX A MIPS III INSTRUCTION SET DETAILS 492 Preliminary User’s Manual S15543EJ1V0UM DSRL32 Doubleword Shift Right Logical + 32 DSRL32 0 0 0 0 0 0 SPECIAL 0 0 0 0 0 0 rt rd sa DSRL32 1 1 1 1 1 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 Format: DSRL32 rd, rt, sa Description: The contents of ge...
Page 493 - Doubleword Subtract; DSUB
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 493 DSUB Doubleword Subtract DSUB rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 DSUB 1 0 1 1 1 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 Format: DSUB rd, rs, rt Description: The contents of general register rt are su...
Page 494 - Doubleword Subtract Unsigned; DSUBU
APPENDIX A MIPS III INSTRUCTION SET DETAILS 494 Preliminary User’s Manual S15543EJ1V0UM DSUBU Doubleword Subtract Unsigned DSUBU rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 DSUBU 1 0 1 1 1 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 Format: DSUBU rd, rs, rt Description: The contents of general regis...
Page 495 - Exception Return; ERET
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 495 ERET Exception Return ERET CO 1 COP0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERET 0 1 1 0 0 0 31 26 25 24 6 5 0 6 1 19 6 Format: ERET Description: ERET is the instruction for returning from an interru...
Page 496 - Hibernate; HIBERNATE
APPENDIX A MIPS III INSTRUCTION SET DETAILS 496 Preliminary User’s Manual S15543EJ1V0UM HIBERNATE Hibernate HIBERNATE CO 1 COP0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIBERNATE 1 0 0 0 1 1 31 26 25 24 6 5 0 6 1 19 6 Format: HIBERNATE Description: HIBERNATE instruction starts mode transi...
Page 497 - Jump
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 497 J Jump J J 0 0 0 0 1 0 target 31 26 25 0 6 26 Format: J target Description: The 26-bit target address is shifted left two bits and combined with the high-order four bits of the address of the delay slot. The prog...
Page 498 - Jump And Link; JAL
APPENDIX A MIPS III INSTRUCTION SET DETAILS 498 Preliminary User’s Manual S15543EJ1V0UM JAL Jump And Link JAL JAL 0 0 0 0 1 1 target 31 26 25 0 6 26 Format: JAL target Description: The 26-bit target address is shifted left two bits and combined with the high-order four bits of the address of the del...
Page 499 - Jump And Link Register; JALR
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 499 JALR Jump And Link Register JALR rs SPECIAL 0 0 0 0 0 0 0 0 0 0 0 0 rd 0 0 0 0 0 0 JALR 0 0 1 0 0 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 Format: JALR rs JALR rd, rs Description: The program unconditionall...
Page 500 - Jump And Link Exchange; JALX
APPENDIX A MIPS III INSTRUCTION SET DETAILS 500 Preliminary User’s Manual S15543EJ1V0UM JALX Jump And Link Exchange JALX JALX 011101 31 26 25 0 6 26 target Format: JALX target Description: When a MIPS16 instruction can be executed, a 26-bit target is shifted to left by 2 bits and then added to highe...
Page 501 - Jump Register; JR
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 501 JR Jump Register JR rs SPECIAL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 0 6 5 15 JR 0 0 1 0 0 0 6 5 6 Format: JR rs Description: The program unconditionally jumps to the address contained in gen...
Page 502 - Load Byte; LB
APPENDIX A MIPS III INSTRUCTION SET DETAILS 502 Preliminary User’s Manual S15543EJ1V0UM LB Load Byte LB base LB 1 0 0 0 0 0 rt offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: LB rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to for...
Page 503 - Load Byte Unsigned; LBU
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 503 LBU Load Byte Unsigned LBU base LBU 1 0 0 1 0 0 rt offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: LBU rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general registe...
Page 504 - Load Doubleword; LD
APPENDIX A MIPS III INSTRUCTION SET DETAILS 504 Preliminary User’s Manual S15543EJ1V0UM LD Load Doubleword LD base LD 1 1 0 1 1 1 rt offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: LD rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base ...
Page 505 - LDL
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 505 LDL Load Doubleword Left (1/3) LDL base LDL 0 1 1 0 1 0 rt offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: LDL rt, offset (base) Description: This instruction can be used in combination with the LDR instruction to...
Page 508 - LDR
APPENDIX A MIPS III INSTRUCTION SET DETAILS 508 Preliminary User’s Manual S15543EJ1V0UM LDR Load Doubleword Right (1/3) LDR base LDR 0 1 1 0 1 1 rt offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: LDR rt, offset (base) Description: This instruction can be used in combination with the LDL instruction t...
Page 511 - Load Halfword; LH
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 511 LH Load Halfword LH base LH 1 0 0 0 0 1 rt offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: LH rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to...
Page 512 - Load Halfword Unsigned; LHU
APPENDIX A MIPS III INSTRUCTION SET DETAILS 512 Preliminary User’s Manual S15543EJ1V0UM LHU Load Halfword Unsigned LHU base LHU 1 0 0 1 0 1 rt offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: LHU rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general reg...
Page 513 - Load Upper Immediate; LUI
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 513 LUI Load Upper Immediate LUI 0 0 0 0 0 0 LUI 0 0 1 1 1 1 rt immediate 31 26 25 21 20 16 15 0 6 5 5 16 Format: LUI rt, immediate Description: The 16-bit immediate is shifted left 16 bits and concatenated to 16 bit...
Page 514 - Load Word; LW
APPENDIX A MIPS III INSTRUCTION SET DETAILS 514 Preliminary User’s Manual S15543EJ1V0UM LW Load Word LW base LW 1 0 0 0 1 1 rt offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: LW rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to for...
Page 515 - LWL
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 515 LWL Load Word Left (1/3) LWL base LWL 1 0 0 0 1 0 rt offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: LWL rt, offset (base) Description: This instruction can be used in combination with the LWR instruction to load ...
Page 518 - LWR
APPENDIX A MIPS III INSTRUCTION SET DETAILS 518 Preliminary User’s Manual S15543EJ1V0UM LWR Load Word Right (1/3) LWR base LWR 1 0 0 1 1 0 rt offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: LWR rt, offset (base) Description: This instruction can be used in combination with the LWL instruction to load...
Page 521 - Load Word Unsigned; LWU
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 521 LWU Load Word Unsigned LWU base LWU 1 0 1 1 1 1 rt offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: LWU rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general registe...
Page 522 - MACC
APPENDIX A MIPS III INSTRUCTION SET DETAILS 522 Preliminary User’s Manual S15543EJ1V0UM MACC Multiply and Accumulate (1/5) MACC rs SPECIAL 0 0 0 0 0 0 rt 1 31 26 25 21 20 16 15 0 6 5 5 MACC 1 0 1 0 0 0 6 5 6 rd sat us 0 0 1 5 1 11 10 9 7 hi 2 8 Format: MACC rd, rs, rt MACCU rd, rs, rt MACCHI rd, rs,...
Page 527 - Move From System Control Coprocessor
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 527 MFC0 Move From System Control Coprocessor MFC0 MF 0 0 0 0 0 COP0 0 1 0 0 0 0 rt 0 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 16 15 0 6 5 5 5 11 10 11 rd Format: MFC0 rt, rd Description: The contents of coprocessor regi...
Page 528 - Move From HI; MFHI
APPENDIX A MIPS III INSTRUCTION SET DETAILS 528 Preliminary User’s Manual S15543EJ1V0UM MFHI Move From HI MFHI 0 0 0 0 0 0 0 0 0 0 0 SPECIAL 0 0 0 0 0 0 31 26 25 11 10 16 15 0 6 10 5 6 rd 0 0 0 0 0 0 MFHI 0 1 0 0 0 0 5 6 5 Format: MFHI rd Description: The contents of special register HI are loaded i...
Page 529 - Move From LO; MFLO
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 529 MFLO Move From LO MFLO 0 0 0 0 0 0 0 0 0 0 0 SPECIAL 0 0 0 0 0 0 31 26 25 11 10 16 15 0 6 10 5 6 rd 0 0 0 0 0 0 MFLO 0 1 0 0 1 0 5 6 5 Format: MFLO rd Description: The contents of special register LO are loaded i...
Page 530 - Move To Coprocessor0
APPENDIX A MIPS III INSTRUCTION SET DETAILS 530 Preliminary User’s Manual S15543EJ1V0UM MTC0 Move To Coprocessor0 MTC0 0 0 0 0 0 0 0 0 0 0 0 0 COP0 0 1 0 0 0 0 31 26 25 11 10 16 15 0 6 11 5 5 rt rd MT 0 0 1 0 0 5 21 20 Format: MTC0 rt, rd Description: The contents of general register rt are loaded i...
Page 531 - Move To HI; MTHI
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 531 MTHI Move To HI rs SPECIAL 0 0 0 0 0 0 MTHI 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 6 5 0 6 5 6 15 MTHI Format: MTHI rs Description: The contents of general register rs are loaded into special ...
Page 532 - Move To LO; MTLO
APPENDIX A MIPS III INSTRUCTION SET DETAILS 532 Preliminary User’s Manual S15543EJ1V0UM MTLO Move To LO MTLO rs SPECIAL 0 0 0 0 0 0 MTLO 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 6 5 0 6 5 6 15 Format: MTLO rs Description: The contents of general register rs are loaded into special ...
Page 533 - Multiply; MULT
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 533 MULT Multiply MULT rs SPECIAL 0 0 0 0 0 0 MULT 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 6 5 0 6 5 6 10 rt 5 16 15 Format: MULT rs, rt Description: The contents of general registers rs and rt are multiplie...
Page 534 - Multiply Unsigned; MULTU
APPENDIX A MIPS III INSTRUCTION SET DETAILS 534 Preliminary User’s Manual S15543EJ1V0UM MULTU Multiply Unsigned MULTU rs SPECIAL 0 0 0 0 0 0 MULTU 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 6 5 0 6 5 6 10 rt 5 16 15 Format: MULTU rs, rt Description: The contents of general register rs and the ...
Page 535 - Nor; NOR
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 535 NOR Nor NOR rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 NOR 1 0 0 1 1 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 Format: NOR rd, rs, rt Description: The contents of general register rs are combined with the cont...
Page 536 - Or; OR
APPENDIX A MIPS III INSTRUCTION SET DETAILS 536 Preliminary User’s Manual S15543EJ1V0UM OR Or OR rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 OR 1 0 0 1 0 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 Format: OR rd, rs, rt Description: The contents of general register rs are combined with the contents ...
Page 537 - Or Immediate; ORI
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 537 ORI Or Immediate ORI rs ORI 0 0 1 1 0 1 rt immediate 31 26 25 21 20 16 15 0 6 5 5 16 Format: ORI rt, rs, immediate Description: The 16-bit immediate is zero-extended and combined with the contents of general regi...
Page 538 - Store Byte; SB
APPENDIX A MIPS III INSTRUCTION SET DETAILS 538 Preliminary User’s Manual S15543EJ1V0UM SB Store Byte SB base SB 1 0 1 0 0 0 rt offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: SB rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to fo...
Page 539 - Store Doubleword; SD
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 539 SD Store Doubleword SD base SD 1 1 1 1 1 1 rt offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: SD rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base...
Page 540 - SDL
APPENDIX A MIPS III INSTRUCTION SET DETAILS 540 Preliminary User’s Manual S15543EJ1V0UM SDL Store Doubleword Left (1/3) SDL base SDL 1 0 1 1 0 0 rt offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: SDL rt, offset (base) Description: This instruction can be used with the SDR instruction to store the con...
Page 543 - SDR
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 543 SDR Store Doubleword Right (1/3) SDR base SDR 1 0 1 1 0 1 rt offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: SDR rt, offset (base) Description: This instruction can be used with the SDL instruction to store the co...
Page 546 - Store Halfword; SH
APPENDIX A MIPS III INSTRUCTION SET DETAILS 546 Preliminary User’s Manual S15543EJ1V0UM SH Store Halfword SH base SH 1 0 1 0 0 1 rt offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: SH rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base t...
Page 547 - Shift Left Logical; SLL
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 547 SLL Shift Left Logical SLL SPECIAL 0 0 0 0 0 0 rt rd sa SLL 0 0 0 0 0 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 0 0 0 0 0 0 Format: SLL rd, rt, sa Description: The contents of general register rt are shifted...
Page 548 - Shift Left Logical Variable; SLLV
APPENDIX A MIPS III INSTRUCTION SET DETAILS 548 Preliminary User’s Manual S15543EJ1V0UM SLLV Shift Left Logical Variable SLLV SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 SLLV 0 0 0 1 0 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 rs Format: SLLV rd, rt, rs Description: The contents of general register r...
Page 549 - Set On Less Than; SLT
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 549 SLT Set On Less Than SLT rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 SLT 1 0 1 0 1 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 Format: SLT rd, rs, rt Description: The contents of general register rt are subtracte...
Page 550 - Set On Less Than Immediate; SLTI
APPENDIX A MIPS III INSTRUCTION SET DETAILS 550 Preliminary User’s Manual S15543EJ1V0UM SLTI Set On Less Than Immediate SLTI rs SLTI 0 0 1 0 1 0 rt immediate 31 26 25 21 20 16 15 0 6 5 5 16 Format: SLTI rt, rs, immediate Description: The 16-bit immediate is sign-extended and subtracted from the cont...
Page 551 - Set On Less Than Immediate Unsigned; SLTIU
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 551 SLTIU Set On Less Than Immediate Unsigned SLTIU rs SLTIU 0 0 1 0 1 1 rt immediate 31 26 25 21 20 16 15 0 6 5 5 16 Format: SLTIU rt, rs, immediate Description: The 16-bit immediate is sign-extended and subtracted ...
Page 552 - Set On Less Than Unsigned; SLTU
APPENDIX A MIPS III INSTRUCTION SET DETAILS 552 Preliminary User’s Manual S15543EJ1V0UM SLTU Set On Less Than Unsigned SLTU rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 SLTU 1 0 1 0 1 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 Format: SLTU rd, rs, rt Description: The contents of general register rt ...
Page 553 - Shift Right Arithmetic; SRA
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 553 SRA Shift Right Arithmetic SRA 0 0 0 0 0 0 SPECIAL 0 0 0 0 0 0 rt rd sa SRA 0 0 0 0 1 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 Format: SRA rd, rt, sa Description: The contents of general register rt are shi...
Page 554 - Shift Right Arithmetic Variable; SRAV
APPENDIX A MIPS III INSTRUCTION SET DETAILS 554 Preliminary User’s Manual S15543EJ1V0UM SRAV Shift Right Arithmetic Variable SRAV rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 SRAV 0 0 0 1 1 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 Format: SRAV rd, rt, rs Description: The contents of general regist...
Page 555 - Shift Right Logical; SRL
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 555 SRL Shift Right Logical SRL 0 0 0 0 0 0 SPECIAL 0 0 0 0 0 0 rt rd sa SRL 0 0 0 0 1 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 Format: SRL rd, rt, sa Description: The contents of general register rt are shifte...
Page 556 - Shift Right Logical Variable; SRLV
APPENDIX A MIPS III INSTRUCTION SET DETAILS 556 Preliminary User’s Manual S15543EJ1V0UM SRLV Shift Right Logical Variable SRLV rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 SRLV 0 0 0 1 1 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 Format: SRLV rd, rt, rs Description: The contents of general register ...
Page 557 - Standby; STANDBY
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 557 STANDBY Standby STANDBY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COP0 0 1 0 0 0 0 STANDBY1 0 0 0 0 1 31 26 25 6 5 0 6 19 6 CO 1 1 24 Format: STANDBY Description: STANDBY instruction starts mode transition from Ful...
Page 558 - Subtract; SUB
APPENDIX A MIPS III INSTRUCTION SET DETAILS 558 Preliminary User’s Manual S15543EJ1V0UM SUB Subtract SUB rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 SUB 1 0 0 0 1 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 Format: SUB rd, rs, rt Description: The contents of general register rt are subtracted from t...
Page 559 - Subtract Unsigned; SUBU
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 559 SUBU Subtract Unsigned SUBU rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 SUBU 1 0 0 0 1 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 Format: SUBU rd, rs, rt Description: The contents of general register rt are subt...
Page 560 - Suspend; SUSPEND
APPENDIX A MIPS III INSTRUCTION SET DETAILS 560 Preliminary User’s Manual S15543EJ1V0UM SUSPEND Suspend SUSPEND 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COP0 0 1 0 0 0 0 SUSPEND 1 0 0 0 1 0 31 26 25 6 5 0 6 19 6 CO 1 1 24 Format: SUSPEND Description: SUSPEND instruction starts mode transition from Fu...
Page 561 - Store Word; SW
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 561 SW Store Word SW base SW 1 0 1 0 1 1 rt offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: SW rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to fo...
Page 562 - SWL
APPENDIX A MIPS III INSTRUCTION SET DETAILS 562 Preliminary User’s Manual S15543EJ1V0UM SWL Store Word Left (1/3) SWL base SW L 1 0 1 0 1 0 rt offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: SWL rt, offset (base) Description: This instruction can be used with the SWR instruction to store the contents...
Page 565 - SWR
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 565 SWR Store Word Right (1/3) SWR base SWR 1 0 1 1 1 0 rt offset 31 26 25 21 20 16 15 0 6 5 5 16 Format: SWR rt, offset (base) Description: This instruction can be used with the SWL instruction to store the contents...
Page 568 - Synchronize; SYNC
APPENDIX A MIPS III INSTRUCTION SET DETAILS 568 Preliminary User’s Manual S15543EJ1V0UM SYNC Synchronize SYNC SPECIAL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 26 25 6 5 0 6 20 SYNC 0 0 1 1 1 1 6 Format: SYNC Description: The SYNC instruction is executed as a NOP on the V R 4121. This...
Page 569 - System Call; SYSCALL
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 569 SYSCALL System Call SYSCALL SPECIAL 0 0 0 0 0 0 Code 31 26 25 6 5 0 6 20 SYSCALL 0 0 1 1 0 0 6 Format: SYSCALL Description: A system call exception occurs, immediately and unconditionally transferring control to ...
Page 570 - Trap If Equal; TEQ
APPENDIX A MIPS III INSTRUCTION SET DETAILS 570 Preliminary User’s Manual S15543EJ1V0UM TEQ Trap If Equal TEQ rs SPECIAL 0 0 0 0 0 0 rt code 31 26 25 21 20 16 15 0 6 5 5 10 TEQ 1 1 0 1 0 0 6 6 5 Format: TEQ rs, rt Description: The contents of general register rt are compared to general register rs. ...
Page 571 - Trap If Equal Immediate; TEQI
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 571 TEQI Trap If Equal Immediate TEQI rs REGIMM 0 0 0 0 0 1 TEQI 0 1 1 0 0 immediate 31 26 25 21 20 16 15 0 6 5 5 16 Format: TEQI rs, immediate Description: The 16-bit immediate is sign-extended and compared to the c...
Page 572 - Trap If Greater Than Or Equal; TGE
APPENDIX A MIPS III INSTRUCTION SET DETAILS 572 Preliminary User’s Manual S15543EJ1V0UM TGE Trap If Greater Than Or Equal TGE rs SPECIAL 0 0 0 0 0 0 rt code 31 26 25 21 20 16 15 0 6 5 5 10 TGE 1 1 0 0 0 0 6 6 5 Format: TGE rs, rt Description: The contents of general register rt are compared to the c...
Page 573 - Trap If Greater Than Or Equal Immediate; TGEI
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 573 TGEI Trap If Greater Than Or Equal Immediate TGEI rs REGIMM 0 0 0 0 0 1 TGEI 0 1 0 0 0 immediate 31 26 25 21 20 16 15 0 6 5 5 16 Format: TGEI rs, immediate Description: The 16-bit immediate is sign-extended and c...
Page 574 - Trap If Greater Than Or Equal Immediate Unsigned; TGEIU
APPENDIX A MIPS III INSTRUCTION SET DETAILS 574 Preliminary User’s Manual S15543EJ1V0UM TGEIU Trap If Greater Than Or Equal Immediate Unsigned TGEIU rs REGIMM 0 0 0 0 0 1 TGEIU 0 1 0 0 1 immediate 31 26 25 21 20 16 15 0 6 5 5 16 Format: TGEIU rs, immediate Description: The 16-bit immediate is sign-e...
Page 575 - Trap If Greater Than Or Equal Unsigned; TGEU
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 575 TGEU Trap If Greater Than Or Equal Unsigned TGEU rs SPECIAL 0 0 0 0 0 0 rt code 31 26 25 21 20 16 15 0 6 5 5 10 TGEU 1 1 0 0 0 1 6 6 5 Format: TGEU rs, rt Description: The contents of general register rt are comp...
Page 576 - Probe TLB For Matching Entry; TLBP
APPENDIX A MIPS III INSTRUCTION SET DETAILS 576 Preliminary User’s Manual S15543EJ1V0UM TLBP Probe TLB For Matching Entry TLBP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COP0 0 1 0 0 0 0 TLBP 0 0 1 0 0 0 31 26 25 6 5 0 6 19 6 CO 1 1 24 Format: TLBP Description: The Index register is loaded with the add...
Page 577 - Read Indexed TLB Entry; TLBR
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 577 TLBR Read Indexed TLB Entry TLBR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COP0 0 1 0 0 0 0 TLBR 0 0 0 0 0 1 31 26 25 6 5 0 6 19 6 CO 1 1 24 Format: TLBR Description: The EntryHi and EntryLo registers are loaded wi...
Page 578 - Write Indexed TLB Entry; TLBWI
APPENDIX A MIPS III INSTRUCTION SET DETAILS 578 Preliminary User’s Manual S15543EJ1V0UM TLBWI Write Indexed TLB Entry TLBWI 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COP0 0 1 0 0 0 0 TLBW I 0 0 0 0 1 0 31 26 25 6 5 0 6 19 6 CO 1 1 24 Format: TLBWI Description: The TLB entry pointed at by the contents ...
Page 579 - Write Random TLB Entry; TLBWR
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 579 TLBWR Write Random TLB Entry TLBWR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COP0 0 1 0 0 0 0 TLBW R 0 0 0 1 1 0 31 26 25 6 5 0 6 19 6 CO 1 1 24 Format: TLBWR Description: The TLB entry pointed at by the contents o...
Page 580 - Trap If Less Than; TLT
APPENDIX A MIPS III INSTRUCTION SET DETAILS 580 Preliminary User’s Manual S15543EJ1V0UM TLT Trap If Less Than TLT rs SPECIAL 0 0 0 0 0 0 rt code 31 26 25 21 20 16 15 0 6 5 5 10 TLT 1 1 0 0 1 0 6 6 5 Format: TLT rs, rt Description: The contents of general register rt are compared to general register ...
Page 581 - Trap If Less Than Immediate; TLTI
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 581 TLTI Trap If Less Than Immediate TLTI rs REGIMM 0 0 0 0 0 1 TLTI 0 1 0 1 0 immediate 31 26 25 21 20 16 15 0 6 5 5 16 Format: TLTI rs, immediate Description: The 16-bit immediate is sign-extended and compared to t...
Page 582 - Trap If Less Than Immediate Unsigned; TLTIU
APPENDIX A MIPS III INSTRUCTION SET DETAILS 582 Preliminary User’s Manual S15543EJ1V0UM TLTIU Trap If Less Than Immediate Unsigned TLTIU rs REGIMM 0 0 0 0 0 1 TLTIU 0 1 0 1 1 immediate 31 26 25 21 20 16 15 0 6 5 5 16 Format: TLTIU rs, immediate Description: The 16-bit immediate is sign-extended and ...
Page 583 - Trap If Less Than Unsigned; TLTU
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 583 TLTU Trap If Less Than Unsigned TLTU rs SPECIAL 0 0 0 0 0 0 rt code 31 26 25 21 20 16 15 0 6 5 5 10 TLTU 1 1 0 0 1 1 6 6 5 Format: TLTU rs, rt Description: The contents of general register rt are compared to gene...
Page 584 - Trap If Not Equal; TNE
APPENDIX A MIPS III INSTRUCTION SET DETAILS 584 Preliminary User’s Manual S15543EJ1V0UM TNE Trap If Not Equal TNE rs SPECIAL 0 0 0 0 0 0 rt code 31 26 25 21 20 16 15 0 6 5 5 10 TNE 1 1 0 1 1 0 6 6 5 Format: TNE rs, rt Description: The contents of general register rt are compared to general register ...
Page 585 - Trap If Not Equal Immediate; TNEI
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 585 TNEI Trap If Not Equal Immediate TNEI rs REGIMM 0 0 0 0 0 1 TNEI 0 1 1 1 0 immediate 31 26 25 21 20 16 15 0 6 5 5 16 Format: TNEI rs, immediate Description: The 16-bit immediate is sign-extended and compared to t...
Page 586 - Exclusive Or; XOR
APPENDIX A MIPS III INSTRUCTION SET DETAILS 586 Preliminary User’s Manual S15543EJ1V0UM XOR Exclusive Or XOR rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 XOR 1 0 0 1 1 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 Format: XOR rd, rs, rt Description: The contents of general register rs are combined with...
Page 587 - Exclusive OR Immediate; XORI
APPENDIX A MIPS III INSTRUCTION SET DETAILS Preliminary User’s Manual S15543EJ1V0UM 587 XORI Exclusive OR Immediate XORI rs XORI 0 0 1 1 1 0 rt immediate 31 26 25 21 20 16 15 0 6 5 5 16 Format: XORI rt, rs, immediate Description: The 16-bit immediate is zero-extended and combined with the contents o...
Page 588 - A.6 CPU Instruction Opcode Bit Encoding
APPENDIX A MIPS III INSTRUCTION SET DETAILS 588 Preliminary User’s Manual S15543EJ1V0UM A.6 CPU Instruction Opcode Bit Encoding Figure A-1 lists the V R 4120A Opcode Bit Encoding. Figure A-1. V R 4120A Opcode Bit Encoding (1/2) 28...26 Opcode 31...29 0 1 2 3 4 5 6 7 0 SPECIAL REGIMM J JAL BEQ BNE BL...
Page 590 - APPENDIX B V
590 Preliminary User’s Manual S15543EJ1V0UM APPENDIX B V R 4120A COPROCESSOR 0 HAZARDS The V R 4120A core avoids contention of its internal resources by causing a pipeline interlock in such cases as when the contents of the destination register of an instruction are used as a source in the succeedin...
Page 595 - Thank you for your kind support.; Document Rating; Facsimile
Although NEC has taken all possible stepsto ensure that the documentation suppliedto our customers is complete, bug freeand up-to-date, we readily accept thaterrors may occur. Despite all the care andp r e c a u t i o n s w e ' v e t a k e n , y o u m a yencounter problems in the documentation.Pleas...
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