Page 3 - NOTES FOR CMOS DEVICES; to be taken for PW boards with semiconductor devices on it.; or GND with a resistor, if it is considered to have a possibility of
3 FIP, EEPROM, IEBus, and QTOP are trademarks of NEC Corporation. MS-DOS, Windows, and WindowsNT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. IBM DOS, IBM PC/AT, and PC DOS are trademarks of International Business Machines Corpo...
Page 4 - The customer must judge the need for license:
4 The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. Purchase of NEC I 2 C components conveys a license under the Philips I 2 C Patent Rights to use these components in an I 2 C system, provided that the system conforms to the I 2 ...
Page 5 - Regional Information; • Device availability
5 NEC Electronics Inc. (U.S.) Santa Clara, CaliforniaTel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Duesseldorf, GermanyTel: 0211-65 03 02Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. Milton Keynes, UKTel: 01908-691-133Fax: 01908-670-290 NEC Electronics ...
Page 6 - Major Revisions in This Edition; The mark
6 Major Revisions in This Edition Page Description Throughout The following products have been changed from “under development” to “already developed”. µ PD78078Y Subseries: µ PD78076Y, 78078Y, 78P078Y The following packages have been added to the µ PD78078Y Subseries. 100-pin plastic LQFP (Fine pit...
Page 7 - INTRODUCTION
7 INTRODUCTION Readers This manual has been prepared for user engineers who understand the functions of the µ PD78078 and 78078Y Subseries and design and develop its application systems and programs. The µ PD78078 and 78078Y Subseries consist of the following members. • µ PD78078 Subseries: µ PD7807...
Page 10 - • Development Tool Documents (User’s Manuals); version when starting design.
10 • Development Tool Documents (User’s Manuals) Document Name Document No. English Japanese RA78K Series Assembler Package Operation EEU-1399 EEU-809 Language EEU-1404 EEU-815 RA78K Series Structured Assembler Preprocessor EEU-1402 U12323J RA78K0 Assembler Package Operation U11802E U11802J Language...
Page 13 - PROM programming mode pins (
13 TABLE OF CONTENTS CHAPTER 1 OUTLINE ( µ PD78078 SUBSERIES) ................................................................................. 33 1.1 Features .................................................................................................................................. 33 1.2 Ap...
Page 14 - CHAPTER 4 PIN FUNCTION (
14 3.2.17 AV SS ............................................................................................................................................. 76 3.2.18 RESET .................................................................................................................................
Page 16 - Outline of Timers Incorporated into
16 CHAPTER 7 CLOCK GENERATOR .................................................................................................... 165 7.1 Clock Generator Functions ................................................................................................ 165 7.2 Clock Generator Configuration ....
Page 20 - APPENDIX A DIFFERENCES BETWEEN
20 CHAPTER 27 µ PD78P078, 78P078Y .................................................................................................. 569 27.1 Internal Memory Size Switching Register ........................................................................ 570 27.2 Internal Extension RAM Size Switchin...
Page 21 - Data Memory Addressing (
21 LIST OF FIGURES (1/9) Figure No. Title Page 3-1 List of Pin Input/Output Circuits ................................................................................................... 80 4-1 List of Pin Input/Output Circuits .............................................................................
Page 22 - Control Register Settings for Two Pulse Width Measurements with
22 LIST OF FIGURES (2/9) Figure No. Title Page 7-1 Block Diagram of Clock Generator ............................................................................................ 166 7-2 Subsystem Clock Feedback Resistor ....................................................................................
Page 23 - Timing of One-Shot Pulse Output Operation Using External Trigger
23 LIST OF FIGURES (3/9) Figure No. Title Page 8-26 Control Register Settings in External Event Counter Mode ..................................................... 211 8-27 External Event Counter Configuration Diagram ........................................................................ 212 8-28 E...
Page 24 - Handling of AV
24 LIST OF FIGURES (4/9) Figure No. Title Page 10-14 8-Bit Timer Control Register Settings for PWM Output Operation .......................................... 264 10-15 PWM Output Operation Timing (Active High Setting) ............................................................... 265 10-16 PWM Out...
Page 25 - Serial Bus Configuration Example Using I
25 LIST OF FIGURES (5/9) Figure No. Title Page 17-1 Serial Bus Interface (SBI) System Configuration Example ...................................................... 317 17-2 Serial Interface Channel 0 Block Diagram ................................................................................ 318 17...
Page 26 - Example of Serial Bus Configuration Using I
26 LIST OF FIGURES (6/9) Figure No. Title Page 18-10 Serial Bus Configuration Example Using 2-Wire Serial I/O Mode ........................................... 385 18-11 2-Wire Serial I/O Mode Timings ................................................................................................. 38...
Page 30 - Differences between
30 LIST OF TABLES (1/3) Table No. Title Page 1-1 Mask Options of Mask ROM Versions ......................................................................................... 47 1-2 Differences between µ PD78078 Subseries and µ PD78054 Subseries ..................................... 47 2-1 Mask Option...
Page 31 - Signals in I
31 LIST OF TABLES (2/3) Table No. Title Page 9-9 Interval Times when 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2) are Used as 16-Bit Timer/Event Counter .................................................................................. 243 9-10 Square-Wave Output Ranges when 2-Channel 8-Bit Ti...
Page 32 - Relationship between ASCK Pin Input Frequency and Baud Rate
32 LIST OF TABLES (3/3) Table No. Title Page 20-3 Relationship between Main System Clock and Baud Rate ...................................................... 467 20-4 Relationship between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H) ..................................................
Page 33 - CHAPTER 1 OUTLINE (; Program Memory
33 CHAPTER 1 OUTLINE ( µ PD78078 SUBSERIES) 1.1 Features Internal high-capacity ROM and RAM Notes 1. The capacity of internal PROM can be changed by means of the internal memory size switching register (IMS). 2. The capacity of internal high-speed RAM can be changed by means of the internal expansio...
Page 34 - Application Fields; Note; Under development; Caution Two types of packages are available for the; xxx indicates ROM code suffix.
34 CHAPTER 1 OUTLINE ( µ PD78078 SUBSERIES) 1.2 Application Fields Cellular phones, cordless telephones, printers, AV equipment, air conditioners, cameras, PPCs, fuzzy home appliances, vending machines, etc. 1.3 Ordering Information Part number Package Internal ROM µ PD78076GC-xxx-7EA 100-pin plasti...
Page 35 - mass-produced and require high reliability.
35 CHAPTER 1 OUTLINE ( µ PD78078 SUBSERIES) 1.4 Quality Grade Part number Package Quality grades µ PD78076GC-xxx-7EA 100-pin plastic QFP (Fine pitch) (14 x 14 mm, resin thickness 1.45 mm) Standard µ PD78076GC-xxx-8EU Note 100-pin plastic LQFP (Fine pitch) (14 x 14 mm, resin thickness 1.4 mm) Standar...
Page 37 - pin to V; Remark; Pin connection in parentheses is for the; AV; AV; RESET
37 CHAPTER 1 OUTLINE ( µ PD78078 SUBSERIES) Cautions 1. Connect IC (Internally Connected) pin to V SS directly. 2. Connect AV DD pin to V DD . 3. Connect AV SS pin to V SS . Remark Pin connection in parentheses is for the µ PD78P078. 100 P13/ANI3 P122/RTP2P121/RTP1P120/RTP0P96P95P94P93P92P91P90P37P3...
Page 39 - Pin Identifications
39 CHAPTER 1 OUTLINE ( µ PD78078 SUBSERIES) Pin Identifications A0 to A15 : Address Bus AD0 to AD7 : Address/Data Bus ANI0 to ANI7 : Analog Input ANO0, ANO1 : Analog Output ASCK : Asynchronous Serial Clock ASTB : Address Strobe AV DD : Analog Power Supply AV REF0 , AV REF1 : Analog Reference Voltage...
Page 40 - : Connect independently to V
40 CHAPTER 1 OUTLINE ( µ PD78078 SUBSERIES) (2) PROM programming mode 100-pin plastic QFP (Fine pitch) (14 x 14 mm, resin thickness 1.45 mm) µ PD78P078GC-7EA 100-pin plastic LQFP (Fine pitch) (14 x 14 mm, resin thickness 1.4 mm) µ PD78P078GC-8EU Note Note Under development Cautions 1. (L) : Connect ...
Page 41 - : Programming Power Supply
41 CHAPTER 1 OUTLINE ( µ PD78078 SUBSERIES) 100-pin plastic QFP (14 x 20 mm) µ PD78P078GF-3BA 100-pin ceramic WQFN µ PD78P078KL-T Cautions 1. (L) : Connect independently to V SS via a pull-down resistor. 2. V SS : Connect to the ground. 3. RESET : Set to the low level. 4. Open : Leave open. A0 to A1...
Page 42 - Planned
42 CHAPTER 1 OUTLINE ( µ PD78078 SUBSERIES) 1.6 78K/0 Series Expansion The products in the 78K/0 Series are listed below. The names in boxes are subseries names. Note Planned µ PD78098 80-pin Added IEBus controller to µ PD78054 µ PD78044F 80-pin Basic subseries for driving FIPs, 34 display outputs µ...
Page 44 - Pin connection in parentheses is for the
44 CHAPTER 1 OUTLINE ( µ PD78078 SUBSERIES) 1.7 Block Diagram Remarks 1. The internal ROM and RAM capacities depend on the product. 2. Pin connection in parentheses is for the µ PD78P078. TO0/P30 TI00/INTP0/P00TI01/INTP1/P01 InterruptControl SerialInterface 1 A/D Converter SerialInterface 0 Watchdog...
Page 45 - Outline of Function
45 CHAPTER 1 OUTLINE ( µ PD78078 SUBSERIES) 1.8 Outline of Function Internal ROM Mask ROM PROM memory 48 Kbytes 60 Kbytes 60 Kbytes Note 1 High-speed RAM 1024 bytes Buffer RAM 32 bytes Expansion RAM 1024 bytes 1024 bytes Note 2 Memory space 64 Kbytes General register 8 bits x 8 x 4 banks With main s...
Page 47 - Table 1-1. Mask Options of Mask ROM Versions; Differences with
47 CHAPTER 1 OUTLINE ( µ PD78078 SUBSERIES) 1.9 Mask Options The mask ROM versions ( µ PD78076, 78078) provide pull-up register mask options which allow users to specify whether to connect a pull-up register to a specific port pin when the user places an order for the device production. Using this m...
Page 49 - CHAPTER 2 OUTLINE (; Notes
49 Data Memory Part Number Type Program Memory (ROM) µ PD78076Y µ PD78078Y µ PD78P078Y CHAPTER 2 OUTLINE ( µ PD78078Y SUBSERIES) 2.1 Features Internal high-capacity ROM and RAM Notes 1. The capacity of internal PROM can be changed using the internal memory size switching register (IMS). 2. The capac...
Page 50 - Application Fields
50 CHAPTER 2 OUTLINE ( µ PD78078Y SUBSERIES) 2.2 Application Fields Cellular phones, cordless telephones, printers, AV equipment, air conditioners, cameras, PPCs, fuzzy home appliances, vending machines, etc. 2.3 Ordering Information Part number Package Internal ROM µ PD78076YGC-xxx-8EU Note 100-pin...
Page 59 - Major differences among Y subseries are tabulated below.
59 CHAPTER 2 OUTLINE ( µ PD78078Y SUBSERIES) Major differences among Y subseries are tabulated below. Function ROM Configuration of Serial Interface I/O V DD Subseries Capacity MIN. Control µ PD78078Y 48K to 60K 3-wire/2-wire/I 2 C : 1 ch 88 1.8 V 3-wire with automatic transmit/receive function : 1 ...
Page 61 - Outline of Function
61 CHAPTER 2 OUTLINE ( µ PD78078Y SUBSERIES) Part Number 2.8 Outline of Function Mask ROM PROM 48 Kbytes 60 Kbytes 60 Kbytes Note 1 High-speed RAM 1024 bytes Buffer RAM 32 bytes Expansion RAM 1024 bytes 1024 bytes Memory space 64 Kbytes General register 8 bits x 8 x 4 banks With main system clock se...
Page 63 - Table 2-1. Mask Options of Mask ROM Versions; Differences with
63 CHAPTER 2 OUTLINE ( µ PD78078Y SUBSERIES) 2.9 Mask Options The mask ROM versions ( µ PD78076Y, 78078Y) provide pull-up register mask options which allow users to specify whether to connect a pull-up register to a specific port pin when the user places an order for the device production. Using thi...
Page 66 - CHAPTER 3 PIN FUNCTION (
66 CHAPTER 3 PIN FUNCTION ( µ PD78078 SUBSERIES) (1) Port pins (2/3) Pin Name Input/Output Function After Reset Alternate Function P30 TO0 P31 TO1 P32 Port 3. TO2 P33 Input/ 8-bit input/output port. TI1 P34 output Input/output mode can be specified bit-wise. TI2 P35 If used as an input port, an on-c...
Page 70 - Description of Pin Functions
70 CHAPTER 3 PIN FUNCTION ( µ PD78078 SUBSERIES) 3.2 Description of Pin Functions 3.2.1 P00 to P07 (Port 0) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt request input, an external count clock input to the timer, a capture trigger s...
Page 71 - Caution
71 CHAPTER 3 PIN FUNCTION ( µ PD78078 SUBSERIES) 3.2.3 P20 to P27 (Port 2) These are 8-bit input/output ports. Besides serving as input/output ports, they function as data input/output to/ from the serial interface, clock input/output, automatic transmit/receive busy input, and strobe output functio...
Page 72 - output and buzzer output.
72 CHAPTER 3 PIN FUNCTION ( µ PD78078 SUBSERIES) 3.2.4 P30 to P37 (Port 3) These are 8-bit input/output ports. Beside serving as input/output ports, they function as timer input/output, clock output and buzzer output. The following operating modes can be specified bit-wise. (1) Port mode These ports...
Page 73 - Port 5 can drive LEDs directly.
73 CHAPTER 3 PIN FUNCTION ( µ PD78078 SUBSERIES) 3.2.6 P50 to P57 (Port 5) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an address bus. Port 5 can drive LEDs directly. The following operating modes can be specified bit-wise. (1) Port mode These ports fu...
Page 74 - to the function the user requires.
74 CHAPTER 3 PIN FUNCTION ( µ PD78078 SUBSERIES) 3.2.8 P70 to P72 (Port 7) This is a 3-bit input/output port. In addition to its use as an input/output port, it also has serial interface data input/ output and clock input/output functions. The following operating modes can be specified bit-wise. (1)...
Page 76 - that are not used as analog outputs must be set as follows:
76 CHAPTER 3 PIN FUNCTION ( µ PD78078 SUBSERIES) 3.2.13 P130 and P131 (Port 13) These are 2-bit input/output ports. Besides serving as input/output ports, they are used for D/A converter analog output. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 2-b...
Page 77 - Connect IC pins to V
77 CHAPTER 3 PIN FUNCTION ( µ PD78078 SUBSERIES) 3.2.21 V DD Positive power supply pin 3.2.22 V SS Ground potential pin 3.2.23 V PP ( µ PD78P078 only) High-voltage apply pin for PROM programming mode setting and program write/verify. Connect directly to V SS in normal operating mode. 3.2.24 IC (Mask...
Page 84 - CHAPTER 4 PIN FUNCTION (
84 CHAPTER 4 PIN FUNCTION ( µ PD78078Y SUBSERIES) Input P40 to P47 Input AD0 to AD7 (1) Port pins (2/3) Pin Name Input/Output Function After Reset Alternate Function P30 TO0 P31 TO1 P32 Port 3. TO2 P33 Input/ 8-bit input/output port. TI1 P34 output Input/output mode can be specified bit-wise. TI2 P3...
Page 88 - Description of Pin Functions
88 CHAPTER 4 PIN FUNCTION ( µ PD78078Y SUBSERIES) 4.2 Description of Pin Functions 4.2.1 P00 to P07 (Port 0) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt request input, an external count clock input to the timer, a capture trigger ...
Page 89 - The following operating modes can be specified bit-wise.
89 CHAPTER 4 PIN FUNCTION ( µ PD78078Y SUBSERIES) 4.2.3 P20 to P27 (Port 2) These are 8-bit input/output ports. Besides serving as input/output ports, they function as data input/output to/ from the serial interface, clock input/output, automatic transmit/receive busy input, and strobe output functi...
Page 93 - P90 to P93 can drive LEDs directly.
93 CHAPTER 4 PIN FUNCTION ( µ PD78078Y SUBSERIES) 4.2.10 P90 to P96 (Port 9) These are 7-bit input/output ports. P90 to P93 can drive LEDs directly. They can be specified bit-wise as input or output ports with port mode register 9 (PM9). P90 to P93 are N-ch open-drain pins. Mask ROM version product ...
Page 101 - CHAPTER 5 CPU ARCHITECTURE; The
101 0000H Data memory space General Registers 32 x 8 bits Internal ROM 49152 x 8 bits BFFFH 1000H0FFFH 0800H07FFH 0080H 007FH 0040H003FH 0000H CALLF Entry Area CALLT Table Area Vector Table Area Program Area Program Area Internal Buffer RAM 32 x 8 bits External Memory 13312 x 8 bits Reserved Program...
Page 102 - internal memory size switching register.
102 CHAPTER 5 CPU ARCHITECTURE 0000H Data memory space General Registers 32 x 8 bits Internal ROM 61440 x 8 bits EFFFH 1000H0FFFH 0800H07FFH 0080H 007FH 0040H003FH 0000H CALLF Entry Area CALLT Table Area Vector Table Area Program Area Program Area Internal Buffer RAM 32 x 8 bits Reserved Note Progra...
Page 103 - by the internal memory size switching register.
103 CHAPTER 5 CPU ARCHITECTURE 0000H Data memory space General Registers 32 x 8 bits Internal PROM 61440 x 8 bits EFFFH 1000H0FFFH 0800H07FFH 0080H 007FH 0040H003FH 0000H CALLF Entry Area CALLT Table Area Vector Table Area Program Area Program Area Internal Buffer RAM 32 x 8 bits Reserved Programmem...
Page 104 - The internal program memory space
104 CHAPTER 5 CPU ARCHITECTURE 5.1.1 Internal program memory space The internal program memory space stores programs and table data. This is generally accessed by the program counter (PC). The µ PD78078 and 78078Y Subseries have various size of internal ROMs or PROM as shown below. Table 5-1. Intern...
Page 106 - Caution Do not access addresses where the SFR is not assigned.
106 CHAPTER 5 CPU ARCHITECTURE 5.1.2 Internal data memory space The µ PD78078 and 78078Y Subseries units incorporate the following RAMs. (1) Internal high-speed RAM This is a 1024 x 8-bit configuration in the area FB00H to FEFFH 4 banks of general registers, each bank consisting of eight 8-bit regis...
Page 107 - For details of addressing, refer to 5.4 Operand Address Addressing.
107 CHAPTER 5 CPU ARCHITECTURE 0000H General Registers 32 x 8 bits Internal ROM 49152 x 8 bits Internal Buffer RAM 32 x 8 bits External Memory 13312 x 8 bits Reserved C000HBFFFH F800HF7FFH FAC0HFABFH FAE0HFADFH FEE0HFEDFH FF00HFEFFH FFFFH Internal High-speed RAM 1024 x 8 bits Reserved FB00HFAFFH F40...
Page 110 - Processor Registers; Figure 5-7. Program Counter Configuration; RESET input sets the PSW to 02H.; Figure 5-8. Program Status Word Configuration
110 CHAPTER 5 CPU ARCHITECTURE 7 0 IE PSW Z RBS1 AC RBS0 0 ISP CY PC 15 0 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 5.2 Processor Registers The µ PD78078 and 78078Y Subseries units incorporate the following processor registers. 5.2.1 Control registers The control register...
Page 111 - These are 2-bit flags to select one of the four register banks.
111 CHAPTER 5 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When IE = 0, the IE is set to interrupt disabled (DI) status. All interrupts except non-maskable interrupt are disabled. When IE = 1, the IE is set to interrupt e...
Page 112 - area can be set as the stack area.; instruction execution.
112 CHAPTER 5 CPU ARCHITECTURE SP 15 0 SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 5-9. Stack Poin...
Page 113 - processing and a register for interruption for each bank.; Figure 5-12. General Register Configuration; FEFFH
113 CHAPTER 5 CPU ARCHITECTURE 5.2.2 General registers A general register is mapped at particular addresses (FEE0H to FEFFH) of the data memory. It consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can also be used as an 8-bit register. Tw...
Page 114 - • 16-bit manipulation
114 CHAPTER 5 CPU ARCHITECTURE 5.2.3 Special function register (SFR) Unlike a general register, each special function register has special functions. It is allocated in the FF00H to FFFFH area. The special function registers can be manipulated in a similar way as the general registers, by using oper...
Page 117 - unless external device expansion function is used with the
117 CHAPTER 5 CPU ARCHITECTURE Address Special Function Register (SFR) Name Symbol R/W After Reset FF74H Transmit shift register TXS SIO2 W — √ — FFH Receive buffer register RXB R FF80H A/D converter mode register ADM R/W √ √ — 01H FF84H A/D converter input select register ADIS — √ — 00H FF8AH Corre...
Page 118 - PC; Instruction Address Addressing; instruction is executed.
118 CHAPTER 5 CPU ARCHITECTURE 15 0 PC + 15 0 8 7 6 S 15 0 PC α jdisp8 When S = 0, all bits of α are 0. When S = 1, all bits of α are 1. PC indicates the start addressof the instructionafter the BR instruction. ... 5.3 Instruction Address Addressing An instruction address is determined by program co...
Page 119 - CALLF !addr11 instruction branches to the area from 0800H to 0FFFH.
119 CHAPTER 5 CPU ARCHITECTURE 5.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 ...
Page 121 - rp
121 CHAPTER 5 CPU ARCHITECTURE 5.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration] 7 0 rp 0 7 A X 15 0 P...
Page 122 - Operand Address Addressing; during instruction execution.
122 CHAPTER 5 CPU ARCHITECTURE 5.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 5.4.1 Implied addressing [Function] The register which functions as an accumulator (A and AX) in ...
Page 123 - Identifier; MOV A, C when selecting C register as r; Register specify code
123 CHAPTER 5 CPU ARCHITECTURE 0 1 1 0 0 0 1 0 Register specify code Operation code 5.4.2 Register addressing [Function] The general register is accessed as an operand. The general register to be accessed is specified with register bank select flags (RBS0 and RBS1) and register specify code (Rn, RPn...
Page 124 - Operation code
124 CHAPTER 5 CPU ARCHITECTURE 5.4.3 Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed. [Operand format] Identifier Description addr16 Label or 16-bit immediate data [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Ope...
Page 131 - CHAPTER 6 PORT FUNCTIONS
131 CHAPTER 6 PORT FUNCTIONS 6.1 Port Functions The µ PD78078 and 78078Y Subseries units incorporate two input ports and eighty-six input/output ports. Figure 6-1 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operat...
Page 136 - Port Configuration; A port consists of the following hardware:; Item; Port; for subsystem clock oscillation.; the output mode is used, set the interrupt mask flag to 1.
136 CHAPTER 6 PORT FUNCTIONS 6.2 Port Configuration A port consists of the following hardware: Table 6-3. Port Configuration Item Configuration Control register Port mode register (PMm: m = 0 to 3, 5 to 10, 12, 13) Pull-up resistor option register (PUOH, PUOL) Memory expansion mode register (MM) Not...
Page 137 - Figure 6-2. Block Diagram of P00 and P07; Internal bus
137 CHAPTER 6 PORT FUNCTIONS Figure 6-2. Block Diagram of P00 and P07 Figure 6-3. Block Diagram of P01 to P06 PUO : Pull-up resistor option register PM : Port mode register RD : Port 0 read signal WR : Port 0 write signal P00/INTP0/TI00,P07/XT1 RD Internal bus P-ch WR PM WR PORT RD WR PUO V DD P01/I...
Page 138 - WR; RD; Selector
138 CHAPTER 6 PORT FUNCTIONS 6.2.2 Port 1 Port 1 is an 8-bit input/output port with output latch. It can specify the input mode/output mode in 1-bit units with a port mode register 1 (PM1). When P10 to P17 pins are used as input ports, an on-chip pull-up resistor can be connected to them in 8-bit un...
Page 139 - Format and Figure 19-3. Serial Operating Mode Register 1 Format.
139 CHAPTER 6 PORT FUNCTIONS P-ch WR PM WR PORT RD WR PUO V DD Selector PUO2 Output Latch(P20, P21, P23 to P26) PM20, PM21PM23 to PM26 Internal bus Dual Function P20/SI1,P21/SO1,P23/STB,P24/BUSY,P25/SI0/SB0,P26/SO0/SB1 6.2.3 Port 2 ( µ PD78078 Subseries) Port 2 is an 8-bit input/output port with out...
Page 140 - Figure 6-6. Block Diagram of P22 and P27
140 CHAPTER 6 PORT FUNCTIONS P-ch WR PM WR PORT RD WR PUO V DD Selector PUO2 Output Latch(P20, P21, P23 to P26) PM20, PM21PM23 to PM26 Internal bus Dual Function P20/SI1,P21/SO1,P23/STB,P24/BUSY,P25/SI0/SB0/SDA0,P26/SO0/SB1/SDA1 Figure 6-6. Block Diagram of P22 and P27 PUO : Pull-up resistor option ...
Page 142 - Figure 6-8. Block Diagram of P22 and P27
142 CHAPTER 6 PORT FUNCTIONS P-ch WR PM WR PORT RD WR PUO V DD Selector PUO2 Output Latch(P22, P27) PM22, PM27 Internal bus Dual Function P22/SCK1,P27/SCK0/SCL Figure 6-8. Block Diagram of P22 and P27 PUO : Pull-up resistor option register PM : Port mode register RD : Port 2 read signal WR : Port 2 ...
Page 144 - Figure 6-11. Block Diagram of Falling Edge Detection Circuit
144 CHAPTER 6 PORT FUNCTIONS 6.2.6 Port 4 Port 4 is an 8-bit input/output port with output latch. P40 to P47 pins can specify the input mode/output mode in 8-bit units with the memory expansion mode register (MM). When P40 to P47 pins are used as input ports, an on- chip pull-up resistor can be conn...
Page 146 - on the port pin and the device version.; Mask ROM version; Pins P60 to P63 can drive LEDs directly.; each of these pins depends on the following conditions:
146 CHAPTER 6 PORT FUNCTIONS 6.2.8 Port 6 Port 6 is an 8-bit input/output port with output latch. P60 to P67 pins can specify the input mode/output mode in 1-bit units with the port mode register 6 (PM6). This port has pull-up resistor options as shown below. However, the option specification method...
Page 151 - Pins P90 to P93 can drive LEDs directly.; of these pins depends on the following conditions:
151 CHAPTER 6 PORT FUNCTIONS 6.2.11 Port 9 Port 9 is an 7-bit input/output port with output latch. P90 to P96 pins can specify the input mode/output mode in 1-bit units with the port mode register 9 (PM9). This port has pull-up resistor options as shown below. However, the option specification metho...
Page 156 - pins that are not used as analog outputs must be set as follows:
156 CHAPTER 6 PORT FUNCTIONS 6.2.14 Port 13 This is a 2-bit input/output port with output latches. Input mode/output mode can be specified in 1-bit units with the port mode register 13 (PM13). When pins P130 and P131 are used as input port pins, an on-chip pull-up resistor can be connected in 2-bit ...
Page 157 - Port Function Control Registers; The following four types of registers control the ports.; be set to 1 beforehand.
157 CHAPTER 6 PORT FUNCTIONS 6.3 Port Function Control Registers The following four types of registers control the ports. • Port mode registers (PM0 to PM3, PM5 to PM10, PM12, PM13) • Pull-up resistor option register (PUOH, PUOL) • Memory expansion mode register (MM) • Key return mode register (KRM)...
Page 158 - set the function with the memory extension mode register (MM).; Remarks x; PMxx : Port mode register
158 CHAPTER 6 PORT FUNCTIONS P00 INTP0 Input 1 (Fixed) None P50 to P57 A8 to A15 Output x Note 2 TI00 Input 1 (Fixed) None P64 RD Output x Note 2 P01 INTP1 Input 1 x P65 WR Output x Note 2 TI01 Input 1 x P66 WAIT Input x Note 2 P02 to P06 INTP2 to INTP6 Input 1 x P67 ASTB Output x Note 2 P07 Note 1 ...
Page 160 - RESET input sets this register to 00H.; Cautions 1. P00 and P07 pins do not incorporate a pull-up resistor.
160 CHAPTER 6 PORT FUNCTIONS (2) Pull-up resistor option register (PUOH, PUOL) This register is used to set whether to use an internal pull-up resistor at each port or not. A pull-up resistor is internally used at bits which are set to the input mode at a port where on-chip pull-up resistor use has ...
Page 161 - This register is used to set input/output of port 4.; Figure 6-26. Memory Expansion Mode Register Format; device is switched to the multiplexed bus mode.
161 CHAPTER 6 PORT FUNCTIONS (3) Memory expansion mode register (MM) This register is used to set input/output of port 4. MM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 10H. Figure 6-26. Memory Expansion Mode Register Format Notes 1. These pins can...
Page 162 - KRM is set with a 1-bit or 8-bit memory manipulation instruction.; Figure 6-27. Key Return Mode Register Format
162 CHAPTER 6 PORT FUNCTIONS (4) Key return mode register (KRM) This register sets enabling/disabling of standby function release by a key return signal (falling edge detection of port 4). KRM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets KRM to 02H. Figure 6-27. Key...
Page 163 - Port Function Operations; output latch contents are output from the pins.; than the manipulated bit.
163 CHAPTER 6 PORT FUNCTIONS 6.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 6.4.1 Writing to input/output port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents ar...
Page 164 - Selection of Mask Option; The following mask option is provided in mask ROM version. The; Table 6-7. Comparison between Mask ROM Version and the; Pin Name
164 CHAPTER 6 PORT FUNCTIONS 6.5 Selection of Mask Option The following mask option is provided in mask ROM version. The µ PD78P078 and 78P078Y have no mask option. Table 6-7. Comparison between Mask ROM Version and the µ PD78P078 and 78P078Y Pin Name Mask ROM Version µ PD78P078 and 78P078Y Mask opt...
Page 165 - types of system clock oscillators are available.
165 CHAPTER 7 CLOCK GENERATOR 7.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are available. (1) Main system clock oscillator This circuit oscillates at frequencies of 1 to 5....
Page 166 - CHAPTER 7 CLOCK GENERATOR; Clock Generator Configuration; The clock generator consists of the following hardware.; Table 7-1. Clock Generator Configuration
166 CHAPTER 7 CLOCK GENERATOR Subsystem Clock Oscillator Main SystemClock Oscillator X2 X1 XT2 XT1/P07 FRC STOP MCC FRC CLS CSS PCC2 PCC1 Internal Bus Standby Control Circuit To INTP0 Sampling Clock 2 f XX 2 2 f XX 2 3 f XX 2 4 f XX Prescaler Clock to PeripheralHardware Prescaler Oscillation Mode Se...
Page 167 - Clock Generator Control Register; The clock generator is controlled by the following two registers:; Figure 7-2. Subsystem Clock Feedback Resistor
167 CHAPTER 7 CLOCK GENERATOR 7.3 Clock Generator Control Register The clock generator is controlled by the following two registers: • Processor clock control register (PCC) • Oscillation mode selection register (OSMS) (1) Processor clock control register (PCC) The PCC selects a CPU clock and the di...
Page 168 - Figure 7-3. Processor Clock Control Register Format; system clock oscillation. A STOP instruction should not be used.; Caution Bit 3 must be set to 0.; or f; : Subsystem clock oscillation frequency
168 CHAPTER 7 CLOCK GENERATOR MCC FRC CLS CSS PCC2 PCC1 PCC0 PCC CLS 0 1 Main system clock Subsystem clock FFFBH 04H <7> <6> <5> <4> Symbol Address After Reset R/W R/W Note 1 0 3 2 0 1 CSS 0 0 f XX /2 PCC2 CPU CIock (f CPU ) Selection PCC1 PCC0 CPU Clock Status 0 0 0 1 0 0 1 ...
Page 169 - The fastest instruction of the; ) and the minimum instruction execution time is shown in Table 7-2.; : Main system clock oscillation frequency; : Subsystem clock oscillation frequency
169 CHAPTER 7 CLOCK GENERATOR The fastest instruction of the µ PD78078 and 78078Y Subseries can be executed in two clocks of the CPU clock. The relationship between the CPU clock (f CPU ) and the minimum instruction execution time is shown in Table 7-2. Table 7-2. Relationship between CPU Clock and ...
Page 170 - OSMS is set with 8-bit memory manipulation instruction.; fx
170 CHAPTER 7 CLOCK GENERATOR (2) Oscillation mode selection register (OSMS) This register specifies whether the clock output from the main system clock oscillator without passing through the scaler is used as the main system clock, or the clock output via the scaler is used as the main system clock...
Page 171 - System Clock Oscillator; connected to the X1 and X2 pins.; Figure 7-6. External Circuit of Main System Clock Oscillator; when a STOP instruction is executed and MCC is set
171 CHAPTER 7 CLOCK GENERATOR 7.4 System Clock Oscillator 7.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 5.0 MHz) connected to the X1 and X2 pins. External clocks can be input to the main system clock oscillat...
Page 172 - and an antiphase clock signal to the XT2 pin.; resistors in series on the side of XT2.
172 CHAPTER 7 CLOCK GENERATOR 7.4.2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 and XT2 pins. External clocks can be input to the subsystem clock oscillator. In this case, input a clock signal to the XT1 pi...
Page 173 - resistors in series on the XT2 side.
173 CHAPTER 7 CLOCK GENERATOR Figure 7-8. Examples of Oscillator with Bad Connection (2/2) (c) Changing high current is too near a (d) Current flows through the grounding line signal conductor of the oscillator (potential at points A, B, and C fluctuate) (e) Signals are fetched (f) Signal conductors...
Page 174 - connect the XT1 and XT2 pins as follows.
174 CHAPTER 7 CLOCK GENERATOR 7.4.3 Divider The divider generates various clocks by dividing the main system clock oscillator output (f XX ). 7.4.4 When no subsystem clocks are used If it is not necessary to use subsystem clocks for low power consumption operations and clock operations, connect the ...
Page 175 - Clock Generator Operations
175 CHAPTER 7 CLOCK GENERATOR 7.5 Clock Generator Operations The clock generator generates the following various types of clocks and controls the CPU operating mode including the standby mode. • Main system clock f XX • Subsystem clock f XT • CPU clock f CPU • Clock to peripheral hardware The follow...
Page 176 - (b) Operation when MCC is set in case of main system clock operation
176 CHAPTER 7 CLOCK GENERATOR 7.5.1 Main system clock operations When operated with the main system clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 0), the following operations are carried out by PCC setting. (a) Because the operation guarantee instruction execution spee...
Page 177 - the following operations are carried out.
177 CHAPTER 7 CLOCK GENERATOR Figure 7-9. Main System Clock Stop Function (2/2) (c) Operation when CSS is set after setting MCC with main system clock operation 7.5.2 Subsystem clock operations When operated with the subsystem clock (with bit 5 (CLS) of the processor clock control register (PCC) set...
Page 178 - Changing System Clock and CPU Clock Settings; Table 7-3. Maximum Time Required for CPU Clock Switchover
178 CHAPTER 7 CLOCK GENERATOR 7.6 Changing System Clock and CPU Clock Settings 7.6.1 Time required for switchover between system clock and CPU clock The system clock and CPU clock can be switched over by means of bit 0 to bit 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (...
Page 179 - System clock and CPU clock switching procedure
179 CHAPTER 7 CLOCK GENERATOR 7.6.2 System clock and CPU clock switching procedure This section describes switching procedure between system clock and CPU clock. Figure 7-10. System Clock and CPU Clock Switching (1) The CPU is reset by setting the RESET signal to low level after power-on. After that...
Page 181 - Outline of Timers Incorporated into; Subseries and the related circuits are outlined below.
181 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.1 Outline of Timers Incorporated into µ PD78078, 78078Y Subseries This chapter explains the 16-bit timer/event counter. First of all, the timers incorporated into the µ PD78078, 78078Y Subseries and the related circuits are outlined below. (1) 16-bit timer/...
Page 183 - Figures in parentheses apply to operation with f
183 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.2 16-Bit Timer/Event Counter Functions The 16-bit timer/event counter (TM0) has the following functions. • Interval timer • PWM output • Pulse width measurement • External event counter • Square-wave output • One-shot pulse output TM0 can perform both PWM o...
Page 184 - Figures in parentheses operation with f
184 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (5) Square-wave output TM0 can output a square wave with any selected frequency. Table 8-3. 16-Bit Timer/Event Counter Square-Wave Output Ranges Minimum Pulse Width Maximum Pulse Width Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 2 x TI00 input ...
Page 185 - The 16-bit timer/event counter consists of the following hardware.
185 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.3 16-Bit Timer/Event Counter Configuration The 16-bit timer/event counter consists of the following hardware. Table 8-4. 16-Bit Timer/Event Counter Configuration Item Configuration Timer register 16 bits x 1 (TM0) Register Capture/compare register: 16 bits ...
Page 186 - Notes 1. Edge detection circuit
186 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-1. 16-Bit Timer/Event Counter Block Diagram Notes 1. Edge detection circuit 2. The configuration of the 16-bit timer/event counter output control circuit is shown in Figure 8-2. Internal bus Capture/CompareControl Register 0 CRC02 CRC01 CRC00 Selecto...
Page 188 - count operation cannot be executed.; CR01 is set with a 16-bit memory manipulation instruction.; by the detection of a valid edge.
188 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (1) Capture/compare register 00 (CR00) CR00 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register or as a compare register is set by bit 0 (CRC00) of capture/compare control re...
Page 189 - TM0 is a 16-bit register which counts the count pulses.
189 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (3) 16-bit timer register (TM0) TM0 is a 16-bit register which counts the count pulses. TM0 is read by a 16-bit memory manipulation instruction. When TM0 is read, capture/compare register (CR01) should first be set as a capture register. RESET input sets TM0 ...
Page 192 - Remarks; Figures in parentheses apply to operation with f
192 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscillation frequency 3. f XT : Subsystem clock oscillation frequency 4. TI00 : 16-bit timer/event counter input pin 5. TM0 : 16-bit timer register 6. MCS : Bit 0 of osci...
Page 193 - CRC0 is set with a 1-bit or 8-bit memory manipulation instruction.; Cautions 1. Timer operation must be stopped before setting CRC0.
193 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Cautions 1. Switch the clear mode and the T00 output timing after stopping the timer operation (by setting TMC01 to TMC03 to 0, 0, 0). 2. Set the valid edge of the TI00/INTP0 pin with an external interrupt mode register 0 (INTM0) and select the sampling clock...
Page 194 - If LVS0 and LVR0 are read after data is set, they will be 0.
194 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (4) 16-bit timer output control register (TOC0) This register controls the operation of the 16-bit timer/event counter output control circuit. It sets R-S type flip-flop (LV0) setting/resetting, the active level in PWM mode, inversion enabling/disabling in mo...
Page 196 - Figure 8-8. External Interrupt Mode Register 0 Format
196 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (6) External interrupt mode register 0 (INTM0) This register is used to set INTP0 to INTP2 valid edges. INTM0 is set with an 8-bit memory manipulation instruction. RESET input sets INTM0 value to 00H. Figure 8-8. External Interrupt Mode Register 0 Format Caut...
Page 198 - the description of the respective control registers for details.; Clear & start on match TM0 and CR00
198 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5 16-Bit Timer/Event Counter Operations 8.5.1 Interval timer operations Setting the 16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 8-10 allows operation as an interval timer. Interrupt requests are...
Page 200 - Figures in parentheses apply to operation with f; and the
200 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Table 8-6. 16-Bit Timer/Event Counter Interval Times Minimum Interval Time Maximum Interval Time Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 0 0 0 2 x TI00 input cycle 2 16 x TI00 input cycle TI00 input edge cycle 0 0 1 Setting 2 x 1/f X Settin...
Page 201 - PWM mode
201 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-13. Control Register Settings for PWM Output Operation (a) 16-bit timer mode control register (TMC0) (b) Capture/compare control register 0 (CRC0) (c) 16-bit timer output control register (TOC0) Remark 0/1 : Setting 0 or 1 allows another function to ...
Page 202 - The analog output voltage (V; : External switching circuit reference voltage; Figure 8-14. Example of D/A Converter Configuration with PWM Output; synthesizer type TV tuner.; Figure 8-15. TV Tuner Application Circuit Example
202 CHAPTER 8 16-BIT TIMER/EVENT COUNTER By integrating 14-bit resolution PWM pulses with an external low-pass filter, they can be converted to an analog voltage and used for electronic tuning and D/A converter applications, etc. The analog output voltage (V AN ) used for D/A conversion with the con...
Page 204 - Pulse width measurement operations; thus eliminating noise with a short pulse width.; Free-Running Counter and One Capture Register
204 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.4 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI00/P00 pin and TI01/P01 pin using the bit timer register (TM0). There are two measurement methods: measuring with TM0 used in free-running mode, a...
Page 205 - and One Capture Register (with Both Edges Specified); Count Clock
205 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-18. Configuration Diagram for Pulse Width Measurement by Free-Running Counter Figure 8-19. Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture Register (with Both Edges Specified) Count Clock TM0 Count Value TI00 Pin I...
Page 206 - detected twice, thus eliminating noise with a short pulse width.; CR00 set as capture register
206 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (2) Two pulse width measurements with free-running counter When the 16-bit timer register (TM0) is operated in free-running mode (see register settings in Figure 8- 20), it is possible to simultaneously measure the pulse widths of the two signals input to the...
Page 207 - Figure 8-21. Timing of Pulse Width Measurement Operation with
207 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-21. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) Count Clock TM0 Count Value TI00 Pin Input CR01 Captured Value INTP0 TI01 Pin Input t CR00 Captured Value INTP1 OVF0 (D1 – D0) x t (10000H – D1 + D2...
Page 208 - Free-Running Counter and Two Capture Registers
208 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (3) Pulse width measurement with free-running counter and two capture registers When the 16-bit timer register (TM0) is operated in free-running mode (see register settings in Figure 8-22), it is possible to measure the pulse width of the signal input to the ...
Page 209 - Counter and Two Capture Registers (with Rising Edge Specified)
209 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-23. Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified) Count Clock TM0 Count Value TI00 Pin Input CR01 Captured Value CR00 Captured Value INTP0 OVF0 (D1 – D0) x t (10000H – D1 + ...
Page 210 - (4) Pulse width measurement by means of restart; pulse width noise to be eliminated.
210 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (4) Pulse width measurement by means of restart When input of a valid edge to the TI00/P00 pin is detected, the count value of the 16-bit timer register (TM0) is taken into 16-bit capture/compare register 01 (CR01), and then the pulse width of the signal inpu...
Page 211 - Clear & start with match of TM0 and CR00
211 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.5 External event counter operation The external event counter counts the number of external clock pulses to be input to the TI00/P00 pin with the 16-bit timer register (TM0). TM0 is incremented each time the valid edge specified with the external interrup...
Page 212 - Figure 8-27. External Event Counter Configuration Diagram; Clear
212 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-27. External Event Counter Configuration Diagram Figure 8-28. External Event Counter Operation Timings (with Rising Edge Specified) Caution When reading the external event counter count value, TM0 should be read. 16-Bit Capture/Compare Register 00 (C...
Page 213 - frequency to be output.; Figure 8-29. Control Register Settings in Square-Wave Output Mode; One-shot pulse output disabled
213 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.6 Square-wave output operation 16-bit timer/event counter operates as a square wave output with any selected frequency at intervals of the count value preset to the 16-bit capture/compare register 00 (CR00). The TO0/P30 pin output status is reversed at in...
Page 217 - the TO0/P30 pin with a TI00/P00 valid edge as an external trigger.; FFFFH
217 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (2) One-shot pulse output using external trigger If the 16-bit timer mode control register (TMC0), capture/compare control register 0 (CRC0), and the 16- bit timer output control register (TOC0) are set as shown in Figure 8-33, a one-shot pulse is output from...
Page 220 - (4) Capture register data retention timings; detection of the valid edge.; Figure 8-37. Capture Register Data Retention Timing
220 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (4) Capture register data retention timings If the valid edge of the TI00/P00 pin is input during 16-bit capture/compare register 01 (CR01) read, CR01 holds data without carrying out capture operation. However, the interrupt request flag (PIF0) is set upon de...
Page 221 - Figure 8-38. Operation Timing of OVF0 Flag
221 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (7) Operation of OVF0 flag OFV0 flag is set to 1 in the following case. The clear & start mode on match between TM0 and CR00 is selected. ↓ CR00 is set to FFFFH. ↓ When TM0 is counted up from FFFFH to 0000H. Figure 8-38. Operation Timing of OVF0 Flag Coun...
Page 223 - CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2; • Interval timer
223 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.1 8-Bit Timer/Event Counters 1 and 2 Functions For the 8-bit timer/event counters 1 and 2, two modes are available. One is a mode for two-channel 8-bit timer/ event counters to be used separately (the 8-bit timer/event counter mode) and the other is...
Page 224 - Interrupt requests are generated at the preset time intervals.
224 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (1) 8-bit interval timer Interrupt requests are generated at the preset time intervals. Table 9-1. 8-Bit Timer/Event Counters 1 and 2 Interval Times Minimum Interval Time Maximum Interval Time Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0...
Page 226 - Interrupt requests can be generated at the preset time intervals.
226 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.1.2 16-bit timer/event counter mode (1) 16-bit interval timer Interrupt requests can be generated at the preset time intervals. Table 9-3. Interval Times when 8-Bit Timer/Event Counters 1 and 2 are Used as 16-Bit Timer/Event Counters Minimum Interva...
Page 227 - Figures in parentheses apply to operation with at f
227 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 9-4. Square-Wave Output Ranges when 8-Bit Timer/Event Counters 1 and 2...
Page 229 - The section in the broken line is an output control circuit.; : Serial clock frequency
229 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Figure 9-2. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1 Remark The section in the broken line is an output control circuit. Figure 9-3. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 2 Remarks 1. The section ...
Page 230 - FFFFH values can be set.; stopping timer operation.; These are 8-bit registers to count count pulses.
230 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (1) Compare registers 10 and 20 (CR10, CR20) These are 8-bit registers to compare the value set to CR10 to the 8-bit timer register 1 (TM1) count value, and the value set to CR20 to the 8-bit timer register 2 (TM2) count value, and, if they match, gen...
Page 231 - This register sets count clocks of 8-bit timer registers 1 and 2.
231 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.3 8-Bit Timer/Event Counters 1 and 2 Control Registers The following four types of registers are used to control the 8-bit timer/event counter. • Timer clock select register 1 (TCL1) • 8-bit timer mode control register 1 (TMC1) • 8-bit timer output ...
Page 232 - Figure 9-4. Timer Clock Select Register 1 Format; Figures in parentheses apply to operation with f
232 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 TCL13 TCL12 TCL11 TCL10 0 0 0 0 TI1 falling edge 0 0 0 1 TI1 rising edge 0 1 1 0 0 1 1 1 f XX /2 f X /2 (2.5 MHz) f X /2 2 (1.25 MHz) 1 0 0 0 f XX /2 2 f X /2 2 (1.25 MHz) f X /2 3 (625 kHz) 1 0 0 1 f XX /2 3 f X /2 3 (625 kHz) f X /2 4 (313 kHz) 1 0 ...
Page 233 - TMC1 is set with a 1-bit or 8-bit memory manipulation instruction.
233 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) 8-bit timer mode control register 1 (TMC1) This register enables/stops operation of 8-bit timer registers 1 and 2 and sets the operating mode of 8-bit timer register 2. TMC1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input...
Page 234 - bit timer registers 1 and 2.; Cautions 1. Stop the timer operation before setting TOC1.
234 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (3) 8-bit timer output control register (TOC1) This register controls operation of 8-bit timer/event counter output control circuits 1 and 2. It sets/resets the R-S flip-flops (LV1 and LV2) and enables/disables inversion and 8-bit timer output of 8- b...
Page 235 - PM3 is set with a 1-bit or 8-bit memory manipulation instruction.
235 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (4) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P31/TO1 and P32/TO2 pins for timer output, set PM31, PM32, and output latches of P31 and P32 to 0. PM3 is set with a 1-bit or 8-bit memory manipulatio...
Page 236 - Figure 9-8. Interval Timer Operation Timing
236 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.4 8-Bit Timer/Event Counters 1 and 2 Operations 9.4.1 8-bit timer/event counter mode (1) Interval timer operations The 8-bit timer/event counters 1 and 2 operate as interval timers which generate interrupt requests repeatedly at intervals of the cou...
Page 239 - is input. Either the rising or falling edge can be selected.; TI1 Pin Input
239 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (2) External event counter operation The external event counter counts the number of external clock pulses to be input to the TI1/P33 and TI2/ P34 pins with 8-bit timer registers 1 and 2 (TM1 and TM2). TM1 and TM2 are incremented each time the valid e...
Page 240 - a square wave with any selected frequency to be output.
240 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (3) Square-wave output Operation 8-bit timer/event counters 1 and 2 operate as a square wave outputs with any selected frequency at intervals of the value preset to 8-bit compare registers 10 and 20 (CR10 and CR20). The TO1/P31 or TO2/P32 pin output s...
Page 241 - Figure 9-10. Timing of Square Wave Output Operation
241 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Figure 9-10. Timing of Square Wave Output Operation Note The initial value of the TO1 output can be set by bits 2 and 3 (LVS1 and LVR1) of the 8-bit timer output control register (TOC1). Count Clock TM1 Count Value 01 02 00 N–1 N 00 01 02 N–1 N 00 Cou...
Page 242 - Figure 9-11. Interval Timer Operation Timing
242 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Count Clock TMS (TM1, TM2) Count Value CR10, CR20 INTTM2 TO2 Interval Time Interval Time Interval Time Interrupt RequestAcknowledge Interrupt RequestAcknowledge N N N N Count Start Clear Clear 0000 0001 N 0000 0001 N 0000 0001 N t 9.4.2 16-bit timer/e...
Page 243 - Figures in parentheses apply to operation with at f
243 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 Table 9-9. Interval Times when 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2) are Used as 16-Bit Timer/Event Counter Minimum Interval Time Maximum Interval Time Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 0 0 0 0 TI1 input cycle 2 8...
Page 245 - selected frequency to be output.
245 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 (3) Square-wave output operation The 8-bit timer/event counters 1 and 2 operate as square wave outputs with any selected frequency at intervals of the value preset to 8-bit compare registers (CR10 and CR20). To set the count value, set the values of t...
Page 246 - with the count pulse.; Figure 9-14. External Event Counter Operation Timing
246 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 9.5 8-Bit Timer/Event Counters 1 and 2 Precautions (1) Timer start errors An error with a maximum of one clock may occur concerning the time required for a match signal to be gener- ated after timer start. This is because 8-bit timer registers 1 and 2...
Page 249 - CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6
249 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 10.1 8-Bit Timer/Event Counters 5 and 6 Functions The 8-bit timer event counters 5 and 6 (TM5, TM6) have the following functions. • Interval timer • External event counter • Square-wave output • PWM output
Page 253 - memory manipulation instruction. The 00H to FFH values can be set.
253 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 Figure 10-2. Block Diagram of 8-Bit Timer/Event Counters 5 and 6 Output Control Circuit Remarks 1. The section in the broken line is an output control circuit. 2. n = 5, 6 (1) Compare register 50 and 60 (CR50, 60) These 8-bit registers compare the va...
Page 254 - This register sets count clocks of 8-bit timer register 5.; Figure 10-3. Timer Clock Select Register 5 Format; Figures in parentheses apply to operation with f
254 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 10.3 8-Bit Timer/Event Counters 5 and 6 Control Registers The following three types of registers are used to control the 8-bit timer/event counters 5 and 6. • Timer clock select register 5 and 6 (TCL5, TCL6) • 8-bit timer mode control registers 5 and...
Page 255 - This register sets count clocks of 8-bit timer register 6.; Figure 10-4. Timer Clock Select Register 6 Format
255 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (2) Timer clock select register 6 (TCL6) This register sets count clocks of 8-bit timer register 6. TCL6 is set with an 8-bit memory manipulation instruction. RESET input sets TCL6 to 00H. Figure 10-4. Timer Clock Select Register 6 Format Note When c...
Page 256 - TMC5 is set with a 1-bit or 8-bit memory manipulation instruction.; Cautions 1. Timer operation must be stopped before setting TMC5.
256 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (3) 8-bit timer mode control register 5 (TMC5) This register enables/stops operation of 8-bit timer register 5, sets the operating mode of 8-bit timer register 5 and controls operation of 8-bit timer/event counter 5 output control circuit. It sets R-...
Page 257 - TMC6 is set with a 1-bit or 8-bit memory manipulation instruction.; Cautions 1. Timer operation must be stopped before setting TMC6.
257 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (4) 8-bit timer mode control register 6 (TMC6) This register enables/stops operation of 8-bit timer register 6, sets the operating mode of 8-bit timer register 6 and controls operation of 8-bit timer/event counter 6 output control circuit. It sets R-...
Page 258 - PM10 is set with a 1-bit or 8-bit memory manipulation instruction.; Figure 10-7. Port Mode Register 10 Format
258 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (5) Port mode register 10 (PM10) This register sets port 10 input/output in 1-bit units. When using the P100/TI5/TO5 and P101/TI6/TO6 pins for timer output, set PM100, PM101 and output latches of P100 and P101 to 0. PM10 is set with a 1-bit or 8-bit ...
Page 259 - Figure 10-9. Interval Timer Operation Timings
259 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 10.4 8-Bit Timer/Event Counters 5 and 6 Operations 10.4.1 Interval timer operations Setting the 8-bit timer mode control registers (TMC5 and TMC6) as shown in Figure 10-8 allows operation as an interval timer. Interrupt requests are generated repeate...
Page 261 - and TCL6) is input. Either rising or falling edge can be selected.
261 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 10.4.2 External event counter operation The external event counter counts the number of external clock pulses to be input to the TI5/P100/TO5 and TI6/ P101/TO6 pins with 8-bit timer registers 5 and 6 (TM5 and TM6). TM5 and TM6 are incremented each ti...
Page 262 - This enables a square wave of any selected frequency to be output.
262 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 10.4.3 Square-wave output A square wave with any selected frequency is output at intervals of the value preset to 8-bit compare registers (CR50 and CR60). The TO5/P100/TI5 or TO6/P101/TI6 pin output status is reversed at intervals of the count value ...
Page 263 - Minimum Pulse Time
263 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 Table 10-5. 8-Bit Timer/Event Counters 5 and 6 Square-Wave Output Ranges Minimum Pulse Time Maximum Pulse Time Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 — 1/f X — 2 8 x 1/f X — 1/f X (200 ns) (51.2 µ s) (200 ns) 1/f X 2 x 1/f X 2 8 x...
Page 267 - Figure 10-20. External Event Counter Operation Timings
267 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 10.5 8-Bit Timer/Event Counters 5 and 6 Precautions (1) Timer start errors An error with a maximum of one clock might occur concerning the time required for a match signal to be generated after the timer starts. This is because 8-bit timer registers ...
Page 268 - to restart the timer after changing CR50 and CR60.
268 CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6 Count Pulse CR50, CR60 N X X – 1 FFH 00H 01H M 02H TM5, TM6 Count Value (3) Operation after compare register change during timer count operation If the values after the 8-bit compare registers (CR50 and CR60) are changed are smaller than those of 8- ...
Page 269 - Table 11-1. Interval Timer Interval Time
269 CHAPTER 11 WATCH TIMER 11.1 Watch Timer Functions The watch timer has the following functions. • Watch timer • Interval timer The watch timer and the interval timer can be used simultaneously. (1) Watch timer When the 32.768-kHz subsystem clock is used, a flag (WTIF) is set at 0.5-second or 0.25...
Page 270 - CHAPTER 11 WATCH TIMER; Watch Timer Configuration; The watch timer consists of the following hardware.
270 CHAPTER 11 WATCH TIMER 11.2 Watch Timer Configuration The watch timer consists of the following hardware. Table 11-2. Watch Timer Configuration Item Configuration Counter 5 bits x 1 Timer clock select register 2 (TCL2) Watch timer mode control register (TMC2) Control register
Page 271 - Watch Timer Control Registers; • Watch timer mode control register (TMC2)
271 CHAPTER 11 WATCH TIMER 11.3 Watch Timer Control Registers The following two types of registers are used to control the watch timer. • Timer clock select register 2 (TCL2) • Watch timer mode control register (TMC2) (1) Timer clock select register 2 (TCL2) This register sets the watch timer count ...
Page 272 - Figure 11-2. Timer Clock Select Register 2 Format
272 CHAPTER 11 WATCH TIMER Figure 11-2. Timer Clock Select Register 2 Format Caution When rewriting TCL2 to other data, stop the timer operation beforehand. Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscillation frequency 3. f XT : Subsystem clock oscill...
Page 273 - Figure 11-3. Watch Timer Mode Control Register Format
273 CHAPTER 11 WATCH TIMER (2) Watch timer mode control register (TMC2) This register sets the watch timer operating mode, watch flag set time and prescaler interval time and enables/disables prescaler and 5-bit counter operations. TMC2 is set with a 1-bit or 8-bit memory manipulation instruction. R...
Page 274 - Watch Timer Operations; Watch timer operation
274 CHAPTER 11 WATCH TIMER 11.4 Watch Timer Operations 11.4.1 Watch timer operation When the 32.768-kHz subsystem clock or 4.19-MHz main system clock is used, the timer operates as a watch timer with a 0.5-second or 0.25-second interval. The watch timer sets the test input flag (WTIF) to 1 at the co...
Page 275 - Table 12-1. Watchdog Timer Runaway Times
275 CHAPTER 12 WATCHDOG TIMER 12.1 Watchdog Timer Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer Caution Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (WDTM) (the watchdog timer and the interval timer cann...
Page 276 - CHAPTER 12 WATCHDOG TIMER
276 CHAPTER 12 WATCHDOG TIMER (2) Interval timer mode Interrupt requests are generated at the preset time intervals. Table 12-2. Interval Times Interval Time MCS = 1 MCS = 0 2 11 x 1/f XX 2 11 x 1/f X (410 µ s) 2 12 x 1/f X (819 µ s) 2 12 x 1/f XX 2 12 x 1/f X (819 µ s) 2 13 x 1/f X (1.64 ms) 2 13 x...
Page 277 - Watchdog Timer Configuration; The watchdog timer consists of the following hardware.; Table 12-3. Watchdog Timer Configuration; Figure 12-1. Watchdog Timer Block Diagram; Control register
277 CHAPTER 12 WATCHDOG TIMER Prescaler f XX 2 4 f XX 2 5 f XX 2 6 f XX 2 7 f XX 2 8 f XX 2 9 Selector Watchdog TimerMode Register Internal Bus Internal Bus TCL22 TCL21 TCL20 f XX /2 3 f XX 2 11 Timer Clock Select Register 2 3 WDTM4 RUN WDTM3 8-Bit Counter TMMK4 RUN TMIF4 INTWDTMaskable InterruptReq...
Page 278 - Watchdog Timer Control Registers; This register sets the watchdog timer count clock.
278 CHAPTER 12 WATCHDOG TIMER 12.3 Watchdog Timer Control Registers The following two types of registers are used to control the watchdog timer. • Timer clock select register 2 (TCL2) • Watchdog timer mode register (WDTM) (1) Timer clock select register 2 (TCL2) This register sets the watchdog timer...
Page 279 - Figure 12-2. Timer Clock Select Register 2 Format
279 CHAPTER 12 WATCHDOG TIMER Figure 12-2. Timer Clock Select Register 2 Format Caution When rewriting TCL2 to other data, stop the timer operation beforehand. Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscillation frequency 3. f XT : Subsystem clock osc...
Page 280 - WDTM is set with a 1-bit or 8-bit memory manipulation instruction.; Figure 12-3. Watchdog Timer Mode Register Format; Thus, once counting starts, it can only be stopped by RESET input.
280 CHAPTER 12 WATCHDOG TIMER (2) Watchdog timer mode register (WDTM) This register sets the watchdog timer operating mode and enables/disables counting. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM to 00H. Figure 12-3. Watchdog Timer Mode Register Format ...
Page 281 - Watchdog Timer Operations; Table 12-4. Watchdog Timer Runaway Detection Time
281 CHAPTER 12 WATCHDOG TIMER 12.4 Watchdog Timer Operations 12.4.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to detect any runaway. The watchdog timer count clock (runaway detection time interval) can be select...
Page 282 - requests, the INTWDT default has the highest priority.; timer mode is not set unless RESET input is applied.; Interval Time
282 CHAPTER 12 WATCHDOG TIMER 12.4.2 Interval timer operation The watchdog timer operates as an interval timer which generates interrupt requests repeatedly at an interval of the preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 0, respectively. The count clo...
Page 283 - Follow the procedure below to output clock pulses.; CLOE
283 CHAPTER 13 CLOCK OUTPUT CONTROL CIRCUIT 13.1 Clock Output Control Circuit Functions The clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSI. Clocks selected with the timer clock select register 0 (TCL0) a...
Page 284 - CHAPTER 13 CLOCK OUTPUT CONTROL CIRCUIT; Clock Output Control Circuit Configuration; Table 13-1. Clock Output Control Circuit Configuration; Figure 13-2. Clock Output Control Circuit Block Diagram
284 CHAPTER 13 CLOCK OUTPUT CONTROL CIRCUIT 13.2 Clock Output Control Circuit Configuration The clock output control circuit consists of the following hardware. Table 13-1. Clock Output Control Circuit Configuration Item Configuration Timer clock select register 0 (TCL0) Port mode register 3 (PM3) F...
Page 285 - Clock Output Function Control Registers; This register sets PCL output clock.
285 CHAPTER 13 CLOCK OUTPUT CONTROL CIRCUIT 13.3 Clock Output Function Control Registers The following two types of registers are used to control the clock output function. • Timer clock select register 0 (TCL0) • Port mode register 3 (PM3) (1) Timer clock select register 0 (TCL0) This register sets...
Page 286 - Figure 13-3. Timer Clock Select Register 0 Format
286 CHAPTER 13 CLOCK OUTPUT CONTROL CIRCUIT Figure 13-3. Timer Clock Select Register 0 Format Cautions 1. The TI00/P00/INTP0 pin valid edge is set by external interrupt mode register 0 (INTM0), and the sampling clock frequency is selected by the sampling clock selection register (SCS). 2. When enabl...
Page 287 - Figure 13-4. Port Mode Register 3 Format
287 CHAPTER 13 CLOCK OUTPUT CONTROL CIRCUIT Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscillation frequency 3. f XT : Subsystem clock oscillation frequency 4. TI00 : 16-bit timer/event counter input pin 5. TM0 : 16-bit timer register 6. MCS : Bit 0 of o...
Page 289 - Follow the procedure below to output the buzzer frequency.; Buzzer Output Control Circuit Configuration; Table 14-1. Buzzer Output Control Circuit Configuration; Figure 14-1. Buzzer Output Control Circuit Block Diagram; Timer Clock Select Register 2
289 CHAPTER 14 BUZZER OUTPUT CONTROL CIRCUIT 14.1 Buzzer Output Control Circuit Functions The buzzer output control circuit outputs 1.2-kHz, 2.4-kHz, 4.9-kHz, or 9.8-kHz frequency square waves. The buzzer frequency selected with timer clock select register 2 (TCL2) is output from the BUZ/P36 pin. Fo...
Page 290 - CHAPTER 14 BUZZER OUTPUT CONTROL CIRCUIT; Buzzer Output Function Control Registers; This register sets the buzzer output frequency.; watchdog timer count clock.
290 CHAPTER 14 BUZZER OUTPUT CONTROL CIRCUIT 14.3 Buzzer Output Function Control Registers The following two types of registers are used to control the buzzer output function. • Timer clock select register 2 (TCL2) • Port mode register 3 (PM3) (1) Timer clock select register 2 (TCL2) This register s...
Page 291 - Figure 14-2. Timer Clock Select Register 2 Format
291 CHAPTER 14 BUZZER OUTPUT CONTROL CIRCUIT Figure 14-2. Timer Clock Select Register 2 Format Caution When rewriting TCL2 to other data, stop the timer operation beforehand. Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscillation frequency 3. f XT : Subs...
Page 292 - Figure 14-3. Port Mode Register 3 Format
292 CHAPTER 14 BUZZER OUTPUT CONTROL CIRCUIT (2) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P36/BUZ pin for buzzer output function, set PM36 and output latch of P36 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET inp...
Page 293 - CHAPTER 15 A/D CONVERTER
293 CHAPTER 15 A/D CONVERTER 15.1 A/D Converter Functions The A/D converter converts an analog input into a digital value. It consists of 8 channels (ANI0 to ANI7) with an 8-bit resolution. The conversion method is based on successive approximation and the conversion result is held in the 8-bit A/ D...
Page 294 - Tap Selector
294 CHAPTER 15 A/D CONVERTER ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 Selector A /D Converter Mode Register Selector Trigger Enable ES40, ES41 Note 3 Sample & Hold Circuit 3 CS Internal Bus EdgeDetector Control Circuit Series Resistor String AV DD Voltage Comparato...
Page 296 - pin when not using; pin when not
296 CHAPTER 15 A/D CONVERTER Caution A series resistor string of approximately 10 k Ω is connected between AV REF0 pin and AV SS pin. Therefore, if the output impedance of the reference voltage source is high, AV REF0 pin is connected in parallel with the series resistor string between AV REF0 pin a...
Page 297 - Setting prohibited because A/D conversion time is less than 19.1
297 CHAPTER 15 A/D CONVERTER Figure 15-2. A/D Converter Mode Register Format Notes 1. Set so that the A/D conversion time is 19.1 µ s or more. 2. Setting prohibited because A/D conversion time is less than 19.1 µ s. Cautions 1. The following sequence is recommended for power consumption reduction of...
Page 298 - ADIS is set with an 8-bit memory manipulation instruction.; Cautions 1. Set the analog input channel in the following order.
298 CHAPTER 15 A/D CONVERTER (2) A/D converter input select register (ADIS) This register determines whether the ANI0/P10 to ANI7/P17 pins should be used for analog input channels or ports. Pins other than those selected as analog input can be used as input/output ports. ADIS is set with an 8-bit me...
Page 299 - This register sets the valid edge for INTP3 to INTP6.; Figure 15-4. External Interrupt Mode Register 1 Format
299 CHAPTER 15 A/D CONVERTER (3) External interrupt mode register 1 (INTM1) This register sets the valid edge for INTP3 to INTP6. INTM1 is set with an 8-bit memory manipulation instruction. RESET input sets INTM1 to 00H. Figure 15-4. External Interrupt Mode Register 1 Format ES71 7 ES70 6 ES61 ES60 ...
Page 300 - • Analog input voltage
300 CHAPTER 15 A/D CONVERTER 15.4 A/D Converter Operations 15.4.1 Basic operations of A/D converter (1) Set the number of analog input channels with A/D converter input select register (ADIS). (2) From among the analog input channels set with ADIS, select one channel for A/D conversion with A/D conv...
Page 301 - After RESET input, the value of ADCR is undefined.; SAR
301 CHAPTER 15 A/D CONVERTER Figure 15-5. A/D Converter Basic Operation A/D conversion operations are performed continuously until bit 7 (CS) of ADM is reset (0) by software. If a write to ADM is performed during an A/D conversion operation, the conversion operation is initialized, and if the CS bit...
Page 302 - Input voltage and conversion results
302 CHAPTER 15 A/D CONVERTER 15.4.2 Input voltage and conversion results The relation between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion result (the value stored in ADCR) is shown by the following expression. ADCR = INT ( x 256 + 0.5) or (ADCR – 0.5...
Page 303 - The following two ways are available to start A/D conversion.
303 CHAPTER 15 A/D CONVERTER 15.4.3 A/D converter operating mode One analog input channel is selected from among ANI0 to ANI7 with the A/D converter input select register (ADIS) and A/D converter mode register (ADM) and A/D conversion is executed. The following two ways are available to start A/D co...
Page 304 - tinues repeatedly until new data is written to ADM.
304 CHAPTER 15 A/D CONVERTER (2) A/D conversion operation in software start When bit 6 (TRG) and bit 7 (CS) of A/D converter mode register (ADM) are set to 0 and 1, respectively, the A/D conversion starts on the voltage applied to the analog input pins specified with bits 1 to 3 (ADM1 to ADM3) of AD...
Page 305 - pin at this time, this current must
305 CHAPTER 15 A/D CONVERTER 15.5 A/D Converter Cautions (1) Current consumption in standby mode The A/D converter operates on the main system clock. Therefore, its operation stops in STOP mode or in HALT mode with the subsystem clock. As a current still flows in the AV REF0 pin at this time, this c...
Page 306 - and ANI0 to ANI7. Since; Figure 15-10. Analog Input Pin Disposition; adjacent to the pin undergoing A/D conversion.
306 CHAPTER 15 A/D CONVERTER (2) Input range of ANI0 to ANI7 The input voltages of ANI0 to ANI7 should be within the specification range. In particular, if a voltage above AV REF0 or below AV SS is input (even if within the absolute maximum rating range), the conversion value for that channel will b...
Page 307 - pin input impedance; pin; Pin
307 CHAPTER 15 A/D CONVERTER (5) AV REF0 pin input impedance A series resistor string of approximately 10 k Ω is connected between the AV REF0 pin and the AV SS pin. Therefore, if the output impedance of the reference voltage source is high, this will result in parallel connection to the series resi...
Page 309 - CHAPTER 16 D/A CONVERTER; The conversion method used is the R-2R resistor ladder method.
309 CHAPTER 16 D/A CONVERTER 16.1 D/A Converter Functions The D/A converter converts a digital input into an analog value. It consists of two 8-bit resolution channels of voltage output type D/A converter. The conversion method used is the R-2R resistor ladder method. Start the A/D conversion by set...
Page 310 - The D/A converter consists of the following hardware.
310 CHAPTER 16 D/A CONVERTER 16.2 D/A Converter Configuration The D/A converter consists of the following hardware. Table 16-1. D/A Converter Configuration Item Configuration D/A conversion value set register 0 (DACS0) D/A conversion value set register 1 (DACS1) Control register D/A converter mode r...
Page 311 - RESET input sets these registers to 00H.; trigger and before the next output trigger.; DACSn
311 CHAPTER 16 D/A CONVERTER (1) D/A conversion value set register 0, 1 (DACS0, DACS1) DACS0 and DACS1 are registers that set the value used to determine analog voltage values output to the ANO0 and ANO1 pins, re-spectively. DACS0 and DACS1 are set with 8-bit memory manipulation instructions. RESET ...
Page 312 - The DAM is set with a 1-bit or 8-bit memory manipulation instruction.; a pull-up resistor should be disconnected.
312 CHAPTER 16 D/A CONVERTER 16.3 D/A Converter Control Registers The D/A converter mode register (DAM) controls the D/A converter. This register sets D/A converter operation enable/stop. The DAM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Fig...
Page 313 - synchronously with the output triggers.; Caution Set DACE0 and DACE1 after setting data in DACS0 and DACS1.
313 CHAPTER 16 D/A CONVERTER 16.4 D/A Converter Operations (1) Select the channel 0 operating mode and channel 1 operating mode with DAM4 and DAM5, respectively, of the D/A converter mode register (DAM). (2) Set the data corresponding to the analog voltages output to the ANO0/P130 and ANO1/P131 pins...
Page 314 - Figure 16-3. Use Example of Buffer Amplifier; When only either one of the D/A converter channels is used with AV; , the other pins that are not; low level from the pin.; ANOn
314 CHAPTER 16 D/A CONVERTER 16.5 D/A Converter Cautions (1) Output impedance of D/A converter Because the output impedance of the D/A converter is high, use of current flowing from the ANOn pins (n = 0,1) is prohibited. If the input impedance of the load for the converter is low, insert a buffer am...
Page 315 - CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (
315 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) The µ PD78078 Subseries incorporates three channels of serial interfaces. Differences between channels 0, 1, and 2 are as follows (Refer to CHAPTER 19 SERIAL INTERFACE CHANNEL 1 for details of the serial interface channel 1. Refer to C...
Page 316 - Serial Interface Channel 0 Functions
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 316 17.1 Serial Interface Channel 0 Functions Serial interface channel 0 employs the following four modes. • Operation stop mode • 3-wire serial I/O mode • SBI (serial bus interface) mode • 2-wire serial I/O mode Caution Do not change the ...
Page 318 - Serial Interface Channel 0 Configuration; Table 17-2. Serial Interface Channel 0 Configuration
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 318 17.2 Serial Interface Channel 0 Configuration Serial interface channel 0 consists of the following hardware. Table 17-2. Serial Interface Channel 0 Configuration Item Configuration Serial I/O shift register 0 (SIO0) Slave address regis...
Page 319 - SIO0 is set with an 8-bit memory manipulation instruction.
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 319 (1) Serial I/O shift register 0 (SIO0) This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO0 is set with an 8-b...
Page 320 - SBI mode, this latch is set upon termination of the 8th serial clock.; When WUP
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 320 (3) SO0 latch This latch holds SI0/SB0/P25 and SO0/SB1/P26 pin levels. It can be directly controlled by software. In the SBI mode, this latch is set upon termination of the 8th serial clock. (4) Serial clock counter This counter counts...
Page 321 - Serial Interface Channel 0 Control Registers
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 321 17.3 Serial Interface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0. • Timer clock select register 3 (TCL3) • Serial operating mode register 0 (CSIM0) • Serial bus inte...
Page 322 - Figure 17-3. Timer Clock Select Register 3 Format
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 322 Figure 17-3. Timer Clock Select Register 3 Format Caution When rewriting TCL3 to other data, stop the serial transfer operation beforehand. Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscill...
Page 323 - function and displays the address comparator match signal.
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 323 (2) Serial operating mode register 0 (CSIM0) This register sets serial interface channel 0 serial clock, operating mode, operation enable/stop wake-up function and displays the address comparator match signal. CSIM0 is set with a 1-bit...
Page 324 - Figure 17-4. Serial Operating Mode Register 0 Format; PMxx : Port mode register
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 324 SBI mode <6> <5> 4 3 2 1 0 <7> Symbol CSIM0 CSIE0 COI WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 CSIM01 0 1 Serial Interface Channel 0 Clock Selection Input Clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) out...
Page 325 - SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 325 (3) Serial bus interface control register (SBIC) This register sets serial bus interface operation and displays statuses. SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Figure 17-5. Ser...
Page 327 - SINT is set with a 1-bit or 8-bit memory manipulation instruction.; Figure 17-6. Interrupt Timing Specify Register Format; SVA
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 327 (4) Interrupt timing specify register (SINT) This register sets the bus release interrupt and address mask functions and displays the SCK0/P27 pin level status. SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET i...
Page 328 - Serial Interface Channel 0 Operations; • Operation stop mode
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 328 17.4 Serial Interface Channel 0 Operations The following four operating modes are available to the serial interface channel 0. • Operation stop mode • 3-wire serial I/O mode • SBI mode • 2-wire serial I/O mode 17.4.1 Operation stop mod...
Page 329 - CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 329 <6> <5> 4 3 2 1 0 <7> Symbol CSIM0 CSIM01 0 1 Serial Interface Channel 0 Clock Selection Input Clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output 0 SBI mode (See 17.4.3 SBI mode operation.) R/W 1 Cloc...
Page 331 - input to the SI0 pin is latched in SIO0 at the rising edge of SCK0.
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 331 (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/ reception is carried out in synchronization with the serial clock. Shift operation of the serial...
Page 332 - Figure 17-9. Circuit of Switching in Transfer Bit Order; two conditions are satisfied.
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 332 (4) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start at MSB or LSB. Figure 17-9 shows the configuration of the serial I/O shift register 0 (SIO0) and internal bus. As shown in the figure...
Page 333 - the board can be decreased.; Figure 17-10. Example of Serial Bus Configuration with SBI
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 333 17.4.3 SBI mode operation SBI (Serial Bus Interface) is a high-speed serial interface in compliance with the NEC serial bus format. SBI uses a single-master device and employs the clocked serial I/O format with the addition of a bus co...
Page 334 - controlled by software, the software must be heavily loaded.; (b) Chip select function by address transmission; The busy signal to report the slave busy state is controlled.
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 334 (1) SBI functions In the conventional serial I/O format, when a serial bus is configured by connecting two or more devices, many ports and wiring are necessary, to provide chip select signal to identify command and data, and to judge t...
Page 335 - The broken lines indicate the READY state.
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 335 SCK0 SB0 (SB1) SCK0 SB0 (SB1) SCK0 SB0 (SB1) 8 9 9 A7 A0 ACK BUSY C7 C0 ACK BUSY READY 8 9 D7 D0 ACK BUSY READY Address Transfer Command Transfer Data Transfer Bus ReleaseSignal Command Signal Address Data Command (2) SBI definition Th...
Page 336 - This signal is output by the master device.
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 336 SCK0 “H” SB0 (SB1) (a) Bus release signal (REL) The bus release signal is a signal with the SB0 (SB1) line which has changed from the low level to the high level when the SCK0 line is at the high level (without serial clock output). Th...
Page 337 - in order to select a particular slave device.; Figure 17-15. Slave Selection with Address; Master; Slave 2; Slave 3
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 337 (c) Address An address is 8-bit data which the master device outputs to the slave device connected to the bus line in order to select a particular slave device. Figure 17-14. Addresses 8-bit data following bus release and command signa...
Page 338 - selected by address transmission.; Command
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 338 (d) Command and data The master device transmits commands to, and transmits/receives data to/from the slave device selected by address transmission. Figure 17-16. Commands Figure 17-17. Data 8-bit data following a command signal is def...
Page 339 - [When output in synchronization with 11th clock SCK0]; The brokens lines indicate the READY state.
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 339 (e) Acknowledge signal (ACK) The acknowledge signal is used to check serial data reception between transmitter and receiver. Figure 17-18. Acknowledge Signal [When output in synchronization with 11th clock SCK0] [When output in synchro...
Page 343 - Caution Set bits 0 to 3 to 0.
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 343 (c) Interrupt timing specify register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. Notes 1. Bit 6 (CLD) is a read-only bit. 2. When using wake-up function in the SBI mode, set ...
Page 345 - Caution Do not set ACKT before termination of transfer.; ACKT
345 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) Figure 17-22. ACKT Operation Caution Do not set ACKT before termination of transfer. SCK0 6 SB0 (SB1) ACKT 7 8 9 D2 D1 D0 ACK When set during this period ACK signal is output fora period of one clockjust after setting
Page 346 - (b) When set after completion of transfer
346 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) Figure 17-23. ACKE Operations (a) When ACKE = 1 upon completion of transfer (b) When set after completion of transfer (c) When ACKE = 0 upon completion of transfer (d) When “ACKE = 1” period is short SB0 (SB1) ACKE 1 2 7 8 9 D7 D6 D2 D...
Page 347 - (a) When ACK signal is output at 9th clock of SCK0; ACKD; BUSY
347 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) Figure 17-24. ACKD Operations (a) When ACK signal is output at 9th clock of SCK0 (b) When ACK signal is output after 9th clock of SCK0 (c) Clear timing when transfer start is instructed in BUSY Figure 17-25. BSYE Operation SCK0 SB0 (SB...
Page 349 - Synchronous clock to output; In BUSY state, transfer starts after the READY state is set.
349 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) Timing Chart Definition Signal Name Output Device Output Condition Effects on Flag Meaning of Signal Synchronous clock to output address/command/data, ACK signal, synchronous BUSY signal, etc. Address/ command/data are transferred with...
Page 350 - it is not necessary to write FFH to SIO0.
350 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) (5) Pin configuration The serial clock pin SCK0 and serial data bus pin SB0 (SB1) have the following configurations. (a) SCK0 ............ Serial clock input/output pin <1> Master ... CMOS and push-pull output <2> Slave ......
Page 351 - device matches the value set to SVA.; instead of using the address match detection method.; two or more devices by outputting an “address” to the serial bus.
351 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) (6) Address match detection method In the SBI mode, a particular slave device can be selected by transmitting slave address from the master device. Address match detection can be automatically executed by hardware. With slave address r...
Page 354 - Figure 17-29. Data Transmission from Master Device to Slave Device
354 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 1 2 3 4 5 6 7 8 9 SCK0 Pin D7 D6 D5 D4 D3 D2 D1 D0 ACK BUSY SB0 (SB1) Pin Program Processing Serial Transmission INTCSI0 Generation ACKD Set SCK0 Stop Hardware Operation ACKT Set Program Processing INTCSI0 Generation ACK Output Hardwar...
Page 355 - Figure 17-30. Data Transmission from Slave Device to Master Device
355 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) 1 2 3 4 5 6 7 8 9 SCK0 Pin D7 D6 D5 D4 D3 D2 D1 D0 ACK BUSY SB0 (SB1) Pin Program Processing Serial Reception INTCSI0 Generation ACK Output SerialReception Hardware Operation Program Processing INTCSI0 Generation ACKD Set Hardware Oper...
Page 356 - write FFH to SIO0 in advance.; serial transfer of the first byte.; (10) How to detect the busy state in a slave
356 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) (9) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. • Serial interface channel 0 operation control bit (CSIE0) = 1 • Internal...
Page 357 - serial transfer of the 1st byte after RESET input.
357 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) (d) For pins which are to be used for data input/output, be sure to carry out the following settings before serial transfer of the 1st byte after RESET input. <1> Set 1 to the output latch of P25 and P26 <2> Set 1 to bit 0 ...
Page 360 - CSIIF0 : Interrupt request flag corresponding to INTCSI0
360 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) (c) Interrupt timing specify register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. Notes 1. Bit 6 (CLD) is a read-only bit. 2. When CSIE0 = 0, CLD becomes 0. Caution Set bits 0...
Page 361 - is carried out bit-wise in synchronization with the serial clock.; Transfer Start at the Falling Edge of SCK0
361 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) (2) Communication operation The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization with the serial clock. Shift operation of the serial ...
Page 362 - state for data reception, write FFH to SIO0 in advance.
362 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) (4) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. • Serial interface channel 0 operation control bit (CSIE0) = 1 • Internal...
Page 363 - Latch; to normal serial clock output.
363 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78078 SUBSERIES) To InternalCircuit SCK0/P27 P27 Output Latch When CSIE0 = 1 and CSIM01 and CSIM00 are 1 and 0, or 1 and 1. Set by bit manipulation instruction SCK0 (1 when transfer stops) From Serial ClockControl Circuit 17.4.5 SCK0/P27 pin output man...
Page 365 - CHAPTER 18 SERIAL INTERFACE CHANNEL 0 (
365 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) The µ PD78078Y Subseries incorporates three channels of serial interfaces. Differences between channels 0, 1, and 2 are as follows (Refer to CHAPTER 19 SERIAL INTERFACE CHANNEL 1 for details of the serial interface channel 1. Refer to...
Page 366 - Serial Interface Channel 0 Functions; Serial interface channel 0 employs the following four modes.; C bus) while the operation; the data transfer processing time.
366 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) 18.1 Serial Interface Channel 0 Functions Serial interface channel 0 employs the following four modes. • Operation stop mode • 3-wire serial I/O mode • 2-wire serial I/O mode • I 2 C (Inter IC) bus mode Caution Do not change the opera...
Page 367 - This mode is in compliance with the I; Figure 18-1. Serial Bus Configuration Example Using I
367 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (4) I 2 C (Inter IC) bus mode (MSB-first) This mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (SCL) and serial data bus (SDA0 or SDA1). This mode is in compliance with the I 2 C bus forma...
Page 368 - Serial Interface Channel 0 Configuration; Table 18-2. Serial Interface Channel 0 Configuration
368 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) 18.2 Serial Interface Channel 0 Configuration Serial interface channel 0 consists of the following hardware. Table 18-2. Serial Interface Channel 0 Configuration Item Configuration Serial I/O shift register 0 (SIO0) Slave address regi...
Page 369 - Figure 18-2. Serial Interface Channel 0 Block Diagram
369 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) Figure 18-2. Serial Interface Channel 0 Block Diagram Remark Output Control performs selection between CMOS output and N-ch open-drain output. CSIE0 COI WUP CSIM 04 CSIM 03 CSIM 02 CSIM 01 CSIM 00 Serial Operating Mode Register 0 Cont...
Page 370 - Caution In the I
370 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (1) Serial I/O shift register 0 (SIO0) This is an 8-bit register to carry out parallel-serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO0 is set with an 8-...
Page 372 - Serial Interface Channel 0 Control Registers; • Serial operating mode register 0 (CSIM0)
372 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) 18.3 Serial Interface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0. • Timer clock select register 3 (TCL3) • Serial operating mode register 0 (CSIM0) • Serial bus int...
Page 373 - This register sets the serial clock of serial interface channel 0.; Figure 18-3. Timer Clock Select Register 3 Format
373 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (1) Timer clock select register 3 (TCL3) This register sets the serial clock of serial interface channel 0. TCL3 is set with an 8-bit memory manipulation instruction. RESET input sets TCL3 to 88H. Figure 18-3. Timer Clock Select Regis...
Page 374 - changing the operation mode.
374 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (2) Serial operating mode register 0 (CSIM0) This register sets serial interface channel 0 serial clock, operating mode, operation enable/stop wake-up function and displays the address comparator match signal. CSIM0 is set with a 1-bi...
Page 375 - Figure 18-4. Serial Operating Mode Register 0 Format; C bus mode, the clock frequency becomes 1/16 of that output from TO2.
375 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) Figure 18-4. Serial Operating Mode Register 0 Format Notes 1. Bit 6 (COI) is a read-only bit. 2. I 2 C bus mode, the clock frequency becomes 1/16 of that output from TO2. 3. Can be used as P25 (CMOS input/output) when used only for tr...
Page 377 - Notes 1. Setting should be performed before transfer.
377 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) Figure 18-5. Serial Bus Interface Control Register Format (2/2) Notes 1. Setting should be performed before transfer. 2. If 8-clock wait mode is selected, the acknowledge signal at reception time must be output using ACKT. 3. The busy...
Page 378 - RESET input sets SINT to 00H.; When not using the I
378 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (4) Interrupt timing specify register (SINT) This register sets the bus release interrupt and address mask functions and displays the SCK0/SCL pin level status. SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET ...
Page 379 - Notes 1. When using wake-up function in the I
379 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) Figure 18-6. Interrupt Timing Specify Register Format (2/2) Notes 1. When using wake-up function in the I 2 C mode, set SIC to 0. 2. When CSIE0 = 0, CLD becomes 0. Remark SVA : Slave address register CSIIF0 : Interrupt request flag co...
Page 380 - Serial Interface Channel 0 Operations
380 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) 18.4 Serial Interface Channel 0 Operations The following four operating modes are available to the serial interface channel 0. • Operation stop mode • 3-wire serial I/O mode • 2-wire serial I/O mode • I 2 C (Inter IC) bus mode 18.4.1 ...
Page 384 - Figure 18-9. Circuit of Switching in Transfer Bit Order
384 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (4) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 18-9 shows the configuration of the serial I/O shift register 0 (SIO0) and internal bus. As shown in the fig...
Page 386 - PMxxx : Port mode register
386 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) <6> <5> 4 3 2 1 0 <7> Symbol CSIM0 CSIE0 COI WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 CSIM01 0 1 Serial Interface Channel 0 Clock Selection Input Clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output R/W ...
Page 387 - Caution Set bits 0 to 3 to 0 when the 2-wire serial I/O mode is selected.
387 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) <6> <5> <4> <3> <2> <1> <0> <7> Symbol SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT RELT When RELT = 1, SO0 Iatch is set to 1. After SO0 Iatch setting, automatically cleared to 0. Also c...
Page 389 - Figure 18-12 shows RELT and CMDT operations.
389 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (3) Other signals Figure 18-12 shows RELT and CMDT operations. Figure 18-12. RELT and CMDT Operations (4) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following ...
Page 390 - C bus mode operation; The I; Figure 18-13. Example of Serial Bus Configuration Using I
390 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) 18.4.4 I 2 C bus mode operation The I 2 C bus mode is provided for when communication operations are performed between a single master device and multiple slave devices. This mode configures a serial bus that includes only a single ma...
Page 391 - C bus mode functions
391 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (1) I 2 C bus mode functions In the I 2 C bus mode, the following functions are available. (a) Automatic identification of serial data Slave devices automatically detect and identifies start condition, data, and stop condition signals...
Page 392 - C bus mode, for details of the start condition output.; If it is 1, it is the slave device which will send data to the master.; Figure 18-17. Transfer Direction Specification
392 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (a) Start condition When the SDA0 (SDA1) pin level is changed from high to low while the SCL pin is high, this transition is recognized as the start condition signal. This start condition signal, which is created using the SCL and SDA...
Page 393 - as a stop condition signal.
393 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) “H” SCL SDA0 (SDA1) (d) Acknowledge signal (ACK) The acknowledge signal indicates that the transferred serial data has definitely been received. This signal is used between the sending side and receiving side devices for confirmation ...
Page 394 - state due to preparing for transmitting or receiving data.
394 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (f) Wait signal (WAIT) The wait signal is output by a slave device to inform the master device that the slave device is in wait state due to preparing for transmitting or receiving data. During the wait state, the slave device continu...
Page 396 - SBIC is set by a 1-bit or 8-bit memory manipulation instruction.; This setting must be performed prior to transfer start.
396 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) <6> <5> <4> <3> <2> <1> <0> <7> Symbol SBIC BSYE ACKD ACKE FF61H 00H R/W Note1 Address After Reset R/W ACKT CMDD RELD CMDT RELT (b) Serial bus interface control register (SBIC) SBIC is s...
Page 397 - SINT is set by the 1-bit or 8-bit memory manipulation instruction.; Remark SVA; : Slave address register
397 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (c) Interrupt timing specification register (SINT) SINT is set by the 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. R/W WAT1 WAT0 Interrupt control by wait Note 2 0 0 Interrupt service request is genera...
Page 398 - A list of signals in the I; C Bus Mode
398 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (4) Various signals A list of signals in the I 2 C bus mode is given in Table 18-4. Table 18-4. Signals in I 2 C Bus Mode Signal name Description Start condition Definition : SDA0 (SDA1) falling edge when SCL is high (Note 1) Function...
Page 407 - conditions have been satisfied:; does not initiate transfer operation.
407 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (9) Start of transfer A serial transfer is started by setting transfer data in the serial I/O shift register 0 (SIO0) if the following two conditions have been satisfied: • The serial interface channel 0 operation control bit (CSIE0) ...
Page 408 - C bus mode
408 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) 18.4.5 Cautions on use of I 2 C bus mode (1) Start condition output (master) The SCL pin normally outputs a low-level signal when no serial clock is output. It is necessary to change the SCL pin to high in order to output a start cond...
Page 409 - to 1 after execution of an SIO0 write instruction.
409 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (2) Slave wait release (slave transmission) The wait status of a slave is released by setting the WREL flag, which is bit 2 of the interrupt timing specify register (SINT), or by executing a serial I/O shift register 0 (SIO0) write in...
Page 410 - as shown in Figure 18-26 to receive data correctly.
410 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) (3) Slave wait release (slave reception) The wait status of a slave is released by setting the WREL flag, which is bit 2 of the interrupt timing specify register (SINT), or by executing a serial I/O shift register 0 (SIO0) write instr...
Page 412 - • Example of program releasing serial transfer status
412 CHAPTER 18 SERIAL INTERFACE CHANNEL 0 ( µ PD78078Y Subseries) • Example of program releasing serial transfer status SET1 P2.5 ; <1> SET1 PM2.5 ; <2> SET1 PM2.7 ; <3> CLR1 CSIE0 ; <4> SET1 CSIE0 ; <5> SET1 RELT ; <6> CLR1 PM2.7 ; <7> CLR1 P2.5 ; <8>...
Page 415 - Serial interface channel 1 employs the following three modes.
415 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 19.1 Serial Interface Channel 1 Functions Serial interface channel 1 employs the following three modes. • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function (1) Operation stop mode This mode is used...
Page 416 - CHAPTER 19 SERIAL INTERFACE CHANNEL 1; Serial Interface Channel 1 Configuration; Table 19-1. Serial Interface Channel 1 Configuration
416 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 19.2 Serial Interface Channel 1 Configuration Serial interface channel 1 consists of the following hardware. Table 19-1. Serial Interface Channel 1 Configuration Item Configuration Register Serial I/O shift register 1 (SIO1) Automatic data transmit/receive a...
Page 417 - SIO1 is set with an 8-bit memory manipulation instruction.
417 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (1) Serial I/O shift register 1 (SIO1) This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO1 is set with an 8-bit memory manipulation ...
Page 418 - Serial Interface Channel 1 Control Registers
418 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 19.3 Serial Interface Channel 1 Control Registers The following four types of registers are used to control serial interface channel 1. • Timer clock select register 3 (TCL3) • Serial operating mode register 1 (CSIM1) • Automatic data transmit/receive contro...
Page 419 - CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction.; Figure 19-3. Serial Operation Mode Register 1 Format
419 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Notes 1. If the external clock input has been selected with CSIM11 set to 0, set bit 1 (BUSY1) and bit 2 (STRB) of the automatic data transmit/receive control register (ADTC) to 0, 0. 2. Can be used freely as port function. 3. Can be used as P20 (CMOS input/...
Page 420 - ADTC is set with a 1-bit or 8-bit memory manipulation instruction.
420 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (3) Automatic data transmit/receive control register (ADTC) This register sets automatic receive enable/disable, the operating mode, strobe output enable/disable, busy input enable/disable, and error check enable/disable, and displays automatic transmit/rece...
Page 421 - Notes 1. The interval is dependent only on CPU processing.
421 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (4) Automatic data transmit/receive interval specify register (ADTI) This register sets the automatic data transmit/receive function data transfer interval. ADTI is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTI to 00H. Figure...
Page 422 - , the minimum interval time
422 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Figure 19-5. Automatic Data Transmit/Receive Interval Specify Register Format (2/4) Note The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4). ...
Page 425 - Serial Interface Channel 1 Operations; Notes 1. Can be used freely as port function.
425 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 19.4 Serial Interface Channel 1 Operations The following three operating modes are available to the serial interface channel 1. • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function 19.4.1 Operation ...
Page 427 - to the SI1 pin is latched into SIO1 at the rising edge of SCK1.; Caution SO1 pin becomes low level by SIO1 write.
427 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/ reception is carried out in synchronization with the serial clock. Shift operation of the serial I/O shift register 1 (...
Page 428 - Figure 19-7. Circuit of Switching in Transfer Bit Order
428 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Figure 19-7. Circuit of Switching in Transfer Bit Order Start bit switching is realized by switching the bit order write to SIO1. The SIO1 shift order remains unchanged. Thus, MSB-first and LSB-first must be switched before writing data to the shift register...
Page 431 - ADTI is set with a 1-bit or 8-bit memory manipulation instruction.
431 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (c) Automatic data transmit/receive interval specify register (ADTI) This register sets the automatic data transmit/receive function data transfer interval. ADTI is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTI to 00H. Note...
Page 435 - subtracting 1 from the number of transmit data bytes.; the written value has no meaning.
435 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (2) Automatic transmit/receive data setting (a) Transmit data setting <1> Write transmit data from the least significant address FAC0H of buffer RAM (up to FADFH at maximum). The transmit data should be in the order from high-order address to low-order...
Page 436 - CSIIF0 : Interrupt request flag; Figure 19-8. Basic Transmission/Reception Mode Operation Timings
436 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Cautions 1. Because, in the basic transmission/reception mode, the automatic transmit/receive function writes/reads data to/from the buffer RAM after 1-byte transmission/reception, an interval is inserted till the next transmission/reception. As the buffer R...
Page 437 - ADTP : Automatic data transmit/receive address pointer
437 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 ADTP : Automatic data transmit/receive address pointer ADTI : Automatic data transmit/receive interval specify register SIO1 : Serial I/O shift register 1 TRF : Bit 3 of automatic data transmit/receive control register (ADTC) Start Write transmit data in buf...
Page 438 - is transferred from SIO1 to the buffer RAM, and ADTP is decremented.
438 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission/reception (ARLD = 0, RE = 1) in basic transmit/receive mode, buffer RAM operates as follows. (i) Before transmission/reception (refer to Figure 19-10 (a)) After any data has been written to the serial I/O shift register 1 (SIO1) (start...
Page 440 - BUSY pins can be used as normal input/ports.; Figure 19-11. Basic Transmission Mode Operation Timings; CSIIF1 : Interrupt request flag
440 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (b) Basic transmission mode In this mode, the specified number of 8-bit unit data are transmitted. Serial transfer is started when any data is written to the serial I/O shift register 1 (SIO1) while bit 7 (CSIE1) of the serial operating mode register 1 (CSIM...
Page 441 - Figure 19-12. Basic Transmission Mode Flowchart
441 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Figure 19-12. Basic Transmission Mode Flowchart ADTP : Automatic data transmit/receive address pointer ADTI : Automatic data transmit/receive interval specify register SIO1 : Serial I/O shift register 1 TRF : Bit 3 of automatic data transmit/receive control ...
Page 444 - are transmitted again.; Figure 19-14. Repeat Transmission Mode Operation Timing
444 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (c) Repeat transmission mode In this mode, data stored in the buffer RAM is transmitted repeatedly. Serial transfer is started by writing any data to serial I/O shift register 1 (SIO1) when 1 is set in bit 7 (CSIE1) of the serial operating mode register 1 (C...
Page 445 - Figure 19-15. Repeat Transmission Mode Flowchart
445 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Figure 19-15. Repeat Transmission Mode Flowchart ADTP : Automatic data transmit/receive address pointer ADTI : Automatic data transmit/receive interval specify register SIO1 : Serial I/O shift register 1 Start Write transmit data in buffer RAM Set ADTP to th...
Page 446 - The first pointer value is set to ADTP again.
446 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission (ARLD = 1, RE = 0) in repeat transmit mode, buffer RAM operates as follows. (i) Before transmission (refer to Figure 19-16 (a)) After any data has been written to the serial I/O shift register 1 (SIO1) (start trigger: this data is not ...
Page 447 - (b) Upon completion of transmission of 6 bytes
447 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Figure 19-16. Buffer RAM Operation in 6-byte Transmission (in Repeat Transmit Mode) (2/2) (b) Upon completion of transmission of 6 bytes (c) 7th byte transmission point Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) Transmit data 4 (T4) Trans...
Page 448 - is suspended upon completion of 8-bit data transfer.; Suspend
448 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (d) Automatic transmission/reception suspending and restart Automatic transmission/reception can be temporarily suspended by setting bit 7 (CSIE1) of the serial operating mode register 1 (CSIM1) to 0. If during 8-bit data transfer, the transmission/reception...
Page 449 - device and slave device.; simultaneously, busy control becomes invalid.; Master Device
449 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (4) Synchronization control Busy control and strobe control are functions for synchronizing sending and receiving between the master device and slave device. By using these functions, it is possible to detect bit slippage during sending and receiving. (a) Bu...
Page 450 - Caution When TRF is cleared, the SO1 pin becomes low level.
450 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Figure 19-19. Operation Timings when Using Busy Control Option (BUSY0 = 0) Caution When TRF is cleared, the SO1 pin becomes low level. Remark CSIIF1 : Interrupt request flag TRF : Bit 3 of the automatic data transmit/receive control register (ADTC) If the bu...
Page 451 - or receiving can wait while the busy signal is being input.
451 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 Figure 19-20. Busy Signal and Wait Cancel (BUSY0 = 0) (b) Busy & strobe control option Strobe control is a function for synchronizing the sending and receiving of data between a master device and slave device. When sending or receiving of 8 bit data ends...
Page 453 - (c) Bit slippage detection function through the busy signal; during sending, bit slippage can be detected.
453 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (c) Bit slippage detection function through the busy signal During an automatic transmit/receive operation, noise occur in the serial clock signal output by the master device and bit slippage may occur in the slave device side serial clock. At this time, if ...
Page 454 - interval may be longer than the value indicated by paragraph (b).
454 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (5) Automatic transmit/receive interval time When using the automatic transmit/receive function, the read/write operations from/to the buffer RAM are performed after transmitting/receiving one byte. Therefore, an interval is inserted before the next transmit...
Page 455 - Internal Clock
455 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (a) When the automatic transmit/receive function is used by the internal clock If bit 1 (CSIM11) of serial operation mode register 1 (CSIM1) is set at (1), the internal clock operates. If the automatic transmit/receive function is operated by the internal cl...
Page 456 - or longer
456 CHAPTER 19 SERIAL INTERFACE CHANNEL 1 (b) When the automatic transmit/receive function is used by the external clock If bit 1 (CSIM11) of serial operating mode register 1 (CSIM1) is cleared to 0, external clock operation is set. When the automatic transmit/receive function is used by the externa...
Page 457 - Serial interface channel 2 has the following three modes.
457 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 20.1 Serial Interface Channel 2 Functions Serial interface channel 2 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial transfer is n...
Page 458 - CHAPTER 20 SERIAL INTERFACE CHANNEL 2; Serial Interface Channel 2 Configuration; Table 20-1. Serial Interface Channel 2 Configuration
458 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 20.2 Serial Interface Channel 2 Configuration Serial interface channel 2 consists of the following hardware. Table 20-1. Serial Interface Channel 2 Configuration Item Configuration Register Transmit shift register (TXS) Receive shift register (RXS) Receive b...
Page 459 - Figure 20-2. Baud Rate Generator Block Diagram
459 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 Figure 20-2. Baud Rate Generator Block Diagram TPS3 TPS2 TPS1 TPS0 Internal Bus MDL3 MDL2 MDL1 MDL0 Baud Rate Generator Control Register 4 TXE CSIE2 5-Bit Counter Selector Selector Decoder 1/2 Selector Terminal Clock 1/2 Selector Receive Clock Match Match MD...
Page 460 - write is performed, the value is written to TXS.
460 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (1) Transmit shift register (TXS) This register is used to set the transmit data. The data written in TXS is transmitted as serial data. If the data length is specified as 7 bits, bits 0 to 6 of the data written in TXS are transferred as transmit data. Writi...
Page 461 - Serial Interface Channel 2 Control Registers; Figure 20-3. Serial Operating Mode Register 2 Format
461 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 20.3 Serial Interface Channel 2 Control Registers Serial interface channel 2 is controlled by the following four registers. • Serial Operating Mode Register 2 (CSIM2) • Asynchronous Serial Interface Mode Register (ASIM) • Asynchronous Serial Interface Status...
Page 462 - ASIM is set with a 1-bit or 8-bit memory manipulation instruction.; Figure 20-4. Asynchronous Serial Interface Mode Register Format
462 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 <6> 5 4 3 2 1 0 <7> Symbol ASIM TXE RXE PS1 PS0 CL SL ISRM SCK FF70H 00H R/W Address After Reset R/W SCK 0 1 Clock in Asynchronous Serial Interface Mode Input clock from off-chip to ASCK pin Dedicated baud rate generator output Note ISRM 0 1 Cont...
Page 463 - Table 20-2. Serial Interface Channel 2 Operating Mode Settings
463 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 Table 20-2. Serial Interface Channel 2 Operating Mode Settings (1) Operation Stop Mode (2) 3-wire Serial I/O Mode (3) Asynchronous Serial Interface Mode Notes 1. Can be used freely as port function. 2. Can be used as P70 (CMOS input/output) when only transmi...
Page 464 - serial interface mode.
464 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (3) Asynchronous serial interface status register (ASIS) This is a register which displays the type of error when a reception error is generated in the asynchronous serial interface mode. ASIS is read with a 1-bit or 8-bit memory manipulation instruction. In...
Page 465 - BRGC is set with an 8-bit memory manipulation instruction.
465 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (4) Baud rate generator control register (BRGC) This register sets the serial clock for serial interface channel 2. BRGC is set with an 8-bit memory manipulation instruction. RESET input sets BRGC to 00H. Figure 20-6. Baud Rate Generator Control Register For...
Page 466 - -Bit Counter Source Clock Selection; must not be written to during a communication operation.
466 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 Figure 20-6. Baud Rate Generator Control Register Format (2/2) 5-Bit Counter Source Clock Selection TPS3 TPS2 TPS1 TPS0 n MCS = 1 MCS = 0 0 0 0 0 f XX /2 10 f XX /2 10 (4.9 kHz) f X /2 11 (2.4 kHz) 11 0 1 0 1 f XX f X (5.0 MHz) f X /2 (2.5 MHz) 1 0 1 1 0 f X...
Page 467 - scaled from the clock input from the ASCK pin.; Table 20-3. Relationship between Main System Clock and Baud Rate
467 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin. (a) Generation of baud rate transmit/receive clock by means of main system clock The transmit/rece...
Page 468 - : Frequency of clock input to ASCK pin
468 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (b) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is obtained with ...
Page 469 - Serial Interface Channel 2 Operation; Caution Ensure that bit 0 and bits 3 through 6 are set to 0.
469 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 20.4 Serial Interface Channel 2 Operation Serial interface channel 2 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode 20.4.1 Operation stop mode In the operation stop mode, serial trans...
Page 471 - CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction.
471 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 20.4.2 Asynchronous serial interface (UART) mode In this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is possible. A dedicated UART baud rate generator is incorporated, allowing communication over a wide r...
Page 473 - ASIS is set with an 8-bit memory manipulation instruction.
473 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (c) Asynchronous serial interface status register (ASIS) ASIS is set with an 8-bit memory manipulation instruction. RESET input sets ASIS to 00H. PE 6 5 4 3 2 1 0 7 Symbol ASIS 0 0 0 0 0 FE OVE FF71H 00H R Address After Reset R/W OVE 0 1 Overrun Error Flag O...
Page 476 - or a signal scaled from the clock input from the ASCK pin.; Table 20-5. Relationship between Main System Clock and Baud Rate
476 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin. (i) Generation of baud rate transmit/receive clock by means of main system clock The transmit/rece...
Page 478 - One data frame consists of the following bits.
478 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (2) Communication operation (a) Data format The transmit/receive data format is shown in Figure 20-7. Figure 20-7. Asynchronous Serial Interface Transmit/Receive Data Format One data frame consists of the following bits. • Start bit ................... 1 bit...
Page 479 - Even parity
479 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (b) Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd number) erro...
Page 481 - bit, reception of one frame of data ends.; the receive error state will continue indefinitely.; Parity
481 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (d) Reception When the RXE bit of the asynchronous serial interface mode register (ASIM) is set (1), a receive operation is enabled and sampling of the RxD pin input is performed. RxD pin input sampling is performed using the serial clock specified by ASIM. ...
Page 482 - INTSR; STOP
482 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (e) Receive errors Three kinds of errors can occur during a receive operation: a parity error, framing error, or overrun error. If the data reception result error flag is set in the asynchronous serial interface status register (ASIS), a receive error interr...
Page 483 - the TXE to 1, before executing the next transmission.; Whether Interrupt Request (INTSR) is Generated or Not
483 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (3) UART mode cautions (a) When transmit operation is stopped by clearing (0) bit 7 (TXE) of the asynchronous serial interface mode register (ASIM) during transmission, be sure to set the transmit shift register (TXS) to FFH, then set the TXE to 1, before ex...
Page 489 - SRIF; received bit by bit in synchronization with the serial clock.
489 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 SI2 SCK2 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO2 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SRIF Transfer Start at the Falling Edge of SCK2 End of Transfer (2) Communication operation In the 3-wire serial I/O mode, data transmission/reception is performed i...
Page 490 - Figure 20-13. Circuit of Switching in Transfer Bit Order; following two conditions are satisfied.
490 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 (3) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 20-13 shows the configuration of the transmit shift register (TXS/SIO2) and internal bus. As shown in the figure, MSB/LSB can be rea...
Page 491 - Details; Countermeasures
491 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 20.4.4 Restrictions on using UART mode In the UART mode, a receive completion interrupt request (INTSR) is generated after a certain period of time following the generation and clearing of the receive error interrupt request (INTSER). Thereby, the phenomenon...
Page 492 - T2 : The amount of time for 2 clocks of 5-bit counter source clock (f; BRGC; Example of countermeasures; An example of the countermeasures is shown below.
492 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 Figure 20-15. Period that Reading Receive Buffer Register is Prohibited T1 : The amount of time for one unit of data sent in the baud rate selected with the baud rate generator control register (BRGC) (1/baud rate) T2 : The amount of time for 2 clocks of 5-b...
Page 493 - INTSER is generated
493 CHAPTER 20 SERIAL INTERFACE CHANNEL 2 [Example] INTSER is generated 7 clocks (MIN.) of CPU clock(time from interrupt request to servicing) Instructions for2205 clocks (MIN.)of CPU clock arerequired. UART receive error interrupt request (INTSER) servicing EI RETI MOV A,RXB Main processing
Page 495 - The real-time output port consists of the following hardware.
495 CHAPTER 21 REAL-TIME OUTPUT PORT 21.1 Real-Time Output Port Functions Data set previously in the real-time output buffer register can be transferred to the output latch by hardware concurrently with timer interrupt request or external interrupt request generation, then output externally. This is...
Page 496 - CHAPTER 21 REAL-TIME OUTPUT PORT
496 CHAPTER 21 REAL-TIME OUTPUT PORT (1) Real-time output buffer register (RTBL, RTBH) Addresses of RTBL and RTBH are mapped individually in the special function register (SFR) area as shown in Figure 21-2. When specifying 4 bits x 2 channels as the operating mode, data are set individually in RTBL ...
Page 497 - Real-Time Output Port Control Registers; The following three registers control the real-time output port.; Figure 21-3. Port Mode Register 12 Format; RTPM is set with a 1-bit or 8-bit memory manipulation instruction.
497 CHAPTER 21 REAL-TIME OUTPUT PORT 21.3 Real-Time Output Port Control Registers The following three registers control the real-time output port. • Port mode register 12 (PM12) • Real-time output port mode register (RTPM) • Real-time output port control register (RTPC) (1) Port mode register 12 (PM...
Page 498 - Table 21-3. Real-time Output Port Operating Mode and Output Trigger
498 CHAPTER 21 REAL-TIME OUTPUT PORT 7 0 Symbol RTPC 6 0 5 0 4 0 3 0 2 0 <1> BYTE <0> EXTR Address FF36H 00H After Reset R/W R/W EXTR 0 1 Real-time Output Control by INTP2 INTP2 not specified as real-time output trigger INTP2 specified as real-time output trigger BYTE 0 1 Real-time Outpu...
Page 499 - The following three types of interrupt functions are used.
499 CHAPTER 22 INTERRUPT FUNCTIONS 22.1 Interrupt Function Types The following three types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally even in a disabled state. It does not undergo interrupt priority control and is given top priority ove...
Page 500 - CHAPTER 22 INTERRUPT FUNCTIONS; Interrupt Sources and Configuration; is the highest priority and 20 is the lowest priority.
500 CHAPTER 22 INTERRUPT FUNCTIONS 22.2 Interrupt Sources and Configuration There are total of 24 non-maskable, maskable, and software interrupts in the interrupt sources (see Table 22-1). Table 22-1. Interrupt Source List (1/2) Interrupt Source Name Trigger Watchdog timer overflow (with watchdog ti...
Page 504 - Interrupt Function Control Registers; to interrupt request sources.
504 CHAPTER 22 INTERRUPT FUNCTIONS 22.3 Interrupt Function Control Registers The following six types of registers are used to control the interrupt functions. • Interrupt request flag register (IF0L, IF0H, IF1L) • Interrupt mask flag register (MK0L, MK0H, MK1L) • Priority specify flag register (PR0L...
Page 505 - or upon application of RESET input.; Figure 22-2. Interrupt Request Flag Register Format
505 CHAPTER 22 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L) The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed. It is cleared to 0 when an instruction is executed upon acknowledgment of an interrup...
Page 506 - RESET input sets these registers to FFH.; Figure 22-3. Interrupt Mask Flag Register Format
506 CHAPTER 22 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L) The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service and to set standby clear enable/disable. MK0L, MK0H, and MK1L are set with a 1-bit or 8-bit memory manipulation instr...
Page 507 - Figure 22-4. Priority Specify Flag Register Format
507 CHAPTER 22 INTERRUPT FUNCTIONS (3) Priority specify flag registers (PR0L, PR0H, PR1L) The priority specify flag is used to set the corresponding maskable interrupt priority orders. PR0L, PR0H, and PR1L are set with a 1-bit or 8-bit memory manipulation instruction. If IF0L and IF0H are used as a ...
Page 508 - These registers set the valid edge for INTP0 to INTP6.; Figure 22-5. External Interrupt Mode Register 0 Format
508 CHAPTER 22 INTERRUPT FUNCTIONS Address FFECH 00H After Reset R/W R/W 0 0 1 1 INTP0 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES11 7 ES31 Symbol INTM0 6 ES30 5 ES21 4 ES20 3 ES11 2 ES10 1 0 0 0 0 1 0 1 ES10 0 0 1 1 INTP1 Valid Edge Selection Fa...
Page 509 - Figure 22-6. External Interrupt Mode Register 1 Format
509 CHAPTER 22 INTERRUPT FUNCTIONS Address FFEDH 00H After Reset R/W R/W 0 0 1 1 INTP3 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES41 7 ES71 Symbol INTM1 6 ES70 5 ES61 4 ES60 3 ES51 2 ES50 1 ES41 0 ES40 0 1 0 1 ES40 0 0 1 1 INTP4 Valid Edge Select...
Page 511 - Sampling Clock; Sampling Clock
511 CHAPTER 22 INTERRUPT FUNCTIONS t SMP Sampling Clock INTP0 PIF0 “L” Because INTP0 level is not active in sampling,PIF0 output remains at low level. When the setting INTP0 input level is active twice in succession, the noise eliminator sets interrupt request flag (PIF0) to 1. Figure 22-8 shows the...
Page 512 - interrupt servicing are mapped.
512 CHAPTER 22 INTERRUPT FUNCTIONS 7 IE PSW 6 Z 5 RBS1 4 AC 3 RBS0 2 0 1 ISP 0 CY 02H After Reset ISP 0 Used when Normal Instruction is Executed Priority of Interrupt Currently Being Received High-priority interrupt servicing(low-priority interrupt disable) 1 Interrupt request not acknowledged or lo...
Page 513 - Interrupt Servicing Operations; if multiple non-maskable interrupt requests are generated.
513 CHAPTER 22 INTERRUPT FUNCTIONS 22.4 Interrupt Servicing Operations 22.4.1 Non-maskable interrupt request acknowledge operation A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledge disable state. It does not undergo interrupt priority contro...
Page 514 - WDTM; Figure 22-11. Non-Maskable Interrupt Request Acknowledge Timing; Watchdog timer interrupt request flag
514 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-10. Flowchart from Non-Maskable Interrupt Generation to Acknowledge WDTM4 = 1 (with watchdog timer mode selected)? Overflow in WDT? WDTM3 = 0 (with non-maskable interrupt selected)? Interrupt request generation WDT interrupt servicing? Interrupt control r...
Page 515 - If a new non-maskable interrupt request is generated during
515 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-12. Non-Maskable Interrupt Request Acknowledge Operation (a) If a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution (b) If two non-maskable interrupt requests are generated during non-maskable interr...
Page 516 - Maskable interrupt request acknowledge operation
516 CHAPTER 22 INTERRUPT FUNCTIONS 22.4.2 Maskable interrupt request acknowledge operation A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the interrupt mask (MK) flag is cleared to 0. A vectored interrupt request is acknowledged in an interrupt en...
Page 517 - Start
517 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-13. Interrupt Request Acknowledge Processing Algorithm xxIF : Interrupt request flag xxMK : Interrupt mask flag xxPR : Priority specify flag IE : Flag to control maskable interrupt request acknowledge ISP : Flag to indicate the priority of interrupt being...
Page 518 - Software interrupt request acknowledge operation; and 003FH) are loaded into PC and branched.
518 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-14. Interrupt Request Acknowledge Timing (Minimum Time) Remark 1 clock: (f CPU : CPU clock) Figure 22-15. Interrupt Request Acknowledge Timing (Maximum Time) Remark 1 clock: (f CPU : CPU clock) 22.4.3 Software interrupt request acknowledge operation A sof...
Page 519 - ISP and IE are the flags contained in PSW
519 CHAPTER 22 INTERRUPT FUNCTIONS 22.4.4 Multiple interrupt servicing A multiple interrupt consists in acknowledging another interrupt during the execution of the interrupt. A multiple interrupt is generated only in the interrupt request acknowledge enable state (IE = 1) (except non- maskable inter...
Page 520 - Example 1. Two multiple interrupts generated; IE = 0 : Interrupt request acknowledge disable
520 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-16. Multiple Interrupt Example (1/2) Example 1. Two multiple interrupts generated During interrupt INTxx servicing, two interrupt requests, INTyy and INTzz are acknowledged, and a multiple interrupt is generated. An EI instruction is issued before each in...
Page 522 - requests are acknowledged.; CPU processing
522 CHAPTER 22 INTERRUPT FUNCTIONS 22.4.5 Interrupt request reserve Some instructions may reserve the acknowledge of an instruction request until the completion of the execution of the next instruction even if the interupt request is generated during the execution. The following shows such instructi...
Page 523 - Figure 22-18. Basic Configuration of Test Function
523 CHAPTER 22 INTERRUPT FUNCTIONS 22.5 Test Functions In this function, when the watch timer overflows and when a rising edge of port 4 is detected, the corresponding test input flag is set (1), and a standby release signal is generated. Unlike the interrupt function, vectored processing is not per...
Page 524 - It indicates whether a clock timer overflow is detected or not.; Figure 22-19. Format of Interrupt Request Flag Register 1L; It is set to FFH by the RESET signal input.; Figure 22-20. Format of Interrupt Mask Flag Register 1L
524 CHAPTER 22 INTERRUPT FUNCTIONS (1) Interrupt request flag register 1L (IF1L) It indicates whether a clock timer overflow is detected or not. It is set by a 1-bit memory manipulation instruction and 8-bit memory manipulation instruction. It is set to 00H by the RESET signal input. Figure 22-19. F...
Page 525 - Figure 22-21. Key Return Mode Register Format; has been applied can be checked from the KRIF status.
525 CHAPTER 22 INTERRUPT FUNCTIONS (3) Key return mode register (KRM) This register is used to set enable/disable of standby function clear by key return signal (port 4 falling edge detection). KRM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets KRM to 02H. Figure 22-2...
Page 527 - Table 23-1. Pin Functions in External Memory Expansion Mode
527 CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION 23.1 External Device Expansion Functions The external device expansion functions connect external devices to areas other than the internal ROM, RAM, and SFR. The external device expansion function can be used in the following two modes: • Multiplexed...
Page 528 - CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION; Table 23-3. Pin Functions in Separate Bus Mode
528 CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION (2) Separate bus mode External devices are connected using independent address and data buses. This connection requires no latches externally, resulting in reduction of external parts and area on the mounting board. In this mode, ports 4 through 6 an...
Page 529 - Memory map of
529 CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION Memory maps when using the external device expansion function are as follows. Figure 23-1. Memory Map when Using External Device Expansion Function (1/2) (a) Memory map of µ PD78076, 78076Y, and of µ PD78P078, 78P078Y when internal PROM capacity is 4...
Page 530 - 8P078Y when internal ROM capacity (PROM)
530 CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION Figure 23-1. Memory Map when Using External Device Expansion Function (2/2) (b) Memory map of µ PD78078, 78078Y, 78P078, (c) Memory map of µ PD78078, 78078Y and of 78P078Y when internal ROM capacity (PROM) µ PD78P078, 78P078Y when internal PROM is 56...
Page 531 - External Device Expansion Function Control Register; RESET input sets this register to 10H.; Figure 23-2. Memory Expansion Mode Register Format; for the internal ROM, RAM, and SFR areas and the reserved area.
531 CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION 23.2 External Device Expansion Function Control Register The external device expansion function is controlled by the memory expansion mode register (MM) and internal memory size switching register (IMS). (1) Memory expansion mode register (MM) MM set...
Page 532 - Figure 23-3. Internal Memory Size Switching Register Format
532 CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION 1 1 48 Kbytes 56 Kbytes Note 2 1 1 0 1 0 0 7 RAM2 Symbol IMS 6 RAM1 5 RAM0 4 0 3 ROM3 2 ROM2 1 ROM1 0 ROM0 Address FFF0H Note 1 After Reset R/W R/W Internal ROM size selection ROM3 60 Kbytes 1 ROM2 1 ROM1 1 ROM0 0 Setting prohibited Other than above ...
Page 533 - It is set by an 8-bit memory manipulation instruction.; Figure 23-4. External Bus Type Select Register Format
533 CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION (3) External bus type select register (EBTS) This register sets the operation mode of the external device expansion function. When the multiplexed bus mode is selected, the P80/A0 through P87/A7 pins can be used as an I/O port. It is set by an 8-bit ...
Page 534 - External Device Expansion Function Timing; from external memory.
534 CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION 23.3 External Device Expansion Function Timing 23.3.1 Timings in multiplexed bus mode Timing control signal output pins in the multiplexed bus mode are as follows. (1) RD pin (Alternate function: P64) Read strobe signal output pin. The read strobe si...
Page 536 - Figure 23-6. External Memory Read Timing in Multiplexed Bus Mode
536 CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION Figure 23-6. External Memory Read Timing in Multiplexed Bus Mode (a) No wait (PW1, PW0 = 0, 0) setting (b) Wait (PW1, PW0 = 0, 1) setting (c) External wait (PW1, PW0 = 1, 1) setting Higher Address ASTB RD AD0 to AD7 A8 to A15 Lower Address Read Data ...
Page 537 - Figure 23-7. External Memory Write Timing in Multiplexed Bus Mode
537 CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION Figure 23-7. External Memory Write Timing in Multiplexed Bus Mode (a) No wait (PW1, PW0 = 0, 0) setting (b) Wait (PW1, PW0 = 0, 1) setting (c) External wait (PW1, PW0 = 1, 1) setting ASTB WR AD0 to AD7 A8 to A15 Lower Address Write Data Hi-Z Higher A...
Page 541 - Figure 23-10. External Memory Read Timing in Separate Bus Mode
541 CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION Figure 23-10. External Memory Read Timing in Separate Bus Mode (a) No wait (PW1, PW0 = 0, 0) setting (b) Wait (PW1, PW0 = 0, 1) setting (c) External wait (PW1, PW0 = 1, 1) setting Note In the separate bus mode, use of the address strobe signal is not...
Page 542 - Figure 23-11. External Memory Write Timing in Separate Bus Mode
542 CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION Figure 23-11. External Memory Write Timing in Separate Bus Mode (a) No wait (PW1, PW0 = 0, 0) setting (b) Wait (PW1, PW0 = 0, 1) setting (c) External wait (PW1, PW0 = 1, 1) setting Note In the separate bus mode, use of the address strobe signal is no...
Page 545 - out intermittent operations such as watch applications.; request, it enables intermittent operations to be carried out.; the main system clock or the subsystem clock.
545 CHAPTER 24 STANDBY FUNCTION 24.1 Standby Function and Configuration 24.1.1 Standby function The standby function is designed to decrease power consumption of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. The HALT mode is intended ...
Page 546 - CHAPTER 24 STANDBY FUNCTION; Standby function control register; OSTS is set with an 8-bit memory manipulation instruction.; input or by interrupt request generation.
546 CHAPTER 24 STANDBY FUNCTION 24.1.2 Standby function control register A wait time after the STOP mode is cleared upon interrupt request till the oscillation stabilizes is controlled with the oscillation stabilization time select register (OSTS). OSTS is set with an 8-bit memory manipulation instr...
Page 547 - Standby Function Operations; Notes 1. Including case when external clock is supplied.
547 CHAPTER 24 STANDBY FUNCTION 24.2 Standby Function Operations 24.2.1 HALT mode (1) HALT mode set and operating status The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the subsystem clock. The operating status in the HALT mode is described below. ...
Page 548 - (a) Release by unmasked interrupt request; standby status is acknowledged.
548 CHAPTER 24 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released with the following four types of sources. (a) Release by unmasked interrupt request An unmasked interrupt request is generated to release the HALT mode. If interrupt request acknowledge is enabled, vectored interrupt...
Page 549 - Figure 24-3. HALT Mode Released by RESET Input; Figures in parentheses apply to operation with f
549 CHAPTER 24 STANDBY FUNCTION HALTInstruction RESETSignal OperatingMode Clock ResetPeriod HALT Mode Oscillation Oscillationstop Oscillation StabilizationWait Status OperatingMode Oscillation Wait (2 17 /f x : 26.2 ms) (d) Release by RESET input As is the case with normal reset operation, a program...
Page 550 - The operating status in the STOP mode is described below.
550 CHAPTER 24 STANDBY FUNCTION 24.2.2 STOP mode (1) STOP mode set and operating status The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock. Cautions 1. When the STOP mode is set, the X2 pin is internally connected to V DD via a pull-up resistor to m...
Page 552 - Figure 24-5. STOP Mode Released by RESET Input
552 CHAPTER 24 STANDBY FUNCTION RESETSignal OperatingMode Clock ResetPeriod STOP Mode Oscillation Stop Oscillation StabilizationWait Status OperatingMode Oscillation Wait (2 17 /f x : 26.2 ms) STOPInstruction Oscillation (c) Release by RESET input The STOP mode is released and after the lapse of osc...
Page 553 - CHAPTER 25 RESET FUNCTION; External reset input with RESET pin; Cautions 1. For an external reset, input a low level for 10
553 CHAPTER 25 RESET FUNCTION 25.1 Reset Function The following two operations are available to generate the reset signal. (1) External reset input with RESET pin (2) Internal reset by watchdog timer overrun time detection External reset and internal reset have no functional differences. In both cas...
Page 554 - CHAPTER 25 RESET FUNCTION; Figure 25-2. Timing of Reset by RESET Input
554 CHAPTER 25 RESET FUNCTION Figure 25-2. Timing of Reset by RESET Input Figure 25-3. Timing of Reset due to Watchdog Timer Overflow Figure 25-4. Timing of Reset by RESET Input in STOP Mode RESET Internal Reset Signal Port Pin Delay Delay Hi-z X1 Normal Operation Reset Period(Oscillation Stop) Osci...
Page 555 - The values after reset depend on the product.
555 CHAPTER 25 RESET FUNCTION Table 25-1. Hardware Status after Reset (1/3) Hardware Status after Reset Program counter (PC) Note 1 The contents of reset vector tables (0000H and 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) 02H Data memory Undefined Note 2 General register ...
Page 556 - Serial interface
556 CHAPTER 25 RESET FUNCTION Table 25-1. Hardware Status after Reset (2/3) Hardware Status after Reset 8-bit timer/event counters Timer register (TM5, TM6) 00H 5 and 6 Compare register (CR50, CR60) 00H Clock select register (TCL5, TCL6) 00H Mode control register (TMC5, TMC6) 00H Watch timer Mode co...
Page 559 - Table 26-1. ROM Correction Configuration
559 CHAPTER 26 ROM CORRECTION 26.1 ROM Correction Functions The µ PD78078, 78078Y Subseries can replace part of a program in the mask ROM with a program in the internal expansion RAM. Instruction bugs found in the mask ROM can be avoided, and program flow can be changed by using the ROM correction. ...
Page 560 - CHAPTER 26 ROM CORRECTION; RESET input sets CORAD0 and CORAD1 to 0000H.; Figure 26-2. Correction Address Registers 0 and 1 Format
560 CHAPTER 26 ROM CORRECTION (1) Correction address registers 0 and 1 (CORAD0, CORAD1) These registers set the start address (correction address) of the instruction(s) to be corrected in the mask ROM. The ROM correction corrects two places (max.) of the program. Addresses are set to two registers, ...
Page 561 - ROM Correction Control Registers; RESET input sets CORCN to 00H.; Figure 26-3. Correction Control Register Format
561 CHAPTER 26 ROM CORRECTION 7 0 6 0 5 0 4 0 COREN1 CORST1 COREN0 CORST0 Symbol CORCN Address FF8AH After reset COREN0 0 1 CORST0 0 1 COREN1 0 1 CORST1 0 1 R/W R/W Note 00H Correction address register 0 and fetch address match detection Not detected Detected Correction address register 0 and fetch ...
Page 562 - EEPROM; ROM Correction Application; as EEPROM; the correction branch.
562 CHAPTER 26 ROM CORRECTION V DD V DD V DD PD78078, 78078Y Subseries EEPROM SCK0 SB1 P32 SCL SDA CS CE µ RA78K/0 EEPROM Source program 00 10 0D 02 9B 02 10 00H 01H 02H FFH CSEG AT 1000H ADD A, #2 BR !1002H 26.4 ROM Correction Application (1) Store the correction address and instruction after corre...
Page 563 - expansion RAM with the main program.; Yes; ROM correction
563 CHAPTER 26 ROM CORRECTION (2) Assemble in advance the initialization routine as shown in Figure 26-6 to correct the program. Figure 26-6. Initialization Routine Note Whether the ROM correction is used or not should be judged by the port input level. For example, when the P20 input level is high,...
Page 565 - ROM Correction Example; fetch address value after the main program is started.; BR; Internal ROM
565 CHAPTER 26 ROM CORRECTION 26.5 ROM Correction Example The example of ROM correction when the instruction at address 1000H “ADD A, #1” is changed to “ADD A, #2” is as follows. Figure 26-8. ROM Correction Example (1) Branches to address F7FDH when the preset value 1000H in the correction address r...
Page 566 - Program Execution Flow; Area filled with diagonal lines : Internal expansion RAM
566 CHAPTER 26 ROM CORRECTION 26.6 Program Execution Flow Figures 26-9 and 26-10 show the program transition diagrams when the ROM correction is used. Figure 26-9. Program Transition Diagram (when One Place is Corrected) (1) Branches to address F7FDH when fetch address matches correction address (2)...
Page 567 - (2) Branches to branch destination judgment program
567 CHAPTER 26 ROM CORRECTION Figure 26-10. Program Transition Diagram (when Two Places are Corrected) (1) Branches to address F7FDH when fetch address matches correction address (2) Branches to branch destination judgment program (3) Branches to correction program 1 by branch destination judgment p...
Page 568 - Cautions on ROM Correction
568 CHAPTER 26 ROM CORRECTION 26.7 Cautions on ROM Correction (1) Address values set in correction address registers 0 and 1 (CORAD0, CORAD1) must be addresses where instruction codes are stored. (2) Correction address registers 0 and 1 (CORAD0, CORAD1) should be set when the correction enable flag ...
Page 569 - Table 27-1. Differences between PROM and Mask ROM Versions; bytes by RESET input.; consumer samples (not engineering samples) of the mask ROM version.
569 CHAPTER 27 µ PD78P078, 78P078Y The µ PD78P078 and 78P078Y (PROM versions) replace the internal mask ROM of the mask ROM versions ( µ PD78074, 78075, 78076, 78078, and µ PD78074Y, 78075Y, 78076Y, 78078Y) with one-time programmable ROM or EPROM, which enable program writing, erasure, and rewriting...
Page 570 - Internal Memory Size Switching Register; Figure 27-1. Internal Memory Size Switching Register Format
570 CHAPTER 27 µ PD78P078, 78P078Y 7 RAM2 Symbol IMS 6 RAM1 5 RAM0 4 0 3 ROM3 2 ROM2 1 ROM1 0 ROM0 Address FFF0H CFH After Reset R/W R/W 1 1 Internal ROM Capacity Selection 48 Kbytes 56 Kbytes Note ROM3 60 Kbytes 1 1 1 ROM2 1 0 1 ROM1 1 0 0 ROM0 1 Setting prohibited Other than above Internal High-Sp...
Page 571 - Internal Extension RAM Size Switching Register; Caution When the
571 CHAPTER 27 µ PD78P078, 78P078Y 7 0 Symbol IXS 6 0 5 0 4 0 3 IXRAM3 2 IXRAM2 1 IXRAM1 0 IXRAM0 Address FFF4H 0AH After Reset Internal Extension RAM Capacity Selection IXRAM3 IXRAM2 IXRAM1 1024 bytes 1 0 1 Setting prohibited Other than above IXRAM0 0 R/W W 0 bytes 1 1 0 0 27.2 Internal Extension R...
Page 572 - PROM Programming; Table 27-4. PROM Programming Operating Modes
572 CHAPTER 27 µ PD78P078, 78P078Y 27.3 PROM Programming The µ PD78P078 and 78P078Y each incorporate a 60-Kbyte PROM as program memory. To write a program into the PROM make the device enter the PROM programming mode by setting the levels of the V PP and RESET pins as specified. For the connection o...
Page 574 - N = Last address of program; Figure 27-3. Page Program Mode Flowchart
574 CHAPTER 27 µ PD78P078, 78P078Y Start Address = G V DD = 6.5 V, V PP = 12.5 V X = 0 Latch Address = Address + 1 Latch Address = Address + 1 Latch Address = Address + 1 Latch X = X + 1 0.1 ms program pulse Verify 4 bytes Pass Address = N? No Pass V DD = 4.5 to 5.5 V, V PP = V DD All bytes verified...
Page 576 - Figure 27-5. Byte Program Mode Flowchart
576 CHAPTER 27 µ PD78P078, 78P078Y Start Address = G V DD = 6.5 V, V PP = 12.5 V X = 0 X = X + 1 0.1 ms program pulse Verify Address = N ? V DD = 4.5 to 5.5 V, V PP = V DD All bytes verified? End of write Fail Fail Pass Yes All Pass No Pass Defective product No Yes X = 10 ? Address = Address + 1 G =...
Page 577 - before applying V; , and remove it after removing V; applied to V; may have an adverse affect on reliability.
577 CHAPTER 27 µ PD78P078, 78P078Y Program Program Verify A0 to A16 D0 to D7 Data Input Hi-Z Data Output V PP V DD V DD + 1.5 V DD V IH V IL V IH V IL V IH V IL V PP V DD CE PGM OE Figure 27-6. Byte Program Mode Timing Cautions 1. Apply V DD before applying V PP , and remove it after removing V PP ....
Page 578 - and V; Address Input
578 CHAPTER 27 µ PD78P078, 78P078Y 27.3.3 PROM reading procedure PROM contents can be read onto the external data bus (D0 to D7) using the following procedure. (1) Fix the RESET pin low, and supply +5 V to the V PP pin. Unused pins are handled as shown in, 1.5 (2) PROM programming mode and 2.5 Pin C...
Page 579 - Screening of One-Time PROM Versions
579 CHAPTER 27 µ PD78P078, 78P078Y 27.4 Erasure Procedure ( µ PD78P078KL-T and 78P078YKL-T Only) With the µ PD78P078KL-T or 78P078YKL-T, it is possible to erase (all contents to FFH) the data contents written in the program memory, and rewrite the memory. The data can be erased by exposing the windo...
Page 581 - CHAPTER 28 INSTRUCTION SET; This chapter describes each instruction set of the
581 CHAPTER 28 INSTRUCTION SET This chapter describes each instruction set of the µ PD78078 and 78078Y Subseries as list table. For details of its operation and operation code, refer to the separate document “78K/0 Series USER’S MANUAL — Instructions (U12326E).”
Page 582 - Legends Used in Operation List; Operand identifiers and description methods
582 CHAPTER 28 INSTRUCTION SET 28.1 Legends Used in Operation List 28.1.1 Operand identifiers and description methods Operands are described in “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications ...
Page 583 - Description of “operation” column
583 CHAPTER 28 INSTRUCTION SET 28.1.2 Description of “operation” column A : A register; 8-bit accumulator X : X register B : B register C : C register D : D register E : E register H : H register L : L register AX : AX register pair; 16-bit accumulator BC : BC register pair DE : DE register pair HL ...
Page 584 - ) selected by the processor
584 CHAPTER 28 INSTRUCTION SET 28.2 Operation List Instruction Mnemonic Operands Byte Clock Operation Flag Group Note 1 Note 2 Z AC CY 8-bit data MOV r, #byte 2 4 — r ← byte transfer saddr, #byte 3 6 7 (saddr) ← byte sfr, #byte 3 — 7 sfr ← byte A, r Note 3 1 2 — A ← r r, A Note 3 1 2 — r ← A A, sadd...
Page 592 - Instructions Listed by Addressing Type
592 CHAPTER 28 INSTRUCTION SET 28.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Page 597 - The major differences between the; Not available in the Y subseries
597 APPENDIX A DIFFERENCES BETWEEN µ PD78078, 78075B SUBSERIES, AND µ PD78070A The major differences between the µ PD78078, 78075B Subseries, and µ PD78070A are shown in Table A-1. Table A-1. Major Differences between µ PD78078, 78075B Subseries, and µ PD78070A Part Number µ PD78078 Subseries µ PD78...
Page 599 - APPENDIX B DEVELOPMENT TOOLS
599 APPENDIX B DEVELOPMENT TOOLS The following development tools are available for the development of systems which employ the µ PD78078 and 78078Y Subseries. Figure B-1 shows the configuration example of the tools.
Page 600 - APPENDIX B DEVELOPMENT TOOLS
600 APPENDIX B DEVELOPMENT TOOLS Figure B-1. Development Tool Configuration (1/2) (1) When using in-circuit emulator IE-78K0-NS PROM programming tool • PG-1500 controller Language processing software • Assembler package• C compiler package• C library source file• Device file Debugging tool • System ...
Page 602 - B.1 Language Processing Software
602 APPENDIX B DEVELOPMENT TOOLS B.1 Language Processing Software RA78K/0 A program that converts a program written in mnemonic into object Assembler Package codes that microcomputers can process. Provided with functions to automatically perform generation of symbol table, optimizing processing of b...
Page 604 - B.2 PROM Writing Tools
604 APPENDIX B DEVELOPMENT TOOLS B.2 PROM Writing Tools B.2.1 Hardware PG-1500 PROM Programmer PA-78P078GC PA-78P078GF PA-78P078KL-T PROM Programmer Adapter A PROM programmer that, by connecting the attached board and separately available PROM programmer adapter, is capable of programming single- ch...
Page 610 - I J K; note: Product by TOKYO ELETECH CORPORATION.
610 APPENDIX B DEVELOPMENT TOOLS I T E M M I L L I M E T E R S I N C H E S b 1 . 8 5 ± 0 . 2 5 0 . 0 7 3 ± 0 . 0 1 0 c 3 . 5 0 . 1 3 8 a 1 4 . 4 5 0 . 5 6 9 d 2 . 0 0 . 0 7 9 h 1 6 . 0 0 . 6 3 0 i 1 . 1 2 5 ± 0 . 3 0 . 0 4 4 ± 0 . 0 1 2 j 0 ~ 5 ° 0 . 0 0 0 ~ 0 . 1 9 7 ° e 3 . 9 0 . 1 5 4 f 0 . 2 5 g...
Page 613 - APPENDIX C EMBEDDED SOFTWARE;
613 APPENDIX C EMBEDDED SOFTWARE For efficient program development and maintenance of the µ PD78078, 78078Y Subseries, the following embedded software is available. Real-time OS (1/2) RX78K/0 A real-time OS conforming to µ ITRON specifications. Real-time OS Added with the tool (configurator) to crea...
Page 614 - APPENDIX C EMBEDDED SOFTWARE
614 APPENDIX C EMBEDDED SOFTWARE Real-time OS (2/2) MX78K0 A µ ITRON specification subset OS. Added with MX78K0 nucleus. OS Performs task management, event management, and time management. In task management, controls the execution order of tasks and performs processing to change the task to the one...
Page 616 - APPENDIX D REGISTER INDEX
616 APPENDIX D REGISTER INDEX [E] 8-bit timer mode control register 1 (TMC1) ... 233 8-bit timer mode control register 5 (TMC5) ... 256 8-bit timer mode control register 6 (TMC6) ... 257 8-bit timer output control register (TOC1) ... 234 8-bit timer register 1 (TM1) ... 230 8-bit timer register 2 (T...
Page 619 - D.2 Register Symbol Index
619 APPENDIX D REGISTER INDEX D.2 Register Symbol Index [A] ADCR: A/D conversion result register ... 295 ADIS: A/D converter input select register ... 298 ADM: A/D converter mode register ... 296 ADTC: Automatic data transmit/receive control register ... 420 ADTI: Automatic data transmit/receive int...
Page 623 - APPENDIX E REVISION HISTORY; Differences with; of AV; CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION
623 APPENDIX E REVISION HISTORY The revision history is shown below. The chapters appearing in the chapter column indicate those of the corresponding edition. Version Major revisions from previous version Chapter Second µ PD78076, 78078, 78P078: Under development → Developed µ PD78074, 78075, 78074Y...
Page 625 - Table 7-2. Relationship between CPU clock and Minimum
625 APPENDIX E REVISION HISTORY Edition Major revisions from previous edition Chapter Fourth T h e f o l l o w i n g p r o d u c t s h a v e b e e n c h a n g e d f r o m “ u n d e r development” to “already developed”. µ PD78078Y Subseries: µ PD78076Y, 78078Y, 78P078Y The following package has been...
Page 627 - Thank you for your kind support.; Document Rating; Name; Facsimile
Although NEC has taken all possible stepsto ensure that the documentation suppliedto our customers is complete, bug freeand up-to-date, we readily accept thaterrors may occur. Despite all the care andp r e c a u t i o n s w e ' v e t a k e n , y o u m a yencounter problems in the documentation.Pleas...
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