Page 3 - Cautions on CMOS Devices; Also handle boards on which MOS devices are mounted in the same way.; or GND pin through a resistor.; MS-DOS is a trademark of Microsoft Corporation.
Cautions on CMOS Devices 1 Countermeasures against static electricity for all MOSs Caution When handling MOS devices, take care so that they are not electrostatically charged. Strong static electricity may cause dielectric breakdown in gates. When transporting or storing MOS devices, use conductive ...
Page 5 - Main Revisions in This Edition; Page; Section; Major changes in this revision are indicated by stars (
Main Revisions in This Edition Page Description P.55 V SS and "Caution" have been added in (a) of Fig. 4-2 . P.329 "Caution" has been added in (2) of Section 12.4.6 . P.383 "Caution" has been added in (b) of Section 14.4.2 . P.429 Appendix B has been modified as follows: • &#...
Page 6 - PREFACE
PREFACE Users: This manual is aimed at engineers who need to be familiar with the capabilities of the µ PD78214 sub-series for application program development purposes. Purpose: The purpose of this manual is to help users understand the hardware capabilities of the µ PD78214 sub-series. Organization...
Page 8 - The following reference documents are also available.; • Documents related to the
Never use the code combinations indicated "Not to be set" in the register descriptions. Characters likely to be confused: 0 (zero) and O (uppercase "O") 1 (one), l (lowercase "L"), and I (uppercase "I") Related documents: The following reference documents are also ava...
Page 9 - Documents related to development tools
• Documents related to development tools IE-78210-R In-Circuit Emulator System Software Operator's Manual CC78K Series C Compiler User's Manual Document No. EEU-1395 EEU-1322 EEU-1331 EEP-1027 EEM-1024 EEM-1260 EEM-1027 EEU-1283 EEU-1273 EEU-1254 EEU-1289 EEU-1280 EEU-1447 EEU-1413 EF-1114 Document ...
Page 10 - Other documents
• Other documents Document No. IEI-1213 IEI-1207 IEI-1209 IEI-1203 MEI-1202 Document name Package Manual SMD Surface Mount Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Quality Assurance for Semiconductor Devices Ca...
Page 12 - Contents; CONTENTS; CHAPTER 1
- i - Contents CONTENTS CHAPTER 1 GENERAL ........................................................................................................................................ 1 1.1 FEATURES .............................................................................................................
Page 13 - CHAPTER 4
- ii - Contents 3.3 NOTES ................................................................................................................................... 53 CHAPTER 4 CLOCK GENERATOR ....................................................................................................................
Page 14 - CHAPTER 6
- iii - Contents Preface 5.8.4 Built-In Pull-Up Resistor .......................................................................................... 93 5.8.5 Notes ......................................................................................................................... 93 5.9 NOTES .....
Page 15 - CHAPTER 8
- iv - Contents 7.4.6 Sample Applications .................................................................................................. 211 7.5 NOTES ................................................................................................................................... 212 7.5.1 Com...
Page 19 - LIST OF FIGURES; Memory Map of
- viii - Contents LIST OF FIGURES Fig. No. Title, Page 2-1 I/O Circuits Provided for Pins ....................................................................................................... 34 3-1 Memory Map of µ PD78212 (EA Pin Driven High) .........................................................
Page 28 - LIST OF TABLES
- xvii - Contents LIST OF TABLES Table No. Title, Page 2-1 Port 2 Functions ............................................................................................................................. 27 2-2 Port 3 Operating Mode ........................................................................
Page 30 - CHAPTER 1 GENERAL
1 1 CHAPTER 1 GENERAL The µ PD78214 sub-series is part of the 78K/II series of eight-bit single-chip microcomputers capable of accessing an expanded memory space of 1 megabyte. This sub-series consists of the following products. The µ PD78214 offers a 16-KB masked ROM, 512-byte RAM, highly functiona...
Page 32 - Chapter 1 General
3 Chapter 1 General 1 1.1 FEATURES ° 78K/II series ° Multiplexed internal bus (faster execution of instructions) Minimum instruction cycle (operating at 12 MHz): 333 ns ( µ PD78212, µ PD78214, and µ PD78P214), or 500 ns ( µ PD78213) ° Instruction set suitable for control applications ° Data memory e...
Page 33 - ORDERING INFORMATION AND QUALITY GRADE
4 µ PD78214 Sub-Series 1.2 ORDERING INFORMATION AND QUALITY GRADE 1.2.1 Ordering Information Ordering code Package Internal ROM µ PD78212CW- ××× 64-pin plastic shrink DIP (750 mil) Masked ROM µ PD78212GC- ××× -AB8 64-pin plastic QFP (14 × 14 mm) Masked ROM µ PD78212GJ- ××× -5BJ 74-pin plastic QFP (2...
Page 36 - Remark
7 Chapter 1 General 1 (2) 68-pin plastic QFJ Remark The NC pin is not connected inside the chip. 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 P70/AN0 P34/TO0 P35/TO1 P36/TO2 P37/TO3 P00 P01 P02 P03 P04 P05 P06 P07 NC P67/REFRQ/AN7 P66/WAIT/AN6 P65/WR 60 59 58 57 56 55 54 53 52 51 50 49 48 47 4...
Page 40 - : Connect the corresponding pin independently to V; : Connect the corresponding pin to V; Open : Leave the corresponding pin unconnected.
11 Chapter 1 General 1 1.3.2 PROM Programming Mode (P20/NMI = 12.5 V, RESET = L) (1) 64-pin plastic shrink DIP, 64-pin plastic QUIP, 64-pin ceramic shrink DIP with window Caution The symbols enclosed in parentheses indicate that the corresponding pins, not used in PROM programming mode, shall be han...
Page 44 - : Programming power supply
15 Chapter 1 General 1 V PP : Programming power supply RESET : Reset D0-D7 : Data bus A0-A14 : Address bus V SS : Ground OE : Output enable V DD : Power supply CE : Chip enable P20/NMI : Port 2/non-maskable interrupt NC : Non-connection
Page 46 - Notes
17 Chapter 1 General 1 1.5 BLOCK DIAGRAM Notes 1. None for µ PD78213 and µ PD78213(A), 8KB for µ PD78212 and µ PD78212(A), 16KB for µ PD78214, µ PD78P214, µ PD78214(A) 2. Internal dual-port RAM 3. Peripheral RAM (PRAM). 128 bytes for µ PD78212 and µ PD78212(A), 256 bytes for µ PD78213, µ PD78214, µ ...
Page 47 - Note
18 µ PD78214 Sub-Series 1.6 FUNCTIONS Item Input pins Output pins I/O pins Total Connected to a pull-up resistor Driving a LED directly Driving a transistor directly 65 µ PD78213 µ PD78212 µ PD78214 µ PD78P214 Real-time output ports General-purpose registers Timer/counters 333 ns 500 ns 8K bytes 16K...
Page 49 - DIFFERENCES BETWEEN THE; AND
20 µ PD78214 Sub-Series Product Item RAM capacity I/O pins Timer/counter Serial interface Interrupt A/D converter Package Others µ PD78213 512 bytes • Software programmable pull-up resistors: Supported • Transistor direct drive outputs: Supported PWM/PPG output: Supported Scaler for the baud rate ge...
Page 50 - DIFFERENCES BETWEEN THE
21 Chapter 1 General 1 Series name µ PD78214 Sub-Series µ PD78218A Sub-Series µ PD78214 µ PD78214(A) µ PD78218A Product µ PD78212 µ PD78212(A) µ PD78213 µ PD78213(A) µ PD78P214 µ PD78P214(A) µ PD78217A µ PD78P218A Minimum instruction cycle(when operating at 12 MHz) 333 ns 500 ns 333 ns 333 ns 500 ns...
Page 51 - DIFFERENCES BETWEEN THE
22 µ PD78214 Sub-Series Product Item Quality grade Package Standard • 64-pin plastoc shrink DIP • 64-pin plastic QFP • 74-pin plastic QFP µ PD78212 µ PD78212(A) Special • 64-pin plastoc shrink DIP • 64-pin plastic QFP Product Item Quality grade Maximum period in which 74- pin plastic QFPs can be sol...
Page 52 - DIFFERENCES BETWEEN THE
23 Chapter 1 General 1 Product name Parameter Internal ROM Internal RAM Port 4 Port 5 Port 6 Others 8KB masked ROM at 00000H to 01FFFH 384 bytes at 0FD80H to 0FEFFH Used as both general-purpose I/O port (P40 to P47) and address/data bus (AD0 to AD7) Used as both general-purpose I/O port (P50 to P57)...
Page 55 - (2) Pins other than those which function as ports
26 µ PD78214 Sub-Series (2) Pins other than those which function as ports TO0-TO3 CI RxD TxD ASCK SB0 SI SO SCK NMI INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 AD0-AD7 A8-A15 A16-A19 RD WR WAIT ASTB REFRQ RESET X1 X2 AN0-AN5 AN6, AN7 AV REF AV SS V DD V SS NC P34-P37 P23/INTP2 P30 P31 P25/INTP4 P33/SO P27 P...
Page 56 - Chapter 2 Pin Functions; Table 2-1 Port 2 Functions
27 Chapter 2 Pin Functions 2 2.1.2 PROM Programming Mode (only for the µ PD78P214, P20/NMI = 12.5 V, RESET = L) Pin P20/NMI RESET A0-A14 D0-D7 CE OE V PP V DD V SS NC Function Address bus Data bus PROM enable input Read strobe to PROM Power for programming Main power Ground — Input Input/output Inpu...
Page 59 - register controls this pin.
30 µ PD78214 Sub-Series (6) P60 to P67 (port 6): Output (P60 to P63) and tristate inputs/outputs (P64 to P67) Port 6 is an eight-bit I/O port with output latches. Pins P64 to P67 are provided with software-programmablepull-up resistors. The pins of port 6 also function as control signal input pins, ...
Page 61 - Not connected inside the chip.
32 µ PD78214 Sub-Series (9) V SS Ground. (10) NC (non-connection) Not connected inside the chip.
Page 62 - pin through a resistor of less than 100 kilohms.
33 Chapter 2 Pin Functions 2 2.3 I/O CIRCUITS AND UNUSED-PIN HANDLING Table 2-4 lists the types of I/O circuits provided for each pin and describes how pins are handled when not used.Fig. 2-1 illustrates the I/O circuit types. Table 2-4 Types of I/O Circuits and Unused-Pin Handling P00-P07 P20/NMI P...
Page 64 - pin through a resistor of
35 Chapter 2 Pin Functions 2 2.4 NOTES (1) While the RESET signal is being applied, pins P60 to P63 are high impedance. When the RESET signal is released, the output of these pins is low level. Design the peripheral circuit so that it operates satisfactorilywhen pins P60 to P63 initially output the ...
Page 66 - CHAPTER 3 CPU FUNCTION; The
37 3 CHAPTER 3 CPU FUNCTION 3.1 MEMORY SPACE The µ PD78214 can access a memory space of up to 1M byte. Figs. 3-1 to 3-4 show the corresponding memory maps. The mapping of program memory depends on the status of the EA pin. The EA pin of the µ PD78213 must be tied low. (1) µ PD78212 Program memory is...
Page 68 - Chapter 3 CPU Function
39 Chapter 3 CPU Function 3 Fig. 3-2 Memory Map of µ PD78212 (EA Pin Driven Low) Notes 1. Accessed in 1M-byte expansion mode. 2. External SFR area Remark The shaded areas indicate internal memory. FFFFFH 10000H 0FFFFH 0FFDFH 0FFD0H 0FF00H 0FEFFH 0FD80H 0FD7FH 00000H Data memory Expansion address Dat...
Page 72 - This area consists of the following two RAMs:; Caution Program fetch from the internal RAM area is prohibited.; PD78212) is an external memory space that can be; External Extension Data Memory Space
43 Chapter 3 CPU Function 3 3.1.2 Internal RAM Area A 512-byte (384-byte for the µ PD78212) general-purpose static RAM is incorporated into the area from 0FD00H to 0FEFFH. This area consists of the following two RAMs: ° Peripheral RAM (PRAM) : 0FD00H to 0FDFFH (0FD80H to 0FDFFH for the µ PD78212) ° ...
Page 73 - Example; Fig. 3-5 Sample Data Transfer between Banks
44 µ PD78214 Sub-Series To access the space, specify the bank to be used (high-order four bits of address, A16 to A19) in the bank register(P60 to P63 of register P6, or PM60 to PM63 of register PM6). Then, execute an instruction which allows extendedaddressing. The high-order four bits of address o...
Page 74 - Fig. 3-6 Configuration of the Program Counter; Fig. 3-7 Configuration of the Program Status Word
45 Chapter 3 CPU Function 3 3.2 REGISTERS 3.2.1 Program Counter (PC) This 16-bit binary counter holds the address of the program to be executed next (see Fig. 3-6 ). Usually, the address is automatically incremented according to the number of bytes of the instruction to befetched. If an instruction ...
Page 75 - Fig. 3-8 Configuration of the Stack Pointer
46 µ PD78214 Sub-Series (3) Register bank selection flags (RBS0, RBS1) These two flags are used to select one of four register banks (see Table 3-2 ). The flags hold two-bit information indicating the register bank selected by the SEL RBn instruction. Table 3-2 Selecting a Register Bank 0 0 1 1 Regi...
Page 76 - Fig. 3-10 Data Restored from the Stack Area
47 Chapter 3 CPU Function 3 Fig. 3-9 Data Saved to the Stack Area Fig. 3-10 Data Restored from the Stack Area PUSH rp instruction Stack Register pair, low Register pair, high SP – 2 SP – 1 SP ⇒ SP ← SP – 2 ↑ ↑ CALL, CALLF, and CALLT instructions Stack PC7-PC0 PC15-PC8 SP – 2 SP – 1 SP ⇒ SP ← SP – 2 ...
Page 77 - When RESET is input, register bank 0 is specified.
48 µ PD78214 Sub-Series Fig. 3-11 Configuration of General-Purpose Registers A E1H B E3H D E5H H E7H A E9H B EBH D EDH H EFH A F1H B F3H D F5H H F7H A F9H B FBH D FDH H FFH X E0H C E2H E E4H L E6H X E8H C EAH E ECH L EEH X F0H C F2H E F4H L F6H X F8H C FAH E FCH L FEH AX BC DE HL AX BC DE HL AX BC D...
Page 78 - The registers have different functions as described below:
49 Chapter 3 CPU Function 3 (2) Function General-purpose registers can be operated in units of eight bits. They can also be operated in units of 16 bits,that is, a pair of eight-bit registers can be operated as a single unit (AX, BC, DE, HL). Each register can temporarily hold operation results or c...
Page 79 - : Whether the contents of the SFR can be read or written
50 µ PD78214 Sub-Series 3.2.5 Special Function Registers (SFR) A mode register, control register, and other registers with special functions, which are built-in hardwareperipherals, are mapped into the 256-byte space from 0FF00H to 0FFFFH. Caution Never access an address to which no SFR is mapped in...
Page 82 - A program fetch from the internal RAM area is prohibited.
53 Chapter 3 CPU Function 3 3.3 NOTES (1) A program fetch from the internal RAM area is prohibited. (2) Operation of the stack pointer In stack addressing, the entire 64K bytes can be accessed. No stack area can be mapped into the SFR areaor internal ROM area. (3) Special function register (SFR) Nev...
Page 84 - Fig. 4-1 Block Diagram of Clock Generator; for the; • Minimize the wiring length.; . Do not ground the capacitors to a ground pattern
55 4 CHAPTER 4 CLOCK GENERATOR 4.1 CONFIGURATION AND FUNCTION A clock generator generates and controls the internal system clock (CLK) sent to the CPU. Fig. 4-1 shows theconfiguration of the clock generator. Fig. 4-1 Block Diagram of Clock Generator Remarks f XX : Crystal/ceramic oscillation frequen...
Page 86 - Chapter 4 Clock Generator; Fig. 4-4 Notes on Connection of the Oscillator; Fig. 4-5 Incorrect Oscillator Connections
57 Chapter 4 Clock Generator 4 Fig. 4-4 Notes on Connection of the Oscillator X2 PD78214 µ X1 V SS Cautions 1. Place the oscillator as close as possible to pins X1 and X2. 2. Do not let other signal lines cross the circuit enclosed in a dashed line. Fig. 4-5 Incorrect Oscillator Connections (a) The ...
Page 87 - At power on
58 µ PD78214 Sub-Series ( c) A varying high current flows too close to the signal line. (d) A current flows through the ground line of the oscillator. (The potentials vary at points A, B, and C.) (e) A signal is being drawn from the oscillator. (2) At power-on or return from STOP mode, some time is ...
Page 88 - CHAPTER 5 PORT FUNCTIONS
59 5 CHAPTER 5 PORT FUNCTIONS 5.1 DIGITAL I/O PORTS The µ PD78214 has the ports shown in Fig. 5-1. These ports can be used for various types of control. Table 5-1 lists the function of each port. For ports 2 through 6, software can specify whether to use a built-in pull-up resistor forinputs. Fig. 5...
Page 89 - Table 5-1 Port Functions
60 µ PD78214 Sub-Series Table 5-1 Port Functions Port 0 Port 2 Port 3 Port 4 Note Port 5 Note Port 6 Note Port 7 Software-specified pull-up resistor Name Pin name P00-P07 P20-P27 P30-P37 P40-P47 P50-P57 P60-P63 P64-P67 P70-P75 Function Can be specified for either output in 8-bit units or high impeda...
Page 90 - Chapter 5 Port Functions
61 Chapter 5 Port Functions 5 5.2.1 Hardware Configuration Fig. 5-2 shows the hardware configuration of port 0. Fig. 5-2 Configuration of Port 0 5.2.2 Setting the Input/Output Mode and Control Mode The port 0 mode register (PM0) sets the I/O mode of port 0, as shown in Fig. 5-3. This register is set...
Page 92 - malfunction due to noise.; (b) Function as a control signal input pin; • INTP5: A/D converter external trigger input
63 Chapter 5 Port Functions 5 5.3 PORT 2 Port 2 is an 8-bit input-only port. P22 through P27 have a software-programmable built-in pull-up resistor. Inaddition to functioning as an input port, port 2 functions as a control signal input pin such as for external interrupts(see Table 5-3 ). All the 8 i...
Page 93 - Fig. 5-6 shows the configuration of port 2; Setting the Input Mode and Control Mode; for
64 µ PD78214 Sub-Series 5.3.1 Hardware Configuration Fig. 5-6 shows the configuration of port 2 Fig. 5-6 Block Diagram of Port 2 Note P20 or P21 does not have a circuit enclosed in a dotted box. 5.3.2 Setting the Input Mode and Control Mode Port 2 is an input-only port. There is no register to speci...
Page 94 - Fig. 5-7 Port Specified as an Input Port
65 Chapter 5 Port Functions 5 Fig. 5-7 Port Specified as an Input Port Caution For the in-circuit emulator, the level of each port 2 pin from which noise has not been removed can be read and tested. 5.3.4 Built-In Pull-Up Resistor P22 through P27 have built-in pull-up resistors. When they must be pu...
Page 95 - In addition to I/O functions, each pin works as control signal pin.
66 µ PD78214 Sub-Series Fig. 5-9 Connection of Pull-Up Resistors (Port 2) Caution P22 through P26 are not pulled up immediately after a reset. In this case, INTP1 through INTP5 (one of the multiple functions assigned to P22 to P26) may set interrupt request flags. To avoid this problem, specify use ...
Page 96 - The TO0 through TO3 pins are timer output pins.
67 Chapter 5 Port Functions 5 Table 5-4 Port 3 Operating Modes (n = 0 through 7) Condition P30 P31 P32 P33 P34 P35 P36 P37 Mode Control signal I/O mode PMC3n = 1 RxD input TxD output SCK I/O SO output or SB0 I/O TO0 output TO1 output TO2 output TO3 output Port mode PMC3n = 0 I/O port (a) Port mode I...
Page 102 - Port 3 is an I/O port. Its pins also function as control signal pins.; Fig. 5-16 Port Specified as an Output Port; Caution; Fig. 5-17 Port Specified as an Input Port
73 Chapter 5 Port Functions 5 5.4.3 Operation Port 3 is an I/O port. Its pins also function as control signal pins. (1) Output port When port 3 is in the output mode, its output latch is operable. Once the output latch becomes operable, datacan be transferred between the output latch and the accumul...
Page 103 - Fig. 5-18 Port Specified as a Control Signal Input or Output
74 µ PD78214 Sub-Series (3) Control signal input or output Regardless of setting of the port mode 3 register (PM3), each bit of port 3 can be used to input or output acontrol signal, independently of the other bits, by setting the corresponding bit of the port mode controlregister (PMC3) to 1. When ...
Page 104 - For the
75 Chapter 5 Port Functions 5 Fig. 5-20 Connection of Pull-Up Resistors (Port 3) 5.5 PORT 4 Port 4 is an 8-bit I/O port with an output latch. The memory expansion mode register (MM) can put all 8 bits ofthis port in either the input or output mode at one time. Each pin has a software-programmable bu...
Page 106 - Fig. 5-22 Port Specified as an Output Port
77 Chapter 5 Port Functions 5 5.5.3 Operation Port 4 is an I/O port. It functions also as an address/data bus (AD0 through AD7). (1) Output port When port 4 is in the output mode, its output latch is operable. Once the output latch becomes operable, datacan be transferred between the output latch an...
Page 107 - Do not execute I/O instructions for port 4.; Caution For the
78 µ PD78214 Sub-Series (3) Address/data bus (AD0 through AD7) Port 4 is used as the address/data automatically for external access. Do not execute I/O instructions for port 4. 5.5.4 Built-In Pull-Up Resistor Port 4 has built-in pull-up resistors. When port 4 must be pulled up, the built-in pull-up ...
Page 108 - Fig. 5-26 Example of Driving an LED Directly
79 Chapter 5 Port Functions 5 Fig. 5-25 Connection of Pull-Up Resistors (Port 4) 5.5.5 Driving LEDs Directly For port 4, the low level side of the output buffer has an enhanced driving capacity so that it can drive an LED directlyon an active-low signal. Fig. 5-26 is an example of such an output buf...
Page 110 - Table 5-6 Port 5 Operating Modes; Fig. 5-29 Port Specified as an Output Port
81 Chapter 5 Port Functions 5 Fig. 5-28 Port 5 Mode Register Format Table 5-6 Port 5 Operating Modes 1 1 0 0 1 × MM2 0 1 × MM1 × 1 × MM0 EA pin MM register bit Operation mode I/O port Address/data bus (A8-A15) For the µ PD78213, port 4 functions only as the address/data bus (AD8 through AD15). 5.6.3...
Page 111 - Fig. 5-30 Port Specified as an Input Port
82 µ PD78214 Sub-Series Fig. 5-30 Port Specified as an Input Port Caution Although its ultimate purpose is to manipulate only 1 bit, a bit manipulation instruction accesses a port in 8-bit units. If a bit manipulation instruction is used for a port some pins of which are in the output mode and the o...
Page 112 - Fig. 5-33 Example of Driving an LED Directly
83 Chapter 5 Port Functions 5 Fig. 5-32 Connection of Pull-Up Resistors (Port 5) 5.6.5 Driving LEDs Directly For port 5, the low level side of the output buffer has an enhanced driving capacity so that it can drive an LED directlyon an active-low signal. Fig. 5-33 is an example of such an output buf...
Page 113 - the other models, it operates when the external memory is expanded.
84 µ PD78214 Sub-Series 5.7 PORT 6 Port 6 is an 8-bit I/O port with an output latch. P64 through P67 have a software-programmable built-in pull-upresistor. In addition to the port functions, port 5 works as I/O pins for various control signals as listed in Table 5-7. Eachcontrol pin is operated by t...
Page 114 - These pins receive analog signals for the A/D converter.
85 Chapter 5 Port Functions 5 (vi) AN6 and AN7 (analog input) These pins receive analog signals for the A/D converter. 5.7.1 Hardware Configuration Fig. 5-34 through 5-37 show the hardware configuration of port 6. Fig. 5-34 Block Diagram of P60 through P63 (Port 6) P6nn = 0, 1, 2, 3 WR MM6 Memory ex...
Page 117 - P66 and P67 can always receive analog signals.; Chapter 8
88 µ PD78214 Sub-Series Fig. 5-37 Block Diagram of P67 (Port 6) 5.7.2 Setting the I/O Mode and Control Mode The port 6 mode register (PM6) can put port 6 in either the input or output mode as shown in Fig. 5-38. Table 5-8 lists the operations needed to make port 6 function as control pins. P66 and P...
Page 118 - circuit emulator may not work.
89 Chapter 5 Port Functions 5 Cautions 1. To use P60 through P63 as an output port, it is necessary to reset the PM60 through PM63 bits to 0. If they are not 0, the in- circuit emulator may not work. 2. To use the P66/WAIT pin as the WAIT pin, it is necessary to put P66 in the input mode using the P...
Page 119 - Port 6 is an I/O port. Its pins also function as control signal pins.; Fig. 5-39 Port Specified as an Output Port
90 µ PD78214 Sub-Series 5.7.3 Operation Port 6 is an I/O port. Its pins also function as control signal pins. (1) Output port When port 6 is in the output mode, the contents of its output latch are output, and data can be transferredbetween the output latch and the accumulator using a transfer instr...
Page 121 - through AV; to these pins, if AN6 and AN7 are selected
92 µ PD78214 Sub-Series 5.7.5 Note When P66 and P67 are used as analog input pins AN6 and AN7 respectively or when A/D conversion is notperformed, do not apply a voltage out of the range AV SS through AV REF to these pins, if AN6 and AN7 are selected for ANI0 through ANI2 of the A/D converter mode r...
Page 122 - Fig. 5-44 Port Specified as an Input Port
93 Chapter 5 Port Functions 5 5.8.3 Operation Port 7 is an input-only port, and the level of its pins can be read and tested. Fig. 5-44 Port Specified as an Input Port Internal bus RD IN P7nn = 0 to 5 5.8.4 Built-In Pull-Up Resistor Port 0 has no built-in pull-up resistor. 5.8.5 Notes (1) When P70 t...
Page 124 - • 4 bits
95 6 CHAPTER 6 REAL-TIME OUTPUT FUNCTION 6.1 CONFIGURATION AND FUNCTION The real-time output function is implemented by the hardware centering around port 0 and the buffer register (P0Hand P0L) as shown in Fig. 6-1. The term real-time output function refers to a function that transfers data in the b...
Page 126 - Chapter 6 Real-Time Output Function; When the RESET signal is input, the RTPC is reset to 00H.
97 Chapter 6 Real-Time Output Function 6 6.2 REAL-TIME OUTPUT CONTROL REGISTER (RTPC) The real-time output control register (RTPC) is an 8-bit register to specify the functions of port 0. An 8-bitmanipulation instruction and a bit manipulation instruction can be used to read data from and write data...
Page 127 - Example of setting data in the buffer registers
98 µ PD78214 Sub-Series Table 6-1 Port 0 Operating Modes and Operations Needed for the Port 0 Buffer Registers 8-bit port mode 8-bit real-time output port mode 4-bit separate real-time output port mode P00-P03: Port P04-P07: Real-time output port mode P00-P03: Real-time output port mode P04-P07: Por...
Page 131 - APPLICATION EXAMPLE; See
102 µ PD78214 Sub-Series 6.5 APPLICATION EXAMPLE This section describes an example of application in which P00 through P03 are used as a 4-bit real-time output port. Each time TM1 for 8-bit timer/counter 1 coincides with the contents of CR10, the contents of the P0L are outputto P00 through P03. At ...
Page 134 - See the notes in
105 Chapter 6 Real-Time Output Function 6 (4) With an in-circuit emulator, digital noise cannot be eliminated normally from the INTP0 pin. When it is specified that data transfer from the buffer register to the output latch be performed according to a signal fromthe INTP0 pin, data transfer may occu...
Page 136 - CHAPTER 7 TIMER/COUNTER UNITS
107 7 CHAPTER 7 TIMER/COUNTER UNITS The µ PD78214 contains one 16-bit timer/counter unit (channel) and three 8-bit timer/counter units (channels). Table 7-1 Timer/Counter Types and Functions Unit Types and functions 16-bit timer/ counter 2 ch — — 2 ch ° ° — ° 2 — 2 ch — — — — — ° ° 2 — 2 ch ° ° 2 ch...
Page 138 - Chapter 7 Timer/Counter Units; • PWM output
109 Chapter 7 Timer/Counter Units 7 7.1 16-BIT TIMER/COUNTER 7.1.1 Functions The 16-bit timer/counter can function as an interval timer and can also be used for programmable square waveoutput and pulse width measurement. In addition to these basic functions, the 16-bit timer/counter can be usedfor t...
Page 140 - TM0 is a count-up timer using a count clock of f; The edge detector detects a valid edge of an external input signal.
111 Chapter 7 Timer/Counter Units 7 (1) 16-bit timer 0 (TM0) TM0 is a count-up timer using a count clock of f CLK /8. The count operation of TM0 can be enabled or disabled by timer control register 0 (TMC0). TM0 allows only read operation using a 16-bit manipulation instruction. When the RESET signa...
Page 142 - When the RESET signal is applied, the TOC register is cleared to 00H.
113 Chapter 7 Timer/Counter Units 7 (3) Timer output control register (TOC) The TOC register is an 8-bit register for specifying the active level of timer output and for enabling/disablingtimer output. The lower 4 bits control the timer output operation (on the TO0 and TO1 pins) of the 16-bit timer/...
Page 143 - count stop; (b) When the CE0 bit is set to 1 again after count operation starts
114 µ PD78214 Sub-Series 7.1.4 Operation of 16-Bit Timer 0 (TM0) (1) Basic operation The 16-bit timer/counter performs count operation by counting up with a count clock of f CLK /8. When the RESET signal is applied, TM0 is cleared to 0000H, and count operation stops. Bit 3 (CE0) of timer control reg...
Page 145 - Fig. 7-8 Clear Operation When the CE0 Bit Is Reset to 0; (b) Restart after 0 is set in TM0 cleared
116 µ PD78214 Sub-Series Fig. 7-8 Clear Operation When the CE0 Bit Is Reset to 0 (a) Basic operation TM0 CE0 n-1 n 0 Count clock (b) Restart after 0 is set in TM0 cleared Count clock TM0 CE0 n-1 n 0 0 1 When the CE0 bit is set to 1 after this count clock, counting starts from 0 on the count clock in...
Page 146 - Compare Register and Capture Register Operations
117 Chapter 7 Timer/Counter Units 7 7.1.5 Compare Register and Capture Register Operations (1) Compare operation The 16-bit timer/counter performs an operation to compare the values set in the compare registers with timercount values. When the values set in the compare registers (CR00, CR01) coincid...
Page 147 - Fig. 7-10 TM0 Cleared After a Coincidence Is Detected; For the detailed format of the INTM1 register, see
118 µ PD78214 Sub-Series Fig. 7-10 TM0 Cleared After a Coincidence Is Detected Remark CLR01 = 1 (2) Capture operation The 16-bit timer/counter performs a capture operation to load the count value of the timer into the captureregister in synchronism with an external trigger. As an external trigger, a...
Page 148 - Basic Operation of Output Control Circuit
119 Chapter 7 Timer/Counter Units 7 Fig. 7-11 Capture Operation Remark Dn: TM0 count value (n = 0, 1, 2, ...) CLR01 = 0 Caution With an in-circuit emulator, digital noise on the INTP3 pin cannot be removed correctly. When the capture function is used, the operation described below is performed if an...
Page 149 - Remarks
120 µ PD78214 Sub-Series Table 7-5 Timer Output (TO0, TO1) Operation TOC 0 0 1 1 0 1 1 0 1 1 0 1 1 ENTO1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 AL V1 0 1 0 1 1 0 1 1 0 1 1 0 1 ENTO0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 AL V0 × 0 0 0 0 0 0 1 1 1 1 1 1 MOD1 × 0 0 0 1 1 1 0 ...
Page 151 - for the inactive level. Take this point
122 µ PD78214 Sub-Series 7.1.7 PWM Output The PWM output function outputs a PWM signal whose period coincides with the full-count period of 16-bit timer0 (TM0). The pulse width of TO0 is determined by the value of CR00, and the pulse width of TO1 is determinedby the value of CR01. Before this functi...
Page 152 - Fig. 7-14 Example of PWM Output Using TM0
123 Chapter 7 Timer/Counter Units 7 Fig. 7-14 Example of PWM Output Using TM0 Remark ALV0 = 0, ALV1 = 0 Fig. 7-15 PWM Output When CR00 = FFFFH Remark ALV0 = 0 FFFFH INTO00 FFFFH FFFFH FFFFH FFFFH TO0 TM0count value Count clock period T OVF flag Duty factor = × 100 = 99.998(%) 0 1 2 0 1 2 0 Pulse wid...
Page 154 - The pulse period and pulse width are as follows:; Fig. 7-18 Example of PPG Output Using TM0
125 Chapter 7 Timer/Counter Units 7 2. If timer output is disabled (ENTOn = 0: n = 0, 1), the output level on the TOn (n = 0, 1) pin is the inverted value of the value set in ALVn (n = 0, 1). Accordingly, note that if timer output is disabled when the PWM output function is selected, the active leve...
Page 156 - Fig. 7-21 Example of Rewriting Compare Register CR00; Fig. 7-22 Example of PPG Output Signal with a 100% Duty Factor
127 Chapter 7 Timer/Counter Units 7 Even if the value of the CR00 compare register coincides with the value of 16-bit timer 0 (TM0) more than onceduring one period of PPG output, the output levels on the timer outputs (TO0, TO1) are not inverted. Fig. 7-21 Example of Rewriting Compare Register CR00 ...
Page 157 - Fig. 7-23 Example of PPG Output Period Made Longer
128 µ PD78214 Sub-Series 2. If the current value of the CR01 compare register is decreased below the value of 16-bit timer 0 (TM0), the PPG period becomes as long as the full-count time of TM0. At this time, if CR01 is rewritten after the value of the CR00 compare register coincideswith the value of...
Page 158 - This interval timer has a resolution of 1.3
129 Chapter 7 Timer/Counter Units 7 7.1.9 Sample Applications (1) Interval timer operation (1) By free running 16-bit timer 0 (TM0), and adding a value to a compare register (CR00, CR01) in an interrupthandling routine, the 16-bit timer/counter can be used as an interval timer whose period is as lon...
Page 161 - This pulse width measurement allows a pulse width of 2.6; ) by the difference between the
132 µ PD78214 Sub-Series Fig. 7-29 Setting of Control Registers for Interval Timer Operation (2) (a) Timer control register 0 (TMC0) 7 6 5 4 3 2 1 0 0 0 0 0 1 0 0 1 CRC0 Clears TM0 when CR01 coincides with TM0 Both TO0 and TO1 are used for toggle output (b) Capture/compare control register 0 (CRC0) ...
Page 162 - Fig. 7-31 Timing of Pulse Width Measurement; Fig. 7-32 Setting of Control Registers for Pulse Width Measurement
133 Chapter 7 Timer/Counter Units 7 Fig. 7-31 Timing of Pulse Width Measurement Remark D n : TM0 count value (n = 0, 1, 2, ...) Fig. 7-32 Setting of Control Registers for Pulse Width Measurement (a) Timer control register 0 (TMC0) (b) Capture/compare control register 0 (CRC0) 7 6 5 4 3 2 1 0 0 0 0 0...
Page 164 - Fig. 7-36 Setting of Control Registers for PWM Output Operation
135 Chapter 7 Timer/Counter Units 7 (4) PWM output operation In PWM output operation, a pulse signal with a duty factor determined by the value set in a compare registeris output. (See Fig. 7-35 .) The duty factor of a PWM output signal can be changed in steps of 1/65536 from 1/65536 to 65535/65536....
Page 166 - Fig. 7-40 Setting of Control Registers for PPG Output Operation
137 Chapter 7 Timer/Counter Units 7 (5) PPG output operation In PPG output operation, a pulse signal with a period and duty factor determined by the values set in thecompare registers is output. (See Fig. 7-39 .) Fig. 7-40 shows the setting of control registers. Fig. 7-41 shows the setting procedure...
Page 168 - Table 7-10 Pulse Width Measurement Range of 8-Bit Timer/Counter 1
139 Chapter 7 Timer/Counter Units 7 7.2 8-BIT TIMER/COUNTER 1 7.2.1 Functions Eight-bit timer/counter 1 can function as an interval timer and can also be used for pulse width measurement. Inaddition to these basic functions, 8-bit timer/counter 1 can be used as a timer for generating an output trigg...
Page 176 - Fig. 7-49 TM1 Cleared after Capture Operation; Fig. 7-50 Clear Operation When the CE1 Bit Is Reset to 0
147 Chapter 7 Timer/Counter Units 7 Fig. 7-49 TM1 Cleared after Capture Operation TM1 Count clock n-1 n 0 1 2 INTP0 TM1 is captured to CR11 here Cleared here TM1 can also be cleared by software when the CE1 bit of the timer control register (TMC1) is reset to 0.Similarly, clear operation is performe...
Page 177 - Compare Register and Capture/Compare Register Operations
148 µ PD78214 Sub-Series (b) Restart after 0 is set in TM1 cleared Count clock TM1 CE1 n-1 n 0 0 1 When the CE1 bit is set to 1 aftr this count clock, counting starts from 0 on the count clock input after the CE1 bit has been set. (c) Restart before 0 is set in TM1 cleared Count clock TM1 CE1 n-1 Wh...
Page 178 - Fig. 7-52 TM1 Cleared After a Coincidence Is Detected
149 Chapter 7 Timer/Counter Units 7 Fig. 7-51 Compare Operation Remark CLR10 = 0, CLR11 = 0, CM = 0 Caution When using an in-circuit emulator, see the notes described in Section 7.5.4. Fig. 7-52 TM1 Cleared After a Coincidence Is Detected (2) Capture operation Eight-bit timer/counter 1 performs a ca...
Page 180 - Fig. 7-54 TM1 Cleared after Capture Operations
151 Chapter 7 Timer/Counter Units 7 Fig. 7-54 TM1 Cleared after Capture Operations Remark D n : TM1 count value (n = 0, 1, 2, ...) CLR10 = 0, CLR11 = 0, CM = 1 7.2.6 Sample Applications (1) Interval timer operation (1) By free running 8-bit timer 1 (TM1), and adding a value to a compare register (CR...
Page 184 - ) loaded and held in the CR11
155 Chapter 7 Timer/Counter Units 7 Fig. 7-61 Setting Procedure for Interval Timer Operation (2) (3) Pulse width measurement operation In pulse width measurement, the width of the high level or low level of an external pulse signal applied to theexternal interrupt request (INTP0) input pin is measur...
Page 186 - Fig. 7-63 Setting of Control Registers for Pulse Width Measurement
157 Chapter 7 Timer/Counter Units 7 Fig. 7-63 Setting of Control Registers for Pulse Width Measurement (a) Timer control register 1 (TMC1) (b) Prescaler mode register 1 (PRM1) (c) Capture/compare control register 1 (CRC1) (d) External interrupt mode register 0 (INTM0) 7 6 5 4 3 2 1 0 0 0 1 0 0 CRC1 ...
Page 188 - • External event counter
159 Chapter 7 Timer/Counter Units 7 7.3 8-BIT TIMER/COUNTER 2 7.3.1 Functions Eight-bit timer/counter 2 has two functions not available with the other three timers/counters: • External event counter • One-shot timer This section describes the following four basic functions in sequence: • Interval ti...
Page 189 - Caution The values in Table 7-12 assume the use of an internal clock.; Table 7-13 Pulse Width Measurement Range of 8-Bit Timer/Counter 2
160 µ PD78214 Sub-Series (2) Programmable square wave output Eight-bit timer/counter 2 outputs a square wave separately on the TO2 and TO3 timer output pins. Table 7-12 Programmable Square Wave Output Setting Range of 8-Bit Timer/Counter 2 Maximum pulse width 2 8 × 16/f CLK (683 µ s) 2 8 × 32/f CLK ...
Page 190 - Table 7-14 Clock Signals That Can Be Applied to 8-Bit Timer/Counter 2
161 Chapter 7 Timer/Counter Units 7 (4) External event counter Eight-bit timer/counter 2 counts clock pulses (CI pin input pulses) applied to the external interrupt input pin(INTP2). Table 7-14 indicates the clock signals that can be applied to 8-bit timer/counter 2. Table 7-14 Clock Signals That Ca...
Page 197 - Fig. 7-73 TM2 Cleared after Capture Operation
168 µ PD78214 Sub-Series (c) When the value of TM2 is FFH (2) Clear operation After a coincidence with the CR21 compare register or capture operation, 8-bit timer 2 (TM2) can beautomatically cleared. If a TM2 clear cause occurs, TM2 is cleared to 00H by the next count clock pulse. Thismeans that eve...
Page 198 - Fig. 7-74 Clear Operation When the CE2 Bit Is Reset to 0; (b) Restart after 0 is set in TM2 cleared
169 Chapter 7 Timer/Counter Units 7 TM2 can also be cleared by software when the CE2 bit of the timer control register (TMC1) is reset to 0.Similarly, clear operation is performed by the count clock pulse following the resetting of CE2 bit to 0. If theCE2 bit is set to 1 before TM2 is reset to 0 by ...
Page 199 - (c) Restart before 0 is set in TM2 cleared; = 6 MHz) or more for both the high level and
170 µ PD78214 Sub-Series (c) Restart before 0 is set in TM2 cleared Count clock TM2 CE2 n-1 When the CE2 bit is set to 1 before this count clock, Clearing TM2 by CE2 ← 0 and counting by CE2 ← 1 are performed simultaneously. n 0 1 2 7.3.5 External Event Counter Function Eight-bit timer/counter 2 can ...
Page 202 - with External Event Counter
173 Chapter 7 Timer/Counter Units 7 Fig. 7-77 Example Where Input of No Valid Edge Cannot Be Distinguished from Input of Only One Valid Edge with External Event Counter Cannot be distinguished TM2 1 0 2 CI 0 Count starts Fig. 7-78 How to Distinguish Input of No Valid Edge from Input of Only One Vali...
Page 203 - • When other in-circuit emulators are used
174 µ PD78214 Sub-Series (b) Count value read processing 3. With an in-circuit emulator, digital noise on the CI/INTP2 pin cannot be removed correctly. When the event counter function is used, the operation described below is performed if an edge is detected erroneously. • When IE-78210-R is used Co...
Page 205 - Compare Register and Capture Register Operations
176 µ PD78214 Sub-Series 7.3.7 Compare Register and Capture Register Operations (1) Compare operation Eight-bit timer/counter 2 performs an operation to compare the values set in the compare registers with timercount values. When the values set in the compare registers (CR20, CR21) coincide with cou...
Page 206 - Fig. 7-81 TM2 Cleared After a Coincidence Is Detected; For the detailed format of the INTM0 register, see; Cautions
177 Chapter 7 Timer/Counter Units 7 Fig. 7-81 TM2 Cleared After a Coincidence Is Detected Remark CLR22 = 0 Caution When using an in-circuit emulator, see the notes described in Section 7.5.4. (2) Capture operation Eight-bit timer/counter 2 performs a capture operation to load the count value of the ...
Page 208 - Fig. 7-83 TM2 Cleared after Capture Operation; Basic Operation of Output Control Circuit
179 Chapter 7 Timer/Counter Units 7 Fig. 7-83 TM2 Cleared after Capture Operation Remark CLR21 = 0, CLR22 = 1 7.3.8 Basic Operation of Output Control Circuit The output control circuit controls the levels of the timer outputs (TO2, TO3) according to the coincidence signalfrom the compare registers. ...
Page 212 - Fig. 7-86 Example of PWM Output Using TM2
183 Chapter 7 Timer/Counter Units 7 Table 7-17 PWM Output on TO2 and TO3 (f CLK = 6 MHz) Count clock f CLK /16 f CLK /32 f CLK /64 f CLK /128 f CLK /256 f CLK /512 Minimum pulse width 2.7 5.3 10.7 21.3 42.7 85.3 PWM period (ms) 0.7 1.4 2.7 5.5 10.9 21.8 PWM frequency (Hz) 1465 732 366 183 92 46 Fig....
Page 213 - Fig. 7-88 Example of Rewriting a Compare Register
184 µ PD78214 Sub-Series Fig. 7-87 PWM Output When CR20 = FFH Remark ALV2 = 0 Even if the value of a compare register (CR20, CR21) coincides with the value of 8-bit timer 2 (TM2) more than onceduring one period of PWM output, the output levels on the timer outputs (TO2, TO3) are not inverted. Fig. 7...
Page 214 - Fig. 7-89 Example of PWM Output Signal with a 100% Duty Factor; for the inactive level. Take
185 Chapter 7 Timer/Counter Units 7 Cautions 1. If a value less than the value of 8-bit timer 2 (TM2) is set in a compare register (CR20, CR21), a PWM signal with a 100% duty factor is output. Rewrite the CR20 or CR21 compare register, if required, by using an interrupt generated by a coincidencebet...
Page 215 - Fig. 7-90 Example of PPG Output Using TM2
186 µ PD78214 Sub-Series Fig. 7-90 shows an example of PPG output using 8-bit timer 2 (TM2). Fig. 7-91 shows an example of PPG outputwhen CR20 = CR21. Fig. 7-92 shows an example of PPG output when CR20 = 00H. Fig. 7-90 Example of PPG Output Using TM2 Remark ALV2 = 0, ALV3 = 0 Table 7-18 PPG Output o...
Page 217 - Fig. 7-93 Example of Rewriting Compare Register CR20; Fig. 7-94 Example of PPG Output Signal with a 100% Duty Factor
188 µ PD78214 Sub-Series Even if the value of the CR20 compare register coincides with the value of 8-bit timer 2 (TM2) more than once duringone period of PPG output, the output level on the timer output (TO2) is not inverted. Fig. 7-93 Example of Rewriting Compare Register CR20 TO2 T1 T2 T1 T1 T2 T...
Page 218 - Fig. 7-95 Example of PPG Output Period Made Longer
189 Chapter 7 Timer/Counter Units 7 2. If the current value of the CR21 compare register is decreased below the value of 8-bit timer 2 (TM2), the PPG period becomes as long as the full-count time of TM2. At this time, if CR21 is rewritten after the value of the CR20 compare register coincideswith th...
Page 224 - Fig. 7-103 Timing of Pulse Width Measurement
195 Chapter 7 Timer/Counter Units 7 Fig. 7-103 Timing of Pulse Width Measurement Remark D n : TM2 count value (n = 0, 1, 2, ...) Fig. 7-104 Setting of Control Registers for Pulse Width Measurement (a) Prescaler mode register 1 (PRM1) (b) Capture/compare control register 2 (CRC2) 7 CRC2 0 0 6 5 4 3 2...
Page 225 - Fig. 7-105 Setting Procedure for Pulse Width Measurement
196 µ PD78214 Sub-Series (c) Timer control register 1 (TMC1) (d) External interrupt mode register 0 (INTM0) Fig. 7-105 Setting Procedure for Pulse Width Measurement Set CRC1 register Set INTM0 register and MK0L register CRC2 ← 10H X 0 ← 0 Initialize buffer memory for capture value Enable interrupt I...
Page 226 - Fig. 7-106 Interrupt Request Handling for Pulse Width Calculation
197 Chapter 7 Timer/Counter Units 7 Fig. 7-106 Interrupt Request Handling for Pulse Width Calculation (4) PWM output operation In PWM output operation, a pulse signal with a duty factor determined by the value set in a compare registeris output. (See Fig. 7-107 .) The duty factor of a PWM output sig...
Page 227 - Fig. 7-108 Setting of Control Registers for PWM Output Operation
198 µ PD78214 Sub-Series Fig. 7-108 Setting of Control Registers for PWM Output Operation (a) Timer control register 1 (TMC1) (b) Prescaler mode register 1 (PRM1) (c) Capture/compare control register 2 (CRC2) 7 6 5 4 3 2 1 0 1 CRC2 0 0 1 0 0 0 0 Disables clearing TM2 Both TO2 and TO3 are used for PW...
Page 228 - Fig. 7-109 Setting Procedure for PWM Output
199 Chapter 7 Timer/Counter Units 7 Fig. 7-109 Setting Procedure for PWM Output Fig. 7-110 Changing Duty Factor of PWM Output (5) PPG output operation In PPG output operation, a pulse signal with a period and duty factor determined by the values set in thecompare registers is output. (See Fig. 7-111...
Page 229 - Fig. 7-112 Setting of Control Registers for PPG Output Operation
200 µ PD78214 Sub-Series Fig. 7-112 Setting of Control Registers for PPG Output Operation (a) Timer control register 1 (TMC1) (b) Prescaler mode register 1 (PRM1) (c) Capture/compare control register 2 (CRC2) 7 6 5 4 3 2 1 0 1 CRC2 0 1 1 1 0 0 0 Clears when TM2 coincides with CR21 Disables clearing ...
Page 230 - Fig. 7-113 Setting Procedure for PPG Output
201 Chapter 7 Timer/Counter Units 7 Fig. 7-113 Setting Procedure for PPG Output Fig. 7-114 Changing Duty Factor of PPG Output (6) External event counter operation When functioning as an external event counter, 8-bit timer/counter 2 counts clock pulses externally appliedto the CI pin. As shown in Fig...
Page 231 - Fig. 7-117 Setting Procedure for External Event Counter Operation
202 µ PD78214 Sub-Series Fig. 7-116 Setting of Control Registers for External Event Counter Operation (a) Prescaler mode register 1 (PRM1) (b) External interrupt mode register 0 (INTM0) (c) Timer control register 1 (TMC1) Fig. 7-117 Setting Procedure for External Event Counter Operation 7 6 5 4 3 2 ...
Page 238 - Fig. 7-127 Clear Operation When the CE3 Bit Is Reset to 0
209 Chapter 7 Timer/Counter Units 7 (2) Clear operation After a coincidence with the CR30 compare register, 8-bit timer 3 (TM3) can be automatically cleared. If a TM3 clear cause occurs, TM3 is cleared to 00H by the next count clock pulse. This means that even if aTM3 clear cause occurs, TM3 holds t...
Page 240 - This interval timer has a resolution from 1.3; Fig. 7-129 Timing of Interval Timer Operation
211 Chapter 7 Timer/Counter Units 7 Fig. 7-128 Compare Operation 7.4.6 Sample Applications (1) Interval timer operation Eight-bit timer/counter 3 can be used as an interval timer that generates an interrupt at intervals of a counttime specified beforehand. Eight-bit timer/counter 3 can also be used ...
Page 241 - Fig. 7-131 Setting Procedure for Interval Timer Operation
212 µ PD78214 Sub-Series Fig. 7-130 Setting of Control Registers for Interval Timer Operation (a) Timer control register 0 (TMC0) (b) Prescaler mode register 0 (PRM0) 7 6 5 4 3 2 1 0 PRS3 0 0 0 0 PRM0 PRS2 PRS1 PRS0 Specifies count clock(x/f CLK ; where x = 16, 32, 64, 128, 256, or 512) Fig. 7-131 S...
Page 244 - of clock pulses; indicated below are automatically inserted.; with Timers/Counters Are Accessed
215 Chapter 7 Timer/Counter Units 7 (6) When a register associated with a timer/counter is accessed, wait states as many as the maximum number of clock pulses Note indicated below are automatically inserted. Note One wait state: 1/f CLK Table 7-20 Maximum Number of Wait States Inserted When Register...
Page 245 - Fig. 7-135 Example of PWM Output Signal with a 100% Duty Factor
216 µ PD78214 Sub-Series (9) When PWM is used, a PWM signal with a 100% duty factor is output if a value less than the value of TMn (n = 0, 2) is set in compare register CRnm (n = 0, 2, m = 0, 1). CRnm rewrite operation must be performed usingan interrupt generated by a coincidence between TMn and C...
Page 246 - Fig. 7-136 Example of PPG Output Signal with a 100% Duty Factor
217 Chapter 7 Timer/Counter Units 7 (10)Notes on compare register rewrite operation when PPG output is used (a) If a value less than the value of TMn is written into compare register CRn0 (n = 0, 2) before the value of the CRn0 register coincides with the value of TMn (n = 0, 2), a PPG signal with a...
Page 247 - Fig. 7-137 Example of PPG Output Period Made Longer; two clock pulses of f; of f; clock pulses of f
218 µ PD78214 Sub-Series Fig. 7-137 Example of PPG Output Period Made Longer n3 n1 n2 n4 n2 0H CRn0 CRn1 TOp(p = 0,2) n1 n3 n1 n4 n2 n1 Full count value n3 n5 TMn The PPG period is extended when a value,n2 less than TMn value, n5 is written toCRn1 here. TOp becomes inactive when CRn0 coincides with ...
Page 249 - Only One Valid Edge with External Event Counter
220 µ PD78214 Sub-Series Fig. 7-138 Interrupt Request Generation Using External Event Counter Countable timing of TM2 TM2 n n-1 n+1 ICI CI 8 to 12 clocks 16 clocks (Max.) Count clock of TM2 Coincidencebetween INTP2and ICI TM2 counts up hereor is compared withcompare register. ICI: Signal that has go...
Page 253 - • Clearing the CE2 bit of timer control register 1 (TMC1) to 0
224 µ PD78214 Sub-Series (c) Event counter function (with only 8-bit timer/counter 2) An erroneously detected edge causes no change in the value of the timer/counter. However, the timingfor generating an interrupt by a coincidence between the value of the timer/counter and the value of acompare regi...
Page 254 - CHAPTER 8 A/D CONVERTER; and with high accuracy.
225 8 CHAPTER 8 A/D CONVERTER The µ PD78214 contains an analog-to-digital (A/D) converter with eight multiplexed analog input pins (AN0 through AN7). This A/D converter uses successive approximation The conversion result is stored in an 8-bit A/D conversion resultregister (ADCR). Conversion can be p...
Page 256 - Chapter 8 A/D Converter; pin; Fig. 8-2 Example of Capacitors Connected to the A/D Converter Pins; Do not apply a voltage out of the rated voltage range (AV; and; pins to be divided into 256 steps.
227 Chapter 8 A/D Converter 8 Cautions 1. To prevent malfunction due to noise, insert a capacitor between each analog input pins (AN0 through AN7) and the AV SS pin and between the reference voltage input pin (AV REF ) and the AV SS pin. Fig. 8-2 Example of Capacitors Connected to the A/D Converter ...
Page 257 - When the RESET signal is input, the ADM register is reset to 00H.
228 µ PD78214 Sub-Series (7) Edge detector The edge detector detects the valid edge of an input at the interrupt request input pin (INTP5) and generatesan external interrupt request signal (INTP5) and an external trigger for A/D conversion. The valid edge of an input at the INTP5 pin is specified by...
Page 260 - A/D conversion continues until the CS bit is reset by software.
231 Chapter 8 A/D Converter 8 A/D conversion continues until the CS bit is reset by software. If data is written to the ADM register during conversion, conversion is initialized. If the CS bit is 1,conversion is started from the beginning. When the RESET signal is input, the ADCR register contents b...
Page 262 - • Use a macro service to handle the A/D conversion end interrupt.
233 Chapter 8 A/D Converter 8 8.3.3 Scan Mode In the scan mode, signals input from the analog input pins, specified by bits 1 through 3 (ANI0 through ANI2) ofthe A/D converter mode register (ADM), are selected successively for conversion. For example, when the ANI2 through ANI0 bits of the ADM regis...
Page 268 - INTERRUPT REQUEST FROM THE A/D CONVERTER; (1) Range of voltages applied to analog input pints
239 Chapter 8 A/D Converter 8 8.4 INTERRUPT REQUEST FROM THE A/D CONVERTER The A/D converter generates an A/D conversion end interrupt request (INTAD), each time a conversion sequenceis completed, except for the select mode. The interrupt control flags are shared by the INTAD interrupt and the INTP5...
Page 269 - (3) Capacitors connected to analog input pins; pin and between the reference voltage input pin (AV; Fig. 8-13 Example of Capacitors Connected to the A/D Converter Pins
240 µ PD78214 Sub-Series (2) About hardware-started A/D conversion (a) Eight to twelve system clocks are required from when a valid edge appears at the INTP5 pin until A/D conversion is actually started. Take this delay into consideration when designing your application. See Chapter 11 for details o...
Page 270 - other interrupts are being handled.
241 Chapter 8 A/D Converter 8 Fig. 8-14 Example of Malfunction in a Hardware-Started A/D Conversion Notes 1. When the operation is normal, the result of conversion 2 is stored. If a malfunction occurs, however, value 7FH is stored. 2. Time from when an input to the INT5 pin changes to when its edge ...
Page 272 - CHAPTER 9 ASYNCHRONOUS SERIAL INTERFACE
243 9 CHAPTER 9 ASYNCHRONOUS SERIAL INTERFACE The µ PD78214 contains an asynchronous serial interface, UART (Universal Asynchronous Receiver Transmitter). This interface transmits 1-byte data following a start bit and is capable of full-duplex transmission. The µ PD78214 also contains a baud rate ge...
Page 273 - Fig. 9-1 Asynchronous Serial Interface Configuration
244 µ PD78214 Sub-Series Fig. 9-1 Asynchronous Serial Interface Configuration INTST Internal bus Reception buffer RESET TXS 1/8 1/8 RXB PE FE OVE INTSR INTSER (ASIS) Transmission control parity generation P31/TxD P30/RxD 1 16 1 16 Selector Transmission shift register Asynchronous serial interface st...
Page 274 - Chapter 9 Asynchronous Serial Interface; The shift register cannot be manipulated directly from the CPU.; (5) Transmission control parity generation; The selector selects a baud rate clock source.; ASYNCHRONOUS SERIAL INTERFACE CONTROL REGISTER; When the RESET signal is input, the ASIM register is set to 80H.
245 Chapter 9 Asynchronous Serial Interface 9 (1) Reception buffer (RXB) The reception buffer holds the receive data. Each time the shift register receives 1 byte of data, it sends it tothis reception buffer. If the data length is specified to be 7 bits, the receive data is sent to bits 0 through 6 ...
Page 275 - disable reception beforehand.; When the RESET signal is input, the ASIS register is reset to 00H.
246 µ PD78214 Sub-Series Fig. 9-2 Format of the Asynchronous Serial Interface Mode Register (ASIM) Cautions 1. The asynchronous serial interface mode register (ASIM) must not be modified during transmission. If the ASIM register is modified during transmission, further transmission becomes impossibl...
Page 276 - the next data is received, and the error status will persist.; ASYNCHRONOUS SERIAL INTERFACE OPERATIONS; • Start bit : 1 bit; Even parity
247 Chapter 9 Asynchronous Serial Interface 9 Fig. 9-3 Format of the Asynchronous Serial Interface Status Register (ASIS) Caution Be sure to read the reception buffer (RXB) contents, even if a reception error occurs. Otherwise, an overrun error will occur when the next data is received, and the erro...
Page 277 - The asynchronous serial interface for the
248 µ PD78214 Sub-Series • Odd parity In contrast to even parity, the parity bit for odd parity is controlled so that the number of 1 bits in the transmitdata becomes odd. When data is received, the number of 1 bits in it is counted, and if the number of 1 bits iseven, a parity error is detected. • ...
Page 279 - Table 9-1 Causes of Reception Errors
250 µ PD78214 Sub-Series Table 9-1 Causes of Reception Errors Parity error Framing error Overrun error The parity of the receive data does not match the type of parity specified at transmission. No stop bit is detected Note . Before the receive data is read out from the reception buffer, the next da...
Page 280 - BAUD RATE GENERATOR; Fig. 9-8 Baud Rate Generator Clock Configuration; ). It generates a signal having the frequency selected; When the RESET signal is input, the BRGC register is reset to 00H.
251 Chapter 9 Asynchronous Serial Interface 9 9.4 BAUD RATE GENERATOR 9.4.1 Configuration of the Baud Rate Generator for UART Fig. 9-8 shows the configuration of the baud rate generator. Fig. 9-8 Baud Rate Generator Clock Configuration (1) 4-bit counter The 4-bit counter counts the internal system c...
Page 282 - Operation of the Baud Rate Generator for UART; (1) Generating the baud rate clock from the internal system clock (f; (2) Generating the baud rate clock from the ASCK input
253 Chapter 9 Asynchronous Serial Interface 9 9.4.3 Operation of the Baud Rate Generator for UART The baud rate generator for UART starts operating, when the CE bit of the baud rate generator control register(BRGC) is set to 1. The baud rate clock to be generated is a signal obtained by dividing eit...
Page 283 - BAUD RATE SETTING; The baud rate can be set by three methods listed in Table 9-2.; : Internal system clock frequency
254 µ PD78214 Sub-Series 9.5 BAUD RATE SETTING The baud rate can be set by three methods listed in Table 9-2. The table indicates the ranges of baud rates that can be generated by each method, the baud rate calculationformulas, and the selection methods. Table 9-2 Baud Rate Setting j PRS3-PRS0 0H 1H...
Page 287 - When changing the mode, disable reception beforehand.
258 µ PD78214 Sub-Series 9.5.3 Example of Setting the BRGC When the External Baud Rate Input (ASCK) Is Used Table 9-5 lists examples of setting the BRGC register when an external baud rate input (ASCK) is used. To use theASCK input, set the SCK bit of the asynchronous serial interface mode register ...
Page 288 - CHAPTER 10 CLOCK SYNCHRONOUS SERIAL INTERFACE; The clock synchronous serial interface of the
259 10 CHAPTER 10 CLOCK SYNCHRONOUS SERIAL INTERFACE 10.1 FUNCTION The clock synchronous serial interface of the µ PD78214 is configured as shown in Fig. 10-1. The clock synchronous serial interface supports the following two operation modes: (1) Three-wire serial I/O mode (MSB first) Three lines, s...
Page 289 - Fig. 10-1 Block Diagram of the Clock Synchronous Serial Interface
260 µ PD78214 Sub-Series Fig. 10-1 Block Diagram of the Clock Synchronous Serial Interface Internal bus D CLS1 CLS0 f CLK /32 f CLK /8 8-bit timer/counter 3 output 1/2 Serial clock selector INTCSI Interrupt signal generator circuit Bus release/command/ acknowledge detector circuit Serial clock count...
Page 290 - Chapter 10 Clock Synchronous Serial Interface; Selects the serial clock to be used.
261 Chapter 10 Clock Synchronous Serial Interface 10 (1) Shift register (SIO) Converts 8-bit serial data into 8-bit parallel data and vice versa. The SIO is used for both transmission andreception. Data is shifted in (received) or shifted out (transmitted) from the MSB. The actual transmission/recep...
Page 291 - CONTROL REGISTERS; The register is set to 00H when RESET is input.
262 µ PD78214 Sub-Series 10.3 CONTROL REGISTERS 10.3.1 Clock Synchronous Serial Interface Mode Register (CSIM) This 8-bit register specifies a serial interface operation mode, serial clock and wake-up function. The 8-bit manipulation instruction and bit manipulation instruction can read and write th...
Page 295 - If transmission and reception are time-shared, and if the
266 µ PD78214 Sub-Series Fig. 10-5 Timing in Three-Wire Serial I/O Mode Notes Master CPU : Output Slave CPU : Input In three-wire serial I/O mode, the SO pin sends a CMOS push-pull output. Remark When connecting the device to a device having two-wire serial I/O, connect a buffer to the SO pin as sho...
Page 296 - Operation When Only Transmission Is Permitted; Operation When Only Reception Is Permitted; (1) Selecting the internal clock as the serial clock
267 Chapter 10 Clock Synchronous Serial Interface 10 10.4.2 Operation When Only Transmission Is Permitted Transmission is enabled when the CTXE bit of the clock synchronous serial interface mode register (CSIM) is set(1). If the CTXE bit is set, writing the contents of the shift register (SIO) invok...
Page 297 - For details of the SBI functions, refer also to
268 µ PD78214 Sub-Series (1) Selecting the internal clock as the serial clock When transmission and reception are started, the serial clock is output from the SCK pin. In synchronizationwith the falling edge of the serial clock, data is sequentially output from the SIO to the SO pin. Insynchronizati...
Page 298 - (2) Function to select a chip by its address; The master sends an address to select a slave chip.
269 Chapter 10 Clock Synchronous Serial Interface 10 (2) Function to select a chip by its address The master sends an address to select a slave chip. (3) Wake-up function Using the wake-up function (which can be set or released by software), a slave device can easily detectwhether it receives the ad...
Page 299 - Configuration of the Serial Interface; • Slave : Schmitt input
270 µ PD78214 Sub-Series 10.5.2 Configuration of the Serial Interface Fig. 10-9 is a block diagram of the µ PD78214. The serial clock pin (SCK) and serial data bus pin SB0 are configured as shown in Fig. 10-8. (1) SCK: Pin to input/output the serial clock • Master : CMOS push-pull output • Slave : S...
Page 300 - Fig. 10-9 Block Diagram of Clock Synchronous Serial Interface
271 Chapter 10 Clock Synchronous Serial Interface 10 Fig. 10-9 Block Diagram of Clock Synchronous Serial Interface Internal bus D CLS1 CLS0 f CLK /32 f CLK /8 INTCSI Interrupt signal generator circuit Bus release/command/ acknowledge detector circuit Serial clock counter Serial clock control circuit...
Page 303 - The value of the SBIC register is set to 00H when RESET is input.
274 µ PD78214 Sub-Series (2) Serial bus interface control register (SBIC) This 8-bit register consists of bits controlling the serial bus statuses and flags indicating the statuses of datainput from the serial bus. The 8-bit manipulation instruction and bit manipulation instruction can read and writ...
Page 306 - SBI COMMUNICATION AND SIGNALS; Address transfer
277 Chapter 10 Clock Synchronous Serial Interface 10 10.6 SBI COMMUNICATION AND SIGNALS This section describes the format of the SBI serial data and signals to be used. Serial data transferred via SBI can be divided into three groups: address, command, and data. Each frame of serialdata is formed as...
Page 307 - Fig. 10-17 Selecting a Slave Device by Its Address
278 µ PD78214 Sub-Series 10.6.2 Command Signal (CMD) The command signal is the SB0 line going from high to low while the SCK line is high (the serial clock is not output).The master device outputs this signal. Fig. 10-15 Command Signal SCK SB0 "H" The slave device contains the hardware to de...
Page 308 - [Output in synchronization with the ninth pulse of the SCK clock]
279 Chapter 10 Clock Synchronous Serial Interface 10 10.6.4 Command and Data The master device sends commands to, and sends or receives data to or from, the slave device selected accordingto the specified address. Fig. 10-18 Command SCK SB0 1 2 3 4 5 6 7 8 Command C7 C6 C5 C4 C3 C2 C1 C0 Command sig...
Page 310 - Caution Do not set ACKT before transfer has been completed.; (a) When ACKE is set to 1 at the end of transfer
281 Chapter 10 Clock Synchronous Serial Interface 10 Fig. 10-23 ACKT Operation Caution Do not set ACKT before transfer has been completed. Fig. 10-24 ACKE Operations (a) When ACKE is set to 1 at the end of transfer (b) When ACKE is set after transfer has been completed (c) When ACKE is set to 0 at t...
Page 316 - Table 10-3 Conditions Governing Release of BUSY; 1 Starting Transmission and Reception
287 Chapter 10 Clock Synchronous Serial Interface 10 10.6.8 Communication In SBI communication, the master device outputs an address on the serial bus and, usually, one target slave deviceis selected out of two or more devices according to the address. Once the target device has been determined, com...
Page 317 - Fig. 10-27 Sending an Address from Master Device to Slave Device
288 µ PD78214 Sub-Series Fig. 10-27 Sending an Address from Master Device to Slave Device Program processing Hardware operation Program processing SCK pin 12 345 6 78 SB0 pin A7 Hardware operation A6 A5 A4 A3 A2 A1 A0 ACK READY Address Master device processing (transmitter) Transfer line Slave devic...
Page 318 - Fig. 10-28 Sending a Command from Master Device to Slave Device
289 Chapter 10 Clock Synchronous Serial Interface 10 Fig. 10-28 Sending a Command from Master Device to Slave Device Program processing Hardware operation Program processing SCK pin 12 345 6 78 SB0 pin C7 Hardware operation C6 C5 C4 C3 C2 C1 C0 ACK READY Command Master device processing (transmitter...
Page 319 - Fig. 10-29 Sending Data from Master Device to Slave Device
290 µ PD78214 Sub-Series Fig. 10-29 Sending Data from Master Device to Slave Device Program processing Hardware operation Program processing SCK pin 12 345 6 78 SB0 pin D7 Hardware operation D6 D5 D4 D3 D2 D1 D0 ACK READY Data Master device processing (transmitter) Transfer line Slave device process...
Page 320 - Fig. 10-30 Sending Data from the Slave Device to the Master Device
291 Chapter 10 Clock Synchronous Serial Interface 10 Fig. 10-30 Sending Data from the Slave Device to the Master Device Program processing Hardware operation Program processing SCK pin 12 345 6 78 12 SB0 pin BUSY READY D7 Hardware operation D6 D5 D4 D3 D2 D1 D0 ACK BUSY D7 D6 READY Data Master devic...
Page 322 - CHAPTER 11 EDGE DETECTION FUNCTION; Table 11-1 Pins P20 to P26 and Use of Detected Edge
293 11 CHAPTER 11 EDGE DETECTION FUNCTION Pins P20 to P26 support an edge detection function to program a rising or falling edge. The detected edge is sentto the internal hardware. Table 11-1 shows the relationship between pins P20 to P26, and the use of the detectededge. Table 11-1 Pins P20 to P26 ...
Page 324 - Chapter 11 Edge Detection Function
295 Chapter 11 Edge Detection Function 11 Fig. 11-2 Format of External Interrupt Mode Register 1 (INTM1) 0 7 0 6 ES51 5 ES50 4 ES41 3 ES40 2 ES31 1 ES30 0 INTM1 ES31 Falling edge Specifies edge to be detected on P24 (INTP3, CR02 capture trigger) 0 ES30 0 Rising edge 0 1 Inhibited 1 0 Both falling an...
Page 325 - is required to detect the edge.; s after it is actually input. This
296 µ PD78214 Sub-Series 11.2 EDGE DETECTION ON PIN P20 An edge on pin P20 is detected after noise elimination by means of analog delay. A pulse width of at least 10 µ s is required to detect the edge. Fig. 11-3 Edge Detection on Pin P20 Caution Because noise elimination by analog delay is performed...
Page 326 - (a) Erroneously detected edge during input of a low signal
297 Chapter 11 Edge Detection Function 11 11.3 EDGE DETECTION ON PINS P21 TO P26 An edge on pins P21 to P26 is detected after digital noise elimination by means of clock sampling. The digital noise elimination is performed by means of sampling with the f CLK /4 clock. The input signal is eliminated ...
Page 327 - (b) Erroneously detected edge during input of a high signal; : Operates according to the erroneously detected edge.; s after the edge; of the f; clock to detect an edge after it is actually input.
298 µ PD78214 Sub-Series (b) Erroneously detected edge during input of a high signal INTPn input (n = 0 to 6) Erroneously detected edge f CLK /4 After noise rejection Falling edge detection Rising edge detection Noise "L" If the IE-78210-R is used, the real-time output port, timer/counter, a...
Page 328 - (5) If noise input to pins P21 to P26 is synchronized with the f; (a) Erroneously detected edge during input of low signal; (b) Erroneously detected edge during input of high signal
299 Chapter 11 Edge Detection Function 11 (5) If noise input to pins P21 to P26 is synchronized with the f CLK /4 clock of the µ PD78214, it may not be judged as being noise. If the input of such noise is possible, add a filter to the input pin so that the noise can beeliminated. (6) An in-circuit e...
Page 330 - CHAPTER 12 INTERRUPT FUNCTIONS
301 12 CHAPTER 12 INTERRUPT FUNCTIONS The µ PD78214 has the following two interrupt handling modes. Either mode can be selected by the program. Interrupt handling by a macro service is limited to the interrupt request sources provided with a macro servicehandling mode listed in Table 12-1. Table 12-...
Page 331 - INTERRUPT REQUEST SOURCES; To exit the BRK service routine, execute the RETB instruction.
302 µ PD78214 Sub-Series 12.1 INTERRUPT REQUEST SOURCES The µ PD78214 has 19 interrupt request sources shown in Table 12-2. Each of these sources is assigned an interrupt vector table. Table 12-2 Interrupt Request Sources Software Nonmaskable Maskable Interrupt request type None None 0 1 2 3 4 5 6 7...
Page 332 - Chapter 12 Interrupt Functions
303 Chapter 12 Interrupt Functions 12 12.1.2 Nonmaskable Interrupt Request A nonmaskable interrupt request is input to the NMI pin. When a valid edge, specified by bit 0 (ESNMI) of externalinterrupt mode register 0 (INTM0), is input to the NMI pin, an interrupt request is generated. A nonmaskable in...
Page 333 - for control of the; INTERRUPT HANDLING CONTROL REGISTERS; The following six registers control interrupt handling.
304 µ PD78214 Sub-Series (2) Selecting INTP5 or INTAD Interrupt INTP5 or INTAD is selected by the A/D converter mode register (ADM). (Either of these interruptsis selected automatically, according to the mode of operation specified for the A/D converter.) Both 8-bit manipulation instruction and bit ...
Page 334 - Table 12-3 Flags for Interrupt Request Sources
305 Chapter 12 Interrupt Functions 12 Table 12-3 Flags for Interrupt Request Sources INTP0 INTP1 INTP2 INTP3 INTC00 INTC01 INTC10 INTC11 INTC21 INTP4 INTC30 INTP5 INTAD INTC20 INTSER INTSR INTST INTCSI Interrupt request source Interrupt request flag PIF0 PIF1 PIF2 PIF3 CIF00 CIF01 CIF10 CIF11 CIF21 ...
Page 336 - When the RESET signal is input, the register is reset to 00H.
307 Chapter 12 Interrupt Functions 12 When a low-priority vectored interrupt is being handled, vectored interrupt requests with lower and higherpriorities are accepted for multiple-interrupt handling provided that interrupts are enabled. When a high-priorityinterrupt is being handled, high-priority ...
Page 337 - When the RESET signal is input, the PSW is set to 02H.; INTERRUPT HANDLING
308 µ PD78214 Sub-Series 12.2.6 Program Status Word (PSW) The PSW is a register that holds the result of instruction execution and the current status of interrupt requests. Theregister is mapped with the IE flag that specifies whether to enable maskable interrupts and the ISP flag to controlmultiple...
Page 338 - Fig. 12-9 Accepting an NMI Interrupt Request
309 Chapter 12 Interrupt Functions 12 Resetting the NMIS bit to 0 during execution of a nonmaskable interrupt service program enables multiple-interrupt handling for nonmaskable interrupt requests. If the NMIS bit is 0, a new nonmaskable interrupt requestis accepted even when a nonmaskable interrupt...
Page 339 - manipulated by the current NMI service program)
310 µ PD78214 Sub-Series (c) If a new NMI request occurs during execution of an NMI service program (when the NMIS bit is reset to 0 bythe current NMI service program after the NMI request occurs) (d) If two new NMI requests occur during execution of an NMI service program (when the NMIS bit is not ...
Page 340 - after the RESET signal; A pending interrupt request is accepted when it is enabled.
311 Chapter 12 Interrupt Functions 12 3. Nonmaskable interrupts are always accepted except during execution of the nonmaskable interrupt handling program (except when multiple-interrupt handling for nonmaskable interrupts have been enabled by resetting the NMIS bit of the IST registerto 0 during exe...
Page 345 - Interrupt Request and Macro Service Pending; EI
316 µ PD78214 Sub-Series Fig. 12-12 Example of Handling Interrupts That Occur Simultaneously 12.3.5 Interrupt Request and Macro Service Pending When any of the following instructions is executed, all interrupts (including nonmaskable interrupts) and macroservices are kept pending. The pending state ...
Page 346 - Interrupt and Macro Service Operation Timing; (1) Generation and acceptance of an interrupt request; When the interrupt request flag is set to 1, three clocks (0.5; Table 12-5 Interrupt Request Acceptance Processing Time
317 Chapter 12 Interrupt Functions 12 Example of correct coding (2) LOOP: BT IF0H.3, $NEXT BR $LOOP NEXT: ← 2. In addition, when you have to use a coding of the instructions listed above consecutively, yet expect frequent occurrence of interrupts and macro services, insert NOP instructions in the co...
Page 347 - Table 12-6 Macro Service Processing Time
318 µ PD78214 Sub-Series 3. “Peripheral RAM” corresponds to the internal RAM at addresses 0FC80H through 0FDFFH (for the µ PD78212, 0FD80H through 0FDFFH). 4. 1 clock = 1/f CLK (167 ns at 12 MHz). (3) Macro service processing time The time required to process a macro service varies, depending on the...
Page 348 - MACRO SERVICE FUNCTION
319 Chapter 12 Interrupt Functions 12 12.4 MACRO SERVICE FUNCTION 12.4.1 Macro Service Outline Macro service is one of the interrupt handling methods. When a vectored interrupt is processed, the contents ofthe program counter (PC) and the program status word (PSW) are saved in the stack and the PC i...
Page 350 - Fig. 12-15 Macro Service Processing Sequence
321 Chapter 12 Interrupt Functions 12 (3) Type C Transfers 1-byte data from memory to the real-time output port and the compare register for 8-bit timer/counter 1 upon each interrupt request. When a specified number of data transfers are performed, a vectoredinterrupt request is generated. Type C ma...
Page 352 - Fig. 12-17 shows the format of the macro service mode register.
323 Chapter 12 Interrupt Functions 12 (2) Macro service mode register A macro service mode register is an 8-bit register that specifies the mode of macro service operation. It ismapped in internal RAM as part of macro service control word (see Fig 12-16 ). Fig. 12-17 shows the format of the macro se...
Page 356 - (3) Example of using the type A macro service; Fig. 12-20 Asynchronous Serial Reception
327 Chapter 12 Interrupt Functions 12 (3) Example of using the type A macro service The following example shows how data received through an asynchronous serial interface is transferred toa buffer area in the internal RAM. Fig. 12-20 Asynchronous Serial Reception 12.4.6 Type B Macro Service (1) Oper...
Page 358 - Caution The following registers cannot be used as SFRs.
329 Chapter 12 Interrupt Functions 12 (2) Macro service channel configuration The macro service pointer (MP) indicates a data buffer area in the 64K memory space as a transfer source ordestination. The SFR pointer (SFRP) is set with the lower 8 bits of the address of an SFR used as a transfer source...
Page 359 - (3) Example of using the type B macro service
330 µ PD78214 Sub-Series (3) Example of using the type B macro service The following example shows how parallel data is input from port 3 in synchronization with an external signal.The external signal is input to the external interrupt pin (INTP4). Fig. 12-23 Parallel Data Input in Synchronization w...
Page 360 - (a) Retention of the timer macro service pointer
331 Chapter 12 Interrupt Functions 12 12.4.7 Macro Service Type C (1) Operation The type C macro service controls 8-bit timer/counter 1 and the real-time output port simultaneously. Thismacro service transfers data to both the compare register for 8-bit timer/counter 1 and the buffer register forthe...
Page 365 - (3) Example of using the type C macro service
336 µ PD78214 Sub-Series (3) Example of using the type C macro service The following example shows a pattern output to the real-time output port and how the output interval iscontrolled directly. Update data is transferred from two data areas previously set in the 64K-byte space to the buffer regist...
Page 366 - (4) Example of using automatic addition control and ring control; t) specified by a macro service
337 Chapter 12 Interrupt Functions 12 Fig. 12-28 Data Transfer Control Timing (4) Example of using automatic addition control and ring control (a) Automatic addition control The automatic addition control function adds the output timing data ( ∆ t) specified by a macro service pointer (MPT) to the c...
Page 370 - (with the Output Timing Varied by Phase 2 Excitation)
341 Chapter 12 Interrupt Functions 12 Fig. 12-33 Block Diagram 2 for Automatic Addition Control Plus Ring Control (with the Output Timing Varied by Phase 2 Excitation) MSC FF –1 Ring counter (RC) 04 –1 Modulo register (MR) 04 MPDL 00 +1 MPDH B0 MPTL 00 MPTH B1 Mode register EE Channel pointer CF Mac...
Page 372 - and an instruction that; after the RESET signal rises.
343 Chapter 12 Interrupt Functions 12 12.5 NOTES (1) Do not use the RETI instruction to return from the software interrupt. (2) A macro service request is accepted and processed even when a nonmaskable interrupt service program is running. To disable macro service processing during execution of the ...
Page 374 - CHAPTER 13 LOCAL BUS INTERFACE FUNCTION
345 13 CHAPTER 13 LOCAL BUS INTERFACE FUNCTION The local bus interface function is provided to connect external memories (ROM and RAM) and I/Os. External memories (ROM and RAM) and I/Os are accessed by using the RD, WR, and ASTB signals, a multiplexedaddress/data bus consisting of lines AD0 to AD7, ...
Page 375 - CONTROL REGISTERS; When the RESET signal is applied, the register is set to 20H.
346 µ PD78214 Sub-Series 13.1 CONTROL REGISTERS 13.1.1 Memory Expansion Mode Register (MM) The MM register is an 8-bit register for controlling externally expanded memory, specifying the number of waitstates (address space: 00000H to 0FFFFH), and controlling the internal fetch cycle. The MM register...
Page 376 - Chapter 13 Local Bus Interface Function; MEMORY EXPANSION FUNCTION
347 Chapter 13 Local Bus Interface Function 13 13.1.2 Programmable Wait Control Register (PW) The PW register is an 8-bit register for specifying the number of wait states for external expansion data memoryspace 10000H to FFFFFH. The PW register can be read and written with both 8-bit manipulation i...
Page 378 - Fig. 13-5 Accessing Expansion Data Memory
349 Chapter 13 Local Bus Interface Function 13 Fig. 13-5 Accessing Expansion Data Memory (a) Read cycle RD (output) A16-A19 (output) Contents of P6/PM6 register Higher address Higher address Lower address(output) Hi-Z Hi-Z Program (input) Lower address(output) Data (input) Hi-Z Hi-Z Hi-Z A8-A15 (out...
Page 379 - Memory Mapping with Expanded Memory; PD78214 take precedence and are accessed. The ASTB, RD, and WR
350 µ PD78214 Sub-Series 13.2.3 Memory Mapping with Expanded Memory Figs. 13-6 to 13-9 show the memory maps when the memory has been expanded. Even when the memory hasbeen expanded, external devices at the same addresses as those of the internal ROM area, internal RAM area, orSFR area (excluding the...
Page 385 - Fig. 13-10 Example of Connecting Memories to
356 µ PD78214 Sub-Series Fig. 13-10 Example of Connecting Memories to µ PD78214 PD23C4000A µ PD43256AC-12 µ PD27C512D-15 µ LE D0-D7 OE Q0-Q7 AD0-AD7 ASTB A8-A14 OECEA17A16A15 A14 A-1-A13 CSWEOE A19A18A17A16 Q4Q3Q2Q1 D4D3D2D1 ST ST G2ACBA G2B WORD/BYTE 74HC04 74HC32 O0-O7 I/O1-I/O8 A0-A14 A0-A14 O0-O...
Page 386 - INTERNAL ROM HIGH-SPEED FETCH FUNCTION
357 Chapter 13 Local Bus Interface Function 13 13.3 INTERNAL ROM HIGH-SPEED FETCH FUNCTION The µ PD78212, µ PD78214, and µ PD78P214 contain an internal ROM. The internal ROM can be accessed quickly without having to use the bus control circuit. Usually, internal ROM is fetched at the same speed as e...
Page 395 - Fig. 13-17 Timing When External Wait Signal Is Used
366 µ PD78214 Sub-Series Fig. 13-17 Timing When External Wait Signal Is Used (a) Read timing Higher address Lower address (output) Data (input) Hi-Z Hi-Z A8-A15 (output) AD0-AD7 ASTB (output) RD (output) f CLK Note WAIT (input) (b) Write timing Higher address Lower address Data Hi-Z Hi-Z A8-A15 (out...
Page 396 - PSEUDO STATIC RAM REFRESH FUNCTION
367 Chapter 13 Local Bus Interface Function 13 13.5 PSEUDO STATIC RAM REFRESH FUNCTION 13.5.1 Function The µ PD78214 provides the pseudo static RAM refresh function to enable pseudo static RAM to be connected directly. The pseudo static RAM refresh function outputs refresh pulses at arbitrary interv...
Page 397 - Fig. 13-19 Pulse Refresh When Internal Memory Is Accessed
368 µ PD78214 Sub-Series 13.5.3 Operation (1) Pulse refresh operation To support the pulse refresh cycle of pseudo static RAM, the REFRQ pin outputs refresh pulses, synchronizedwith the bus cycle. Adjust the oscillator frequency and bits 1 and 0 (RFT1 and RFT0) of the refresh mode register (RFM) so ...
Page 398 - Fig. 13-20 Pulse Refresh When External Memory Is Accessed
369 Chapter 13 Local Bus Interface Function 13 (b) Accessing External Memory The refresh bus cycle is generated at the intervals specified with the refresh mode register (RFM). Pseudo static RAM may malfunction if the access timing overlaps the refresh pulse output timing;therefore, the µ PD78214 ge...
Page 399 - after the output level
370 µ PD78214 Sub-Series (2) Self-refresh Self-refresh is performed to retain the contents of pseudo static RAM when in standby mode. (a) Setting self-refresh mode When bit 4 (RFEN) of the RFM register is set to 1, and bit 7 (RFLV) is set to 0, pin REFRQ outputs a low-levelsignal, requesting pseudo ...
Page 401 - Example of Connecting Pseudo Static RAM; Fig. 13-23 shows an example of connecting pseudo static RAM to the
372 µ PD78214 Sub-Series 13.5.4 Example of Connecting Pseudo Static RAM Fig. 13-23 shows an example of connecting pseudo static RAM to the µ PD78214. In this example, pseudo static RAM is assigned to addresses 20000H to 3FFFFH. Fig. 13-23 Example of Connecting Pseudo Static RAM to µ PD78214 Remarks ...
Page 402 - Table 13-3 Conditions and Operations for Illegal Write Access
373 Chapter 13 Local Bus Interface Function 13 (3) When macro service Type A or Type C is used in external memory expansion mode (the µ PD78213 always uses external memory), an illegal write access may occur. This occurs when any of the following three conditions is satisfied: (a) Data is transferre...
Page 404 - Fig. 13-27 Preventing Problems That May Occur during Emulation
375 Chapter 13 Local Bus Interface Function 13 Fig. 13-27 Preventing Problems That May Occur during Emulation A19 To target circuit A18 A17 A16 ASTB Q 4 Q 3 Q 2 Q 1 D 4 D 3 D 2 D 1 Target probe 74HC375
Page 408 - Chapter 14 Standby Function; When the RESET signal is input, the register is set to 0000; Specifying HALT Mode and Operation States in HALT Mode; Table 14-1 Operation States in HALT Mode
379 Chapter 14 Standby Function 14 14.2 STANDBY CONTROL REGISTER (STBC) The standby control register (STBC) is an 8-bit register which controls standby mode. The STBC register can beboth read and written. Only a specified instruction (MOV STBC, #byte), however, can be used for writing to theregister...
Page 410 - (2) Release by a maskable interrupt request; Table 14-3 Release of HALT Mode by a Maskable Interrupt Request
381 Chapter 14 Standby Function 14 (2) Release by a maskable interrupt request Only maskable interrupts with 0 in the interrupt mask flag can be used to release HALT mode. If the interruptpriority status flag (ISP) is set to 0 (only high-priority interrupts are enabled), only interrupts with 0 in th...
Page 411 - Specifying STOP Mode and Operation States in STOP Mode; Table 14-4 Operation States in STOP Mode; (ground potential) to prevent current leakage from the clock; STOP mode can be released by inputting an NMI or RESET signal.
382 µ PD78214 Sub-Series 14.4 STOP MODE 14.4.1 Specifying STOP Mode and Operation States in STOP Mode The system enters STOP mode when the STP bit of the STBC register is set to 1. The STBC register can be written only with a specified 8-bit data write instruction. To specify STOP mode, executethe “...
Page 412 - Fig. 14-4 Releasing STOP Mode with an NMI Signal
383 Chapter 14 Standby Function 14 Fig. 14-4 Releasing STOP Mode with an NMI Signal Caution If another effective edge of the NMI signal is detected during the oscillation settling time, the oscillation settling time counter is cleared and restarts counting, resulting in a longer wait time than usual...
Page 413 - for that port, as well as the port mode register, by means of a program.; and V; . A voltage that falls outside
384 µ PD78214 Sub-Series 14.4.3 Notes on Using STOP Mode Check the following items to ensure that current consumption is appropriately reduced in STOP mode: (1) Is the output level of each output pin appropriate? The appropriate output level of each pin depends on the circuit of the next stage. Sele...
Page 414 - Fig. 14-6 Example of Address Bus Arrangement; CMOS IC
385 Chapter 14 Standby Function 14 Fig. 14-6 Example of Address Bus Arrangement Power supply backed up V DD V DD V SS V SS IN Diode with small V F An (n = 8 to 15) Power supply not backed up CMOS IC , etc. PD78214 µ The outputs of the address/data bus pins are high-impedance in STOP mode. The addres...
Page 415 - Fig. 14-8 Example Arrangement for Analog Input Pin; NMI request to release STOP mode, input the NMI signal again.
386 µ PD78214 Sub-Series Fig. 14-8 Example Arrangement for Analog Input Pin V DD V SS ANn (n = 0 to 7) Power supply backed up PD78214 µ AV REF Diode with small V F Power supply not backed up Signal source The voltage input to the AN0 to AN7 pins must be maintained at a level between V SS and V DD . ...
Page 416 - Fig. 14-9 Example of Longer Oscillation Settling Time
387 Chapter 14 Standby Function 14 Fig. 14-9 Example of Longer Oscillation Settling Time NMI (effective at falling edge) 2 16 /f CLK STOP mode Wait for oscillation to settle Normal operation Oscillation settling time is extended by this period. CPU operation Count value of oscillation settling time ...
Page 418 - CHAPTER 15 RESET FUNCTION; Initialize registers in the program as required.
389 15 CHAPTER 15 RESET FUNCTION 15.1 RESET FUNCTION When the signal applied to the RESET input pin is low, the system is reset, and each hardware component is setto the state indicated in Table 15-2. All pins, except the power supply pin, assume the high-impedance state. Table15-1 lists the states ...
Page 420 - Chapter 15 Reset Function
391 Chapter 15 Reset Function 15 Table 15-2 Hardware States after Reset (1/2) State after reset Hardware Program counter (PC) Stack pointer (SP) Program status word (PSW) Data memory General registers (X, A, C, B, E, D, L, H) Ports Port 0, 2, 3, 4, 5, and 7 Port 6 Port mode registers PM0, PM3, PM5 P...
Page 422 - Fig. 15-3 Timing Charts for Reset Operation
393 Chapter 15 Reset Function 15 Fig. 15-3 Timing Charts for Reset Operation (a) For µ PD78213 (b) For µ PD78214 15.2 NOTE When resetting the system at power-on, do not set the RESET signal high immediately after the supply voltagereaches the specified level. Keep the signal low until oscillation ha...
Page 424 - Data transferred to the buffer register is output from port 0.
395 16 CHAPTER 16 APPLICATION EXAMPLES 16.1 OPEN-LOOP CONTROL OF STEPPER MOTORS This section provides an example of controlling stepper motors with the real-time output function, 8-bit timer/counter 1, and the macro service function of the µ PD78214. Fig. 16-1 shows the functional blocks for control...
Page 425 - Fig. 16-1 Example of Controlling Two Stepper Motors
396 µ PD78214 Sub-Series Fig. 16-1 Example of Controlling Two Stepper Motors Internal bus Internal bus Compare register CR11 8-bit timer 1 TM1 Buffer register P0H Output latch Output latch Buffer register P0L Real-time output port (lower) Real-time output port (higher) Prescaler mode register Multip...
Page 426 - Chapter 16 Application Examples; SERIAL COMMUNICATION WITH MULTIPLE DEVICES
397 Chapter 16 Application Examples 16 16.2 SERIAL COMMUNICATION WITH MULTIPLE DEVICES Fig. 16-2 shows an example of a system configured with a serial bus interface. The serial bus interface can transferaddresses (for selecting devices), commands, and data, as well as acknowledge and busy signals, u...
Page 428 - CHAPTER 17 PROGRAMMING FOR THE; Table 17-1 Operating Modes for PROM Programming; Caution When V; PROCEDURE FOR WRITING INTO PROM
399 17 CHAPTER 17 PROGRAMMING FOR THE µ PD78P214 The µ PD78P214 employs an electrically writable PROM of 16384 × 8 bits for program memory. Use the NMI and RESET pins to set the µ PD78P214 to PROM programming mode when programming the PROM. The µ PD78P214 provides programming characteristics compati...
Page 429 - Fig. 17-1 Timing Chart for PROM Write and Verify
400 µ PD78214 Sub-Series Fig. 17-1 Timing Chart for PROM Write and Verify Hi-Z Data input A0-A14 Data output Data input Hi-Z Hi-Z Hi-Z +12.5 V D0-D7 V DD V pp +6 V V DD V DD CE (input) 3X ms Write Verify Additional write Address input Repetition of X times OE (input)
Page 430 - Chapter 17 Programming for The; PROCEDURE FOR READING FROM PROM; (3) Input the address of the data to be read into the A0 to A14 pins.
401 Chapter 17 Programming for The µ PD78214 17 Fig. 17-2 Write Operation Flowchart 17.3 PROCEDURE FOR READING FROM PROM The contents of PROM can be read out to the external data bus (D0 to D7) by following the procedure below: (1) Fix the RESET pin to the low level. Apply +12.5 V to pin NMI. Handle...
Page 431 - When V
402 µ PD78214 Sub-Series Fig. 17-3 PROM Read Timing Chart Address input A0-A14 Hi-Z Data output CE (input) OE (input) D0-D7 Hi-Z 17.4 NOTE When V PP is +12.5 V and V DD is +6 V, CE and OE must not be set to low at the same time.
Page 432 - CHAPTER 18 INSTRUCTION OPERATIONS
403 18 CHAPTER 18 INSTRUCTION OPERATIONS This chapter describes the operation of each instruction of the µ PD78214 sub-series. Refer to the 78K/II Series User’s Manual, Instructions (IEU-1311) for details of each operation, the corresponding machine language code (instruction code), and the number o...
Page 434 - Chapter 18 Instruction Operations
405 Chapter 18 Instruction Operations 18 Z : Zero flag RBS1-RBS0 : Register bank selection flag IE : Interrupt request enable flag STBC : Standby control register jdisp8 : Signed 8-bit data (displacement: –128 to +127) ( ) : Contents at address enclosed in parentheses or at address indicated in regi...
Page 435 - LIST OF OPERATIONS
406 µ PD78214 Sub-Series MOV XCH Operation Mnemonic Operand No. of bytes Flags Z AC CY 18.2 LIST OF OPERATIONS (1) 8-bit data transfer instructions: MOV, XCH r, #byte 2 r ← byte saddr, #byte 3 (saddr) ← byte sfr, #byte 3 sfr ← byte r, r' 2 r ← r' A, r 1 A ← r A, saddr 2 A ← (saddr) saddr, A 2 (saddr...
Page 436 - MOVW
407 Chapter 18 Instruction Operations 18 MOVW Operation Mnemonic Operand No. of bytes Flags rp, #word 3 rp ← word saddrp, #word 4 (saddrp) ← word sfrp, #word 4 sfrp ← word rp, rp' 2 rp ← rp' AX, saddrp 2 AX ← (saddrp) saddrp, AX 2 (saddrp) ← AX AX, sfrp 2 AX ← sfrp sfrp, AX 2 sfrp ← AX AX, mem1 2 AX...
Page 438 - XOR
409 Chapter 18 Instruction Operations 18 XOR CMP Operation Mnemonic Operand No. of bytes Flags A, #byte 2 A ← A ∨ byte × saddr, #byte 3 (saddr) ← (saddr) ∨ byte × sfr, #byte 4 sfr ← sfr ∨ byte × r, r' 2 r ← r ∨ r' × A, saddr 2 A ← A ∨ (saddr) × A, sfr 3 A ← A ∨ sfr × saddr, saddr' 3 (saddr) ← (saddr...
Page 440 - ADJBA
411 Chapter 18 Instruction Operations 18 ADJBA ADJBS Operation Mnemonic Operand No. of bytes Flags Z AC CY 1 Use the decimal adjust accumulator after addition. × × × 1 Use the decimal adjust accumulator after subtraction. × × × MOV1 AND1 OR1 Operation Mnemonic Operand No. of bytes Flags Z AC CY CY, ...
Page 444 - MOV
415 Chapter 18 Instruction Operations 18 MOV SEL NOP EI DI Operation Mnemonic Operand No. of bytes Flags STBC, #byte 4 STBC ← byte RBn 2 RBS1 – 0 ← n, n = 0 – 3 1 No operation 1 IE ← 1 (Enable interrupts) 1 IE ← 0 (Disable interrupts) Z AC CY (14) CPU control instructions: MOV, SEL, NOP, EI, DI
Page 445 - INSTRUCTION LISTS FOR EACH ADDRESSING TYPE; Table 18-1 8-Bit Instructions for Each Addressing Type
416 µ PD78214 Sub-Series Firstoperand Second operand # byte A sfr mem & mem !addr16 & !addr16 PSW n None Note 2 r r' saddr saddr' MOV XCH MOV XCH ADD Note 1 MOV MOV XCH ADD Note 1 MOV XCH ADD Note 1 DEC INC DBNZ ROR RORC ROL ROLC SHR SHL DBNZ MULU DIVUW DEC INC MOV ADD Note 1 MOV MOV ADD Not...
Page 446 - Table 18-2 16-Bit Instructions for Each Addressing Type
417 Chapter 18 Instruction Operations 18 (2) 16-bit instructions MOVW, ADDW, SUBW, CMPW, INCW, DECW, SHRW, and SHLW Table 18-2 16-Bit Instructions for Each Addressing Type Firstoperand Second operand # word AX sfr mem1 & mem1 ADDW SUBW CMPW MOVW ADDW SUBW CMPW MOVW ADDW SUBW CMPW AX rp rp' saddr...
Page 448 - (4) Call instructions and branch instructions
419 Chapter 18 Instruction Operations 18 (4) Call instructions and branch instructions CALL, CALLF, CALLT, BR, BC, BT, BF, BTCLR, DBNZ, BL, BNC, BNL, BZ, BE, BNZ, and BNE Table 18-4 Call Instructions and Branch Instructions for Each Addressing Type Instruction addressing operand $addr16 !addr16 rp !...
Page 450 - APPENDIX A 78K/II SERIES PRODUCT LIST; The following pages list the 78K/II series products.
421 A APPENDIX A 78K/II SERIES PRODUCT LIST The following pages list the 78K/II series products. For details, refer to each User’s Manual.
Page 452 - Appendix A 78K/II Series Product List
423 Appendix A 78K/II Series Product List A (1/3) µ PD78234 Sub-Series µ PD78244 Sub-Series µ PD78233 µ PD78243 µ PD78238 ( µ PD78P238) µ PD78237 500 ns 333 ns 333 ns 500 ns 333 ns 500 ns 65 (instructions common to all 78K/II series products) 8 bits × 8 × 4 banks 32K (32/16K Note ) None None 16K 16K...
Page 458 - APPENDIX B DEVELOPMENT TOOLS
429 B APPENDIX B DEVELOPMENT TOOLS The development tools described on the following pages are available for the development of systems using µ PD78214 sub-series.
Page 459 - When the in-circuit emulator is connected to the host mahine; DEVELOPMENT ENVIRONMENT
430 µ PD78214 Sub-Series IE-78210-R Note 2 IE-78240-R IE-78240-R-A In-circuit emulator Emulation probe EP-78210CW Note 2 EP-78210GC Note 2 EP-78210GJ EP-78210GQ Note 2 EP-78210L Note 2 EP-78240CW-R EP-78240GC-R EP-78240GJ-R EP-78240GQ-R EP-78240LP-R Console Note 4 Host machine PC-9800 series IBM PC/...
Page 460 - Appendix B Development Tools
431 Appendix B Development Tools B IE-78240-R-A The IE-78240-R-A is an enhanced version of the IE-78210-R and IE-78240-R. This in-circuit emulator can be used for any model of the µ PD78214 sub-series. It operates with a PC-9800 series or IBM PC/AT host machine. By using this emulator together with ...
Page 466 - The following OSs are supported for the IBM PC:
437 Appendix B Development Tools B This program provides the serial and parallel interfaces between PG-1500 and the host machine, enabling the host machine to control the PG-1500. PG-1500 controller OS µ S5A10PG1500 µ S5A13PG1500 µ S7B11PG1500 µ S7B10PG1500 µ S5A13PG1500 Part number 5-inch 2HD 3.5-i...
Page 467 - B.3 UPGRADING OTHER IN-CIRCUIT EMULATORS TO 78K/II SERIES LEVEL
438 µ PD78214 Sub-Series B.3 UPGRADING OTHER IN-CIRCUIT EMULATORS TO 78K/II SERIES LEVEL The 78K series and 75X series in-circuit emulators can be upgraded to the level of the 78K/II series by replacingtheir internal boards with an optional board. Note that the upgraded in-circuit emulator requires ...
Page 472 - APPENDIX D REGISTER INDEX
443 D APPENDIX D REGISTER INDEX D.1 REGISTER INDEX 16-bit capture register (CR02) ... 111 16-bit compare register (CR00,CR01) ... 111 16-bit timer 0 (TM0) ... 111 8-bit capture/compare register (CR11) ... 142 8-bit capture register (CR22) ... 161 8-bit compare register (CR10) ... 142 8-bit compare r...
Page 474 - Appendix D Register Index; D.2 REGISTER SYMBOL INDEX
445 Appendix D Register Index D D.2 REGISTER SYMBOL INDEX A ADCR: A/D conversion result register ... 227 ADM: A/D converter mode register ... 229, 304 ASIM: Asynchronous serial interface mode register ... 245 ASIS: Asynchronous serial interface status register ... 246 B BRGC: Baud rate generator con...
Page 476 - APPENDIX E INDEX
447 E APPENDIX E INDEX E.1 INDEX 0 parity ... 247, 248 16-bit timer 0 ... 111, 114 16-bit timer/counter ... 109 1M-byte expansion function ... 348 4-bit counter ... 251 4-bit separate real-time output port ... 97 64-pin ceramic shrink DIP with window ... 6 64-pin plastic QFP ... 8 64-pin plastic QUI...
Page 478 - Appendix E Index; Pin
449 Appendix E Index E Interrupt status register ... 304, 307 Interval timer ... 129, 151, 190, 192, 210, 211 Interval ... 109, 139, 159, 205 L Local bus interface function ... 345 Loop counter ... 49 M Macro service ... 301, 319 Macro service channel ... 321, 326, 329 Macro service channel pointer ...
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