Page 3 - NOTES FOR CMOS DEVICES
User’s Manual U15331EJ4V1UD 3 1 2 3 4 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V IL (MAX) and V IH (MIN) due to noise, etc., the device may malfunction. Take c...
Page 6 - Regional Information; Device availability; NEC Electronics Hong Kong Ltd.
6 User’s Manual U15331EJ4V1UD Regional Information • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power ...
Page 7 - Major Revisions in This Edition
User’s Manual U15331EJ4V1UD 7 Major Revisions in This Edition Page Description Throughout Change of descriptions of µ PD789489, 78F9489 • Change of status from under development to development completed • Change of the subseries name to “ µ PD789489 subseries” pp.31 to 33 Update of 1.5 78K/0S Series...
Page 8 - INTRODUCTION
8 User’s Manual U15331EJ4V1UD INTRODUCTION Target Readers This manual is intended for user engineers who wish to understand the functions of the µ PD789489 Subseries and design and develop application systems and programs for these devices. Target products: • µ PD789489 Subseries: µ PD789488, 789489...
Page 10 - Note
10 User’s Manual U15331EJ4V1UD Documents Related to Flash Memory Writing Document Name Document No. PG-FP3 Flash Memory Programmer User’s Manual U13502E PG-FP4 Flash Memory Programmer User’s Manual U15260E Other Related Documents Document Name Document No. SEMICONDUCTOR SELECTION GUIDE - Products an...
Page 11 - CONTENTS; to V
User’s Manual U15331EJ4V1UD 11 CONTENTS CHAPTER 1 GENERAL .......................................................................................................................... 26 1.1 Features ..........................................................................................................
Page 14 - Supplying LCD Drive Voltages V
14 User’s Manual U15331EJ4V1UD 9.4.1 Operation as watchdog timer ...................................................................................................... 171 9.4.2 Operation as interval timer .................................................................................................
Page 15 - CHAPTER 15 REMOTE CONTROLLER RECEIVER (
User’s Manual U15331EJ4V1UD 15 14.1 Multiplier Function ................................................................................................................... 267 14.2 Multiplier Configuration .................................................................................................
Page 16 - CHAPTER 22 ELECTRICAL SPECIFICATIONS (
16 User’s Manual U15331EJ4V1UD CHAPTER 20 MASK OPTIONS ...........................................................................................................331 CHAPTER 21 INSTRUCTION SET ......................................................................................................332 2...
Page 26 - CHAPTER 1 GENERAL; • ROM and RAM capacities
26 User’s Manual U15331EJ4V1UD CHAPTER 1 GENERAL 1.1 Features • ROM and RAM capacities Item Data Memory Part Number Program Memory (ROM) Internal RAM LCD Display RAM µ PD789488 Mask ROM µ PD78F9488 Flash memory 32 KB 1024 bytes 28 × 4 bits µ PD789489 Mask ROM 1536 bytes µ PD78F9489 Flash memory 48 K...
Page 27 - Ordering Information
CHAPTER 1 GENERAL User’s Manual U15331EJ4V1UD 27 1.3 Ordering Information Part Number Package Internal ROM µ PD789488GC- ××× -8BT 80-pin plastic QFP (14 × 14) Mask ROM µ PD789488GK- ××× -9EU 80-pin plastic TQFP (fine pitch) (12 × 12) Mask ROM µ PD78F9488GC-8BT 80-pin plastic QFP (14 × 14) Flash memo...
Page 28 - registers; and; and
CHAPTER 1 GENERAL 28 User’s Manual U15331EJ4V1UD 1.4 Pin Configuration (Top View) (1) µ PD789488, 78F9488 80-pin plastic QFP (14 × 14) µ PD789488GC- ××× -8BT µ PD78F9488GC-8BT µ PD789488GC- ××× -8BT-A µ PD78F9488GC-8BT-A 80-pin plastic TQFP (fine pitch) (12 × 12) µ PD789488GK- ××× -9EU µ PD78F9488GK...
Page 29 - pin to V; The parenthesized values apply to the
CHAPTER 1 GENERAL User’s Manual U15331EJ4V1UD 29 Cautions 1. Connect the IC (Internally Connected) pin directly to V SS . 2. Connect the AV DD pin to V DD . 3. Connect the AV SS pin to V SS . Remark The parenthesized values apply to the µ PD78F9488 (2) µ PD789489, 78F9489 80-pin plastic QFP (14 × 14...
Page 31 - Remark; VFD (Vacuum Fluorescent Display) is referred to as FIP; documents, but the functions of the two are the same.
CHAPTER 1 GENERAL User’s Manual U15331EJ4V1UD 31 1.5 78K/0S Series Lineup The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names. 80-pin SIO, 8-bit A/D converter, and resistance division type LCD (28 × 4) 52-pin 52-pin SIO and resistance division type LCD...
Page 33 - Series for ASSP
CHAPTER 1 GENERAL User’s Manual U15331EJ4V1UD 33 Series for ASSP Timer V DD Function Subseries Name ROM Capacity 8-Bit 16-Bit Watc h WDT 8-Bit A/D 10-Bit A/D Serial Interface I/O MIN. Value Remarks USB µ PD789800 8 KB 2 ch − − 1 ch − − 2 ch (USB: 1 ch) 31 4.0 V − Inverter control µ PD789842 8 KB to ...
Page 34 - CHAPTER 20 MASK OPTIONS
CHAPTER 1 GENERAL 34 User’s Manual U15331EJ4V1UD 1.6 Block Diagram 78K/0SCPU core ROM (flash memory) RAM V DD V SS IC0 (V PP ) CPT20/TO20/P33 8-bit timer/event counter 60 P00 to P07 Port 0 P10 to P11 Port 1 P20 to P25 Port 2 P30 to P34 Port 3 P50 to P53 Port 5 P60 to P67 Port 6 P70 to P73 Note 1 Por...
Page 35 - Overview of Functions
CHAPTER 1 GENERAL User’s Manual U15331EJ4V1UD 35 1.7 Overview of Functions (1/2) Item µ PD789488 µ PD78F9488 µ PD789489 µ PD78F9489 ROM 32 KB 32 KB (flash memory) 48 KB 48 KB (flash memory) High-speed RAM 1024 bytes Low-speed RAM − 512 bytes Internal memory LCD display RAM 28 bytes Main system clock...
Page 36 - An outline of the timer is shown below.
CHAPTER 1 GENERAL 36 User’s Manual U15331EJ4V1UD (2/2) Item µ PD789488 µ PD78F9488 µ PD789489 µ PD78F9489 Supply voltage V DD = 1.8 to 5.5 V Operating ambient temperature T A = − 40 to +85 ° C Package • 80-pin plastic QFP (14 × 14) • 80-pin plastic TQFP (fine pitch) (12 × 12) An outline of the timer...
Page 38 - CHAPTER 2 PIN FUNCTIONS; the; selected in 1-bit units by means of a mask option in the; CHAPTER 20 MASK
CHAPTER 2 PIN FUNCTIONS User’s Manual U15331EJ4V1UD 38 (1) Port pins (2/2) Pin Name I/O Function After Reset Alternate Function P70 to P73 Note 1 Input Port 7. 4-bit input port. (Only when input port is selected by mask option or port function register) Input − P80 to P87 Note 2 I/O Port 8. 8-bit I/...
Page 40 - Description of Pin Functions; mode; These are the serial data I/O pins of the serial interface.
CHAPTER 2 PIN FUNCTIONS User’s Manual U15331EJ4V1UD 40 2.2 Description of Pin Functions 2.2.1 P00 to P07 (Port 0) These pins constitute an 8-bit I/O port. In addition, these pins enable key return signal detection. Port 0 can be specified in the following operation modes in 1-bit units. (1) Port mod...
Page 41 - remote control receive data input; These are the external clock input pins of timers 60 and 61.
CHAPTER 2 PIN FUNCTIONS User’s Manual U15331EJ4V1UD 41 2.2.4 P30 to P34 (Port 3) These pins constitute a 5-bit I/O port. In addition, they also function as timer I/O, external interrupt input, and remote control receive data input Note . Port 3 can be specified in the following operation modes in 1-...
Page 42 - key return signal detection; mask option in the
CHAPTER 2 PIN FUNCTIONS User’s Manual U15331EJ4V1UD 42 2.2.6 P60 to P67 (Port 6) This is an 8-bit input-only port. In addition to a general-purpose input port function, it has A/D converter input and key return signal detection Note functions. (1) Port mode In this mode, P60 to P67 function as an 8-...
Page 45 - Pin I/O Circuits and Recommended Connection of Unused Pins; Notes; When
CHAPTER 2 PIN FUNCTIONS User’s Manual U15331EJ4V1UD 45 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 2-1. For the I/O circuit configuration of each type, see Figure 2-1. Table 2-1. Types of...
Page 48 - CHAPTER 3 CPU ARCHITECTURE; The
48 User’s Manual U15331EJ4V1UD CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space The µ PD789489 Subseries can access 64 KB of memory space. Figures 3-1 to 3-4 show the memory maps. Figure 3-1. Memory Map ( µ PD789488) 8 0 0 0 H 7 F F F H Special function registers 256 × 8 bits Internal high-speed RAM 1024...
Page 58 - Processor Registers; Figure 3-9. Program Counter Configuration; Figure 3-10. Program Status Word Configuration
CHAPTER 3 CPU ARCHITECTURE 58 User’s Manual U15331EJ4V1UD 3.2 Processor Registers The µ PD789489 Subseries is provided with the following on-chip processor registers. 3.2.1 Control registers The control registers contain special functions to control the program sequence status and stack memory. The ...
Page 60 - Figure 3-11. Stack Pointer Configuration
CHAPTER 3 CPU ARCHITECTURE 60 User’s Manual U15331EJ4V1UD (3) Stack pointer (SP) This is a 16-bit register that holds the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 3-11. Stack Pointer Configuration 0 15 SP14 SP15 SP SP13 SP12 S...
Page 62 - manipulation can also be specified with an address.
CHAPTER 3 CPU ARCHITECTURE 62 User’s Manual U15331EJ4V1UD 3.2.3 Special function registers (SFRs) Unlike a general-purpose register, each special function register has a special function. The special function registers are allocated in the 256-byte area of FF00H to FFFFH. Special function registers ...
Page 64 - These registers function only in the
CHAPTER 3 CPU ARCHITECTURE 64 User’s Manual U15331EJ4V1UD Table 3-4. Special Function Registers (2/3) Bit Unit for Manipulation Address Special Function Register (SFR) Name Symbol R/W 1 Bit 8 Bits 16 Bits After Reset FF40H 8-bit H width compare register 61 CRH61 W − √ − Undefined FF41H 8-bit timer m...
Page 66 - Instruction Address Addressing
CHAPTER 3 CPU ARCHITECTURE 66 User’s Manual U15331EJ4V1UD 3.3 Instruction Address Addressing An instruction address is determined by the program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be f...
Page 67 - In case of CALL !addr16 and BR !addr16 instructions
CHAPTER 3 CPU ARCHITECTURE User’s Manual U15331EJ4V1UD 67 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 instruction is executed. CALL !addr16 and B...
Page 69 - Operand Address Addressing; manipulation during instruction execution.
CHAPTER 3 CPU ARCHITECTURE User’s Manual U15331EJ4V1UD 69 3.4 Operand Address Addressing The following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 Direct addressing [Function] The memory indicated with i...
Page 74 - Instruction code
CHAPTER 3 CPU ARCHITECTURE 74 User’s Manual U15331EJ4V1UD 3.4.6 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive n...
Page 75 - CHAPTER 2 PIN FUNCTIONS
User’s Manual U15331EJ4V1UD 75 CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions The µ PD789489 Subseries provides the ports shown in Figure 4-1, enabling various methods of control. The functions of each port are shown in Table 4-1. Numerous other functions are provided that can be used in addition to th...
Page 76 - CHAPTER 4 PORT FUNCTIONS; selected in 1-bit units by means of a mask option for the; Port Configuration
CHAPTER 4 PORT FUNCTIONS 76 User’s Manual U15331EJ4V1UD Table 4-1. Port Functions Port Name Pin Name Function Port 0 P00 to P07 I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option r...
Page 77 - Figure 4-2. Block Diagram of P00 to P07; WR; RD; Output latch; Port mode register
CHAPTER 4 PORT FUNCTIONS User’s Manual U15331EJ4V1UD 77 4.2.1 Port 0 This is an 8-bit I/O port with an output latch. Port 0 can be specified in the input or output mode in 1-bit units by using port mode register 0 (PM0). When the P00 to P07 pins are used as input port pins, on-chip pull-up resistors...
Page 78 - Figure 4-3. Block Diagram of P10 and P11
CHAPTER 4 PORT FUNCTIONS 78 User’s Manual U15331EJ4V1UD 4.2.2 Port 1 This is a 2-bit I/O port with an output latch. Port 1 can be specified in the input or output mode in 1-bit units by using port mode register 1 (PM1). When using the P10 and P11 pins as input port pins, on-chip pull-up resistors ca...
Page 81 - Figure 4-6. Block Diagram of P22 and P25
CHAPTER 4 PORT FUNCTIONS User’s Manual U15331EJ4V1UD 81 Figure 4-6. Block Diagram of P22 and P25 P22/SI20/RxD20,P25/SI10 WR PUB2 RD WR PORT WR PM PUB22, PUB25 Alternate function Output latch (P22, P25) PM22, PM25 V DD P-ch Internal bus Selector PUB2: Pull-up resistor option register B2 PM: Port mode...
Page 86 - Port 5 read signal
CHAPTER 4 PORT FUNCTIONS 86 User’s Manual U15331EJ4V1UD 4.2.5 Port 5 This is a 4-bit N-ch open-drain I/O port with an output latch. Port 5 can be specified in the input or output mode in 1-bit units by using port mode register 5 (PM5). For a mask ROM version, use of an on-chip pull-up resistor can b...
Page 88 - Port 6 read signal
CHAPTER 4 PORT FUNCTIONS 88 User’s Manual U15331EJ4V1UD Figure 4-12. Block Diagram of P60 to P67 (2/2) (b) When µ PD789489, 78F9489 is used V REF RD Alternate function P60/ANI0/KR10 to P67/ANI7/KR17 + − KRM010, KRM014 to KRM017 WR KRM01 A/D converter Internal bus KRM01: Key return mode register 01 R...
Page 89 - option in the; Port 7 read signal
CHAPTER 4 PORT FUNCTIONS User’s Manual U15331EJ4V1UD 89 4.2.7 Port 7 This is a 4-bit input-only port. Only the bits for which the port function is selected can be used, by using a mask option in the µ PD789488 and 789489 or port function register 7 (PF7) in the µ PD78F9488 and 78F9489. Figure 4-13 s...
Page 90 - using a mask option in the; Port 8 read signal
CHAPTER 4 PORT FUNCTIONS 90 User’s Manual U15331EJ4V1UD 4.2.8 Port 8 This is an 8-bit I/O port with an output latch. Only the bits for which the port function is selected can be used, by using a mask option in the µ PD789488 and 789489 or port function register 8 (PF8) in the µ PD78F9488 and 78F9489...
Page 91 - Registers Controlling Port Function
CHAPTER 4 PORT FUNCTIONS User’s Manual U15331EJ4V1UD 91 4.3 Registers Controlling Port Function The ports are controlled by the following three types of registers. • Port mode registers (PM0 to PM3, PM5, PM8) • Pull-up resistor option registers (PUB0 to PUB3) • Port function registers (PF7, PF8) ( µ...
Page 92 - care
CHAPTER 4 PORT FUNCTIONS 92 User’s Manual U15331EJ4V1UD Table 4-3. Port Mode Registers and Output Latch Settings When Using Alternate Functions Alternate Function Pin Name Name I/O PM ×× P ×× P00 to P07 KR0 to KR7 or KR00 to KR07 Input 1 × INTP0 Input 1 × TO50 Output 0 0 P30 TMI60 Input 1 × INTP1 In...
Page 93 - Caution This register is valid only in the
CHAPTER 4 PORT FUNCTIONS User’s Manual U15331EJ4V1UD 93 (2) Pull-up resistor option registers (PUB0 to PUB3) These registers set whether to use on-chip pull-up resistors for pins P00 to P07, P10, P11, P20 to P25, and P30 to P34. An on-chip pull-up resistor can be used only for those bits set to the ...
Page 94 - Port Function Operation
CHAPTER 4 PORT FUNCTIONS 94 User’s Manual U15331EJ4V1UD 4.4 Port Function Operation The operation of a port differs depending on whether the port is set in the input or output mode, as described below. 4.4.1 Writing to I/O port (1) In output mode A value can be written to the output latch of a port ...
Page 95 - Main system clock oscillator; Clock Generator Configuration; Table 5-1. Configuration of Clock Generator
User’s Manual U15331EJ4V1UD 95 CHAPTER 5 CLOCK GENERATOR 5.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are used. • Main system clock oscillator This circuit oscillates at 1....
Page 96 - CHAPTER 5 CLOCK GENERATOR
CHAPTER 5 CLOCK GENERATOR 96 User’s Manual U15331EJ4V1UD Figure 5-1. Clock Generator Block Diagram ( µ PD789488, 789489) f XT 8f XT f XTT X1 X2 XT1 XT2 f X f X 2 2 f XTT 2 1/2 Prescaler Standby controller Wait controller Mask option STOP MCC PCC1 CLS Internal bus CSS0 FRC SCC Internal bus Timer 50Wa...
Page 98 - Registers Controlling Clock Generator; Processor clock control register (PCC); Figure 5-3. Format of Processor Clock Control Register; : Main system clock oscillation frequency; : Subsystem clock oscillation frequency
CHAPTER 5 CLOCK GENERATOR 98 User’s Manual U15331EJ4V1UD 5.3 Registers Controlling Clock Generator The clock generator is controlled by the following four registers. • Processor clock control register (PCC) • Subclock oscillation mode register (SCKM) • Subclock control register (CSS) • Subclock sele...
Page 99 - oscillation; Bit 5 is read only.
CHAPTER 5 CLOCK GENERATOR User’s Manual U15331EJ4V1UD 99 (2) Subclock oscillation mode register (SCKM) SCKM selects a feedback resistor for the subsystem clock, and controls the oscillation of the clock. SCKM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SCKM to 00H....
Page 100 - This register is used to control the operation of the; The register is set to 00H only by RESET input.
CHAPTER 5 CLOCK GENERATOR 100 User’s Manual U15331EJ4V1UD (4) Subclock selection register (SSCK) ( µ PD78F9488, 78F9489 only) This register is used to control the operation of the × 4 subsystem clock multiplication circuit. SSCK is set via a 1-bit or 8-bit memory manipulation instruction. RESET inpu...
Page 101 - System Clock Oscillators; across the X1 and X2 pins.; Figure 5-7. External Circuit of Main System Clock Oscillator; Keep the wiring length as short as possible.; Do not fetch signals from the oscillator.
CHAPTER 5 CLOCK GENERATOR User’s Manual U15331EJ4V1UD 101 5.4 System Clock Oscillators 5.4.1 Main system clock oscillator The main system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 MHz TYP.) connected across the X1 and X2 pins. An external clock can also be input to the ...
Page 102 - inverted signal to the XT2 pin.; Figure 5-8. External Circuit of Subsystem Clock Oscillator
CHAPTER 5 CLOCK GENERATOR 102 User’s Manual U15331EJ4V1UD 5.4.2 Subsystem clock oscillator The subsystem clock oscillator is oscillated by the crystal resonator (32.768 kHz TYP.) connected across the XT1 and XT2 pins. An external clock can also be input to the circuit. In this case, input the clock ...
Page 103 - Example of incorrect resonator connection; (c) Wiring near high fluctuating current
CHAPTER 5 CLOCK GENERATOR User’s Manual U15331EJ4V1UD 103 5.4.3 Example of incorrect resonator connection Figure 5-9 shows examples of incorrect resonator connection. Figure 5-9. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line V SS X1 X2 V SS X1 X2 PORTn ...
Page 104 - handle the XT1 and XT2 pins as follows.; multiplication circuit; inserted to eliminate noise.
CHAPTER 5 CLOCK GENERATOR 104 User’s Manual U15331EJ4V1UD Figure 5-9. Examples of Incorrect Resonator Connection (2/2) (e) Signal is fetched V SS X1 X2 Remark When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect a resistor to XT2 in series. 5.4.4 Divider circuit T...
Page 105 - Clock Generator Operation
CHAPTER 5 CLOCK GENERATOR User’s Manual U15331EJ4V1UD 105 5.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as the standby mode. • Main system clock f X • Subsystem clock f XT • CPU clock f CPU • Clock to peripheral har...
Page 106 - Changing Setting of System Clock and CPU Clock; is used for the duration of several instructions after that (see; Table 5-2. Maximum Time Required for Switching CPU Clock; The parenthesized values apply to operation at f
CHAPTER 5 CLOCK GENERATOR 106 User’s Manual U15331EJ4V1UD 5.6 Changing Setting of System Clock and CPU Clock 5.6.1 Time required for switching between system clock and CPU clock The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC) and bit 4 (CSS0) of the ...
Page 107 - Switching between system clock and CPU clock; Caution
CHAPTER 5 CLOCK GENERATOR User’s Manual U15331EJ4V1UD 107 5.6.2 Switching between system clock and CPU clock The following figure illustrates how the CPU clock and system clock switch. Figure 5-10. Switching Between System Clock and CPU Clock System clock CPU clock Interrupt request signal RESET V D...
Page 108 - interrupt
108 User’s Manual U15331EJ4V1UD CHAPTER 6 16-BIT TIMER 20 6.1 16-Bit Timer 20 Functions 16-bit timer 20 has the following functions. • Timer interrupt • Timer output • Count value capture (1) Timer interrupt An interrupt is generated when a count value and compare value match. (2) Timer output Timer...
Page 109 - occurred during the oscillation stabilization time.
CHAPTER 6 16-BIT TIMER 20 User’s Manual U15331EJ4V1UD 109 Figure 6-1. Block Diagram of 16-Bit Timer 20 CPT20/TO20 /INTP3/P33 Internal bus Internal bus 16-bit timer modecontrol register 20(TMC20) 16-bit timer modecontrol register 20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20 f X f X /2 2 Edge dete...
Page 110 - Registers Controlling 16-Bit Timer 20
CHAPTER 6 16-BIT TIMER 20 110 User’s Manual U15331EJ4V1UD (4) 16-bit counter read buffer 20 This buffer is used to latch and hold the count value for TM20. 6.3 Registers Controlling 16-Bit Timer 20 16-bit timer 20 is controlled by the following three registers. • 16-bit timer mode control register 2...
Page 111 - Figure 6-2. Format of 16-Bit Timer Mode Control Register 20; If f
CHAPTER 6 16-BIT TIMER 20 User’s Manual U15331EJ4V1UD 111 Figure 6-2. Format of 16-Bit Timer Mode Control Register 20 Symbol <7> <6> 5 4 3 2 1 <0> Address After reset R/W TMC20 TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20 FF48H 00H R/W Note 1 TOD20 Timer output data 0 Timer ...
Page 112 - Figure 6-3. Format of Port Mode Register 3
CHAPTER 6 16-BIT TIMER 20 112 User’s Manual U15331EJ4V1UD (2) Port mode register 3 (PM3) This register is used to set the I/O mode of port 3 in 1-bit units. When using the P33/INTP3/CPT20/TO20 pin as a capture input (CPT20), set PM33 to 1. When using the above pin as a timer output (TO20), set the P...
Page 113 - : Main system clock oscillation frequency
CHAPTER 6 16-BIT TIMER 20 User’s Manual U15331EJ4V1UD 113 6.4 16-Bit Timer 20 Operation 6.4.1 Operation as timer interrupt 16-bit timer 20 can generate interrupts repeatedly each time the free-running counter value reaches the value set to CR20. Since this counter is not cleared and holds the count ...
Page 116 - capture trigger edge detection during TCP20 read.
CHAPTER 6 16-BIT TIMER 20 116 User’s Manual U15331EJ4V1UD 6.4.3 Capture operation The capture operation consists of latching the count value of 16-bit timer counter 20 (TM20) into a capture register in synchronization with a capture trigger, and retaining the count value. Set TMC20 as shown in Figur...
Page 118 - Restrictions when rewriting 16-bit compare register 20; the start of the interrupt.
CHAPTER 6 16-BIT TIMER 20 118 User’s Manual U15331EJ4V1UD 6.5 Cautions on Using 16-Bit Timer 20 6.5.1 Restrictions when rewriting 16-bit compare register 20 (1) Disable interrupts (TMMK20 = 1) and inversion control of timer output (TOC20 = 0) before rewriting the compare register (CR20). If the valu...
Page 119 - NOP
CHAPTER 6 16-BIT TIMER 20 User’s Manual U15331EJ4V1UD 119 <Countermeasure B> When rewriting using 16-bit access <1> Disable interrupts (TMMK20 = 1) and inversion control of timer output (TOC20 = 0). <2> Rewrite CR20 (16 bits). <3> Wait for one cycle or more of the count clock...
Page 123 - CHA
CHA PTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 123 Figure 7-2. Block Diagram of Timer 50 TEG50 TCL500 TCL501 8-bit timer mode control register 50 (TMC50) Decoder Selector Selector 8-bit compare register 50 (CR50) 8-bit timer counter 50 (TM50) Selector Count operation start signa...
Page 126 - Carrier generator mode
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 126 Figure 7-5. Block Diagram of Output Controller (Timer 60) F/F RMC60 NRZ60 TOE60 PM31 P31 output latch Selector TO60/INTP1/P31 Carrier generator mode Carrier clock (1) 8-bit compare register 50 (CR50) This 8-bit register is used to...
Page 129 - To manipulate TMC50, follow the setting procedure below.
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 129 Figure 7-6. Format of 8-Bit Timer Mode Control Register 50 (2/2) Symbol <7> <6> 5 4 3 2 1 <0> Address After reset R/W TMC50 TCE50 TEG50 TCL502 TCL501 TCL500 TMD501 TMD500 TOE50 FF4DH 00H R/W TOE50 Control of time...
Page 130 - any setting for TCE50 is ignored.; : External input clock frequency
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 130 Figure 7-7. Format of 8-Bit Timer Mode Control Register 60 Symbol <7> 6 5 4 3 2 1 <0> Address After reset R/W TMC60 TCE60 0 TCL602 TCL601 TCL600 TMD601 TMD600 TOE600 FF4EH 00H R/W TCE60 Control of TM60 count operation ...
Page 131 - Figure 7-8. Format of Carrier Generator Output Control Register 60; Bit 0 is write-only; NRZB60, input the data required by the program in advance.
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 131 (3) Carrier generator output control register 60 (TCA60) This register is used to set the timer output data in carrier generator mode. TCA60 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this regis...
Page 133 - Figure 7-10. Format of Port Mode Register 3
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 133 (5) Port mode register 3 (PM3) This register is used to set the I/O mode of port 3 in 1-bit units. When using the P30/INTP0/TO50/TMI60 pin as a timer output (TO50), set PM30 and the P30 output latch to 0. When used as a timer inpu...
Page 137 - FFH
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 137 Figure 7-13. Timing of Interval Timer Operation with 8-Bit Resolution (When CRnm Is Set to FFH) Count clock CRnm TCEnm INTTMnm TOnm FFH TMnm FFH 00H 01H 00H 01H 00H FFH 00H 01H FFH FFH 00H Clear Clear Clear Count start Remark nm =...
Page 141 - Remarks; : Subsystem clock oscillation frequency
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 141 (3) Operation as square-wave output with 8-bit resolution Square waves of any frequency can be output at an interval specified by the value preset in 8-bit compare register nm (CRnm). To operate timer nm for square-wave output, se...
Page 146 - (2) Operation as external event counter with 16-bit resolution
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 146 (2) Operation as external event counter with 16-bit resolution The external event counter counts the number of external clock pulses input to the TMI60 pin by TM50 and TM60. To operate as an external event counter with 16-bit reso...
Page 148 - : Main system clock oscillation frequency
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 148 (3) Operation as square-wave output with 16-bit resolution Square waves of any frequency can be output at an interval specified by the count value preset in CR50 and CR60. To operate as a square-wave output with 16-bit resolution,...
Page 149 - The initial value of TO60 is low level when output is enabled.
CHA PTER 7 8-BIT TIMERS 50, 60, A ND 61 User’s Manual U15331EJ4V1UD 149 Count clock TM60 count value CR60 TCE60 INTTM60 TO60 Note FFH 00H 7FH 00H N 00H N N N N 80H 7FH 80H FFH 00H N 00H N N N TM50 count pulse TM50 00H X X − 1 01H CR50 X X X 7FH 80H FFH 00H N 00H N N N X X − 1 00H Not cleared because...
Page 154 - the PWM output mode.; may not be performed normally.
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 154 7.4.4 PWM output mode operation (timer 50) In the PWM output mode, TO50 becomes high level when TM50 overflows, and TO50 becomes low level when CR50 and TM50 match. It is thus possible to output a pulse with any duty ratio (free-r...
Page 158 - in the PPG output mode.
CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 158 7.4.5 PPG output mode operation (timer 60 and timer 61) In the PPG output mode, a pulse of any duty ratio can be output by setting a low-level width using CR6m and a high-level width using CRH6m. To operate timer 6m in PPG output ...
Page 161 - Watch timer; Figure 8-1. Block Diagram of Watch Timer
User’s Manual U15331EJ4V1UD 161 CHAPTER 8 WATCH TIMER 8.1 Watch Timer Functions The watch timer has the following functions. • Watch timer • Interval timer The watch and interval timers can be used at the same time. Figure 8-1 shows a block diagram of the watch timer. Figure 8-1. Block Diagram of Wa...
Page 162 - CHAPTER 8 WATCH TIMER; Table 8-1. Interval Time of Interval Timer; Configuration of Watch Timer; Table 8-2. Configuration of Watch Timer
CHAPTER 8 WATCH TIMER 162 User’s Manual U15331EJ4V1UD (1) Watch timer An interrupt request (INTWT) occurs at an interval of 0.5 second when using either the 4.19 MHz main system clock or the 32.768 kHz subsystem clock. Also, an interrupt request (INTWT) occurs at an interval of 1.0 seconds when usin...
Page 163 - Control Registers for Watch Timer; Figure 8-2. Format of Watch Timer Mode Control Register
CHAPTER 8 WATCH TIMER User’s Manual U15331EJ4V1UD 163 8.3 Control Registers for Watch Timer The watch timer is controlled by the following registers. • Watch timer mode control register (WTM) • Watch timer interrupt time selection register (WTIM) (1) Watch timer mode control register (WTM) This regi...
Page 165 - Watch Timer Operation; seconds may occur in the overflow; Table 8-3. Interval Time of Interval Timer
CHAPTER 8 WATCH TIMER User’s Manual U15331EJ4V1UD 165 8.4 Watch Timer Operation 8.4.1 Operation as watch timer The main system clock (4.19 MHz) or subsystem clock (32.768 kHz) is used to enable the watch timer to operate at 0.5-second intervals. Also, an interrupt request (INTWT) occurs at an interv...
Page 166 - : Watch timer clock frequency
CHAPTER 8 WATCH TIMER 166 User’s Manual U15331EJ4V1UD Figure 8-4. Watch Timer/Interval Timer Operation Timing 0H Start Overflow Overflow 5-bit counter Count clockf W /2 9 Watch timerinterrupt INTWT Interval timerinterrupt INTWTI Watch timer interrupt time (0.5 s) Watch timer interrupt time (0.5 s) I...
Page 167 - Watchdog timer; timer
User’s Manual U15331EJ4V1UD 167 CHAPTER 9 WATCHDOG TIMER 9.1 Watchdog Timer Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (WDTM). (1) Watchdog timer T...
Page 168 - CHAPTER 9 WATCHDOG TIMER; Watchdog Timer Configuration; Table 9-3. Configuration of Watchdog Timer; Figure 9-1. Block Diagram of Watchdog Timer
CHAPTER 9 WATCHDOG TIMER 168 User’s Manual U15331EJ4V1UD 9.2 Watchdog Timer Configuration The watchdog timer includes the following hardware. Table 9-3. Configuration of Watchdog Timer Item Configuration Control registers Watchdog timer clock selection register (WDCS) Watchdog timer mode register (W...
Page 169 - Watchdog Timer Control Registers; Figure 9-2. Format of Watchdog Timer Clock Selection Register
CHAPTER 9 WATCHDOG TIMER User’s Manual U15331EJ4V1UD 169 9.3 Watchdog Timer Control Registers The watchdog timer is controlled by the following two registers. • Watchdog timer clock selection register (WDCS) • Watchdog timer mode register (WDTM) (1) Watchdog timer clock selection register (WDCS) Thi...
Page 170 - Figure 9-3. Format of Watchdog Timer Mode Register; started, it cannot be stopped by any means other than RESET input.
CHAPTER 9 WATCHDOG TIMER 170 User’s Manual U15331EJ4V1UD (2) Watchdog timer mode register (WDTM) This register sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM ...
Page 171 - Watchdog Timer Operation; clear the watchdog timer before executing the STOP instruction.; Table 9-4. Watchdog Timer Program Loop Detection Time
CHAPTER 9 WATCHDOG TIMER User’s Manual U15331EJ4V1UD 171 9.4 Watchdog Timer Operation 9.4.1 Operation as watchdog timer The watchdog timer detects a program loop when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1. The count clock (program loop detection time interval) of the w...
Page 172 - clear the interval timer before executing the STOP instruction.; timer mode is not set unless the RESET signal is input.
CHAPTER 9 WATCHDOG TIMER 172 User’s Manual U15331EJ4V1UD 9.4.2 Operation as interval timer When bits 4 and 3 (WDTM4, WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1, respectively, the watchdog timer operates as an interval timer that repeatedly generates an interrupt at interval...
Page 176 - When f
CHAPTER 10 10-BIT A/D CONVERTER 176 User’s Manual U15331EJ4V1UD 10.3 10-Bit A/D Converter Control Registers The 10-bit A/D converter is controlled by the following two registers. • A/D converter mode register 0 (ADML0) • Analog input channel specification register 0 (ADS0) (1) A/D converter mode reg...
Page 177 - Caution Bits 3 to 7 must be set to 0.
CHAPTER 10 10-BIT A/D CONVERTER User’s Manual U15331EJ4V1UD 177 Cautions 1. Start conversion (ADCS0 = 1) after 14 µ s have elapsed following the setting of ADCE0. If ADCE0 is not used, the conversion result immediately after the setting of bit 7 (ADCS0) is undefined. 2. The conversion result may be ...
Page 178 - s have elapsed following the setting of ADCE0.
CHAPTER 10 10-BIT A/D CONVERTER 178 User’s Manual U15331EJ4V1UD 10.4 10-Bit A/D Converter Operation 10.4.1 Basic operation of 10-bit A/D converter <1> Bit 0 of A/D converter mode register 0 (ADML0) is set (ADCE0 = 1). <2> Select a channel for A/D conversion, using analog input channel sp...
Page 179 - Input voltage and conversion result
CHAPTER 10 10-BIT A/D CONVERTER User’s Manual U15331EJ4V1UD 179 Figure 10-4. Basic Operation of 10-Bit A/D Converter Conversion time Sampling time Sampling A/D conversion Undefined Conversion result Conversion result A/D converter operation SAR ADCRL0 INTAD0 A/D conversion continues until bit 7 (ADC...
Page 182 - or less than or equal to AV; reading from ADCRL0 using instruction; (4) Conversion result immediately after start of A/D conversion; s has elapsed following
CHAPTER 10 10-BIT A/D CONVERTER 182 User’s Manual U15331EJ4V1UD 10.5 Cautions Related to 10-Bit A/D Converter (1) Current consumption in standby mode In standby mode, the A/D converter stops operation. Clearing bit 7 (ADCS0) and bit 0 (ADCE0) of A/D converter mode register 0 (ADML0) to 0 can reduce ...
Page 184 - prevention; To maintain a resolution of 10 bits, watch for noise at the AV; and ANI0 to ANI7 pins. The higher the output; Figure 10-10. Analog Input Pin Handling
CHAPTER 10 10-BIT A/D CONVERTER 184 User’s Manual U15331EJ4V1UD (6) Noise prevention To maintain a resolution of 10 bits, watch for noise at the AV DD and ANI0 to ANI7 pins. The higher the output impedance of the analog input source, the larger the effect by noise. To reduce noise, attach an externa...
Page 185 - pin; Pin Handling; pin input impedance
CHAPTER 10 10-BIT A/D CONVERTER User’s Manual U15331EJ4V1UD 185 (9) Interrupt request flag (ADIF0) Changing the contents of A/D converter mode register 0 (ADML0) does not clear the interrupt request flag (ADIF0). If the analog input pins are changed during A/D conversion, therefore, the A/D conversi...
Page 186 - Serial interface 20 has the following three modes.; serial; Serial Interface 20 Configuration; Table 11-1. Configuration of Serial Interface 20
186 User’s Manual U15331EJ4V1UD CHAPTER 11 SERIAL INTERFACE 20 11.1 Serial Interface 20 Functions Serial interface 20 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial transf...
Page 187 - Figure 11-1. Block Diagram of Serial Interface 20; See
CHA PTER 11 SERIA L INTERFA C E 20 User’s Manual U15331EJ4V1UD 187 Internal bus Receive buffer register 20 (RXB20) Switch of the first bit Asynchronous serial interface status register 20 (ASIS20) Serial operation mode register 20 (CSIM20) Receive shift register 20 (RXS20) CSIE20 DIR20 CSCK20 PE20 F...
Page 188 - Figure 11-2. Block Diagram of Baud Rate Generator 20
CHA PTER 11 SERIA L INTERFA C E 20 188 User’s Manual U15331EJ4V1UD Clock for receive detection Transmit shift clock Receive shift clock Receive detection TXE20 RXE20 CSIE20 1/2 1/2 Transmit clockcounter (3 bits) Receive clockcounter (3 bits) 4 f X /2 f X /2 3 f X /2 4 f X /2 5 f X /2 6 f X /2 7 f X ...
Page 189 - CHAPTER 11 SERIAL INTERFACE 20; attempt to write to RXB20 results in a value being written to TXS20.
CHAPTER 11 SERIAL INTERFACE 20 User’s Manual U15331EJ4V1UD 189 (1) Transmit shift register 20 (TXS20) TXS20 is a register in which transmit data is prepared. The transmit data is output from TXS20 bit-serially. When the data length is seven bits, bits 0 to 6 of the data in TXS20 will be transmit dat...
Page 190 - Serial Interface 20 Control Registers; Figure 11-3. Format of Serial Operation Mode Register 20
CHAPTER 11 SERIAL INTERFACE 20 190 User’s Manual U15331EJ4V1UD 11.3 Serial Interface 20 Control Registers Serial interface 20 is controlled by the following six registers. • Serial operation mode register 20 (CSIM20) • Asynchronous serial interface mode register 20 (ASIM20) • Asynchronous serial int...
Page 192 - Table 11-2. Serial Interface 20 Operation Mode Settings; These pins can be used for port functions.
CHAPTER 11 SERIAL INTERFACE 20 192 User’s Manual U15331EJ4V1UD Table 11-2. Serial Interface 20 Operation Mode Settings (1) Operation stop mode ASIM20 CSIM20 TXE20 RXE20 CSIE20 DIR20 CSCK20 PM22 P22 PM21 P21 PM20 P20 First Bit Shift Clock P22/SI20/ RxD20 Pin Function P21/SO20/ TxD20 Pin Function P20/...
Page 193 - overrun error will occur every time data is received.
CHAPTER 11 SERIAL INTERFACE 20 User’s Manual U15331EJ4V1UD 193 (3) Asynchronous serial interface status register 20 (ASIS20) ASIS20 indicates the type of a reception error, if it occurs while asynchronous serial interface mode is set. ASIS20 is set with a 1-bit or 8-bit memory manipulation instructi...
Page 194 - Figure 11-6. Format of Baud Rate Generator Control Register 20; An external clock can be used only in UART mode.; Be sure not to select n = 1 in UART mode when f
CHAPTER 11 SERIAL INTERFACE 20 194 User’s Manual U15331EJ4V1UD (4) Baud rate generator control register 20 (BRGC20) BRGC20 is used to specify the serial clock for serial interface 20. BRGC20 is set with an 8-bit memory manipulation instruction. RESET input sets BRGC20 to 00H. Figure 11-6. Format of ...
Page 195 - : Main system clock oscillation frequency; Caution Do not select n = 1 during operation at f
CHAPTER 11 SERIAL INTERFACE 20 User’s Manual U15331EJ4V1UD 195 The baud rate transmit/receive clock to be generated is either a divided system clock signal, or a signal obtained by dividing the clock input to the ASCK20 pin. (a) Generation of UART baud rate transmit/receive clock form system clock T...
Page 196 - : Frequency of clock input to the ASCK20 pin; Table 11-4. Relationship Between ASCK20 Pin Input Frequency
CHAPTER 11 SERIAL INTERFACE 20 196 User’s Manual U15331EJ4V1UD (b) Generation of UART baud rate transmit/receive clock from external clock input to ASCK20 pin The transmit/receive clock is generated by dividing the clock input from the ASCK20 pin. The baud rate of a clock generated from the clock in...
Page 197 - Serial Interface 20 Operation; Operation stop mode; setting
CHAPTER 11 SERIAL INTERFACE 20 User’s Manual U15331EJ4V1UD 197 11.4 Serial Interface 20 Operation Serial interface 20 provides the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode 11.4.1 Operation stop mode In operation stop mode, seri...
Page 198 - Caution Bits 0 and 1 must be set to 0.
CHAPTER 11 SERIAL INTERFACE 20 198 User’s Manual U15331EJ4V1UD (b) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM20 to 00H. TXE20 0 1 Transmit operation control Transmit operation stopped Transmit ope...
Page 202 - Can only be used in the UART mode.; Be sure not to select n = 1 during operation at f
CHAPTER 11 SERIAL INTERFACE 20 202 User’s Manual U15331EJ4V1UD (d) Baud rate generator control register 20 (BRGC20) BRGC20 is set with an 8-bit memory manipulation instruction. RESET input sets BRGC20 to 00H. TPS203 0 0 0 0 0 0 0 0 1 TPS202 0 0 0 0 1 1 1 1 0 f X /2 f X /2 2 f X /2 3 f X /2 4 f X /2 ...
Page 203 - : Frequency of clock input to ASCK20 pin; Table 11-6. Relationship Between ASCK20 Pin Input Frequency
CHAPTER 11 SERIAL INTERFACE 20 User’s Manual U15331EJ4V1UD 203 Table 11-5. Example of Relationship Between System Clock and Baud Rate Error (%) Baud Rate (bps) n BRGC20 Set Value f X = 5.0 MHz f X = 4.9152 MHz 1,200 8 70H 2,400 7 60H 4,800 6 50H 9,600 5 40H 19,200 4 30H 38,400 3 20H 76,800 2 10H 1.7...
Page 204 - operation
CHAPTER 11 SERIAL INTERFACE 20 204 User’s Manual U15331EJ4V1UD (2) Communication operation (a) Data format The transmit/receive data format is as shown in Figure 11-7. One data frame consists of a start bit, character bits, parity bit, and stop bit(s). The specification of character bit length in on...
Page 205 - parity
CHAPTER 11 SERIAL INTERFACE 20 User’s Manual U15331EJ4V1UD 205 (b) Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-...
Page 208 - Figure
CHAPTER 11 SERIAL INTERFACE 20 208 User’s Manual U15331EJ4V1UD (e) Receive errors The following three errors may occur during a receive operation: a parity error, framing error, and overrun error. After data reception, an error flag is set in asynchronous serial interface status register 20 (ASIS20)...
Page 210 - When RXE20 is set to 0 at the time indicated by
CHAPTER 11 SERIAL INTERFACE 20 210 User’s Manual U15331EJ4V1UD (3) Cautions related to UART mode (a) When bit 7 (TXE20) of asynchronous serial interface mode register 20 (ASIM20) is cleared during transmission, be sure to set transmit shift register 20 (TXS20) to FFH, then set TXE20 to 1 before exec...
Page 214 - The value of the last bit previously output is output.
CHAPTER 11 SERIAL INTERFACE 20 214 User’s Manual U15331EJ4V1UD (2) Communication operation In 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/ received bit by bit in synchronization with the serial clock. Transmit shift register 20 (TXS20/SIO20) a...
Page 215 - start
CHAPTER 11 SERIAL INTERFACE 20 User’s Manual U15331EJ4V1UD 215 Figure 11-11. 3-Wire Serial I/O Mode Timing (2/2) (ii) Slave operation timing (CSCK20=1) 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SCK20 SI20 Note SO20 SIO20 write INTCSI20 Note The value of the last...
Page 216 - Serial interface 1A0 has the following three modes.
216 User’s Manual U15331EJ4V1UD CHAPTER 12 SERIAL INTERFACE 1A0 12.1 Function of Serial Interface 1A0 Serial interface 1A0 has the following three modes. • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function (1) Operation stop mode This mode...
Page 217 - CHAPTER 12 SERIAL INTERFACE 1A0; Configuration of Serial Interface 1A0; Table 12-1. Configuration of Serial Interface 1A0; Figure 12-1. Block Diagram of Serial Interface 1A0
CHAPTER 12 SERIAL INTERFACE 1A0 User’s Manual U15331EJ4V1UD 217 12.2 Configuration of Serial Interface 1A0 Serial interface 1A0 includes the following hardware. Table 12-1. Configuration of Serial Interface 1A0 Item Configuration Registers Serial I/O shift register 1A0 (SIO1A0) Automatic data transm...
Page 218 - This register stores value of (transmit data byte
CHAPTER 12 SERIAL INTERFACE 1A0 218 User’s Manual U15331EJ4V1UD (1) Serial I/O shift register 1A0 (SIO1A0) This is an 8-bit register used to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO1A0 is set w...
Page 219 - Control Registers for Serial Interface 1A0; Serial operation mode register 1A0 (CSIM1A0)
CHAPTER 12 SERIAL INTERFACE 1A0 User’s Manual U15331EJ4V1UD 219 12.3 Control Registers for Serial Interface 1A0 Serial interface 1A0 is controlled by the following five registers. • Serial operation mode register 1A0 (CSIM1A0) • Automatic data transmit/receive control register 0 (ADTC0) • Automatic ...
Page 220 - Figure 12-2. Format of Serial Operation Mode Register 1A0
CHAPTER 12 SERIAL INTERFACE 1A0 220 User’s Manual U15331EJ4V1UD Figure 12-2. Format of Serial Operation Mode Register 1A0 Symbol <7> 6 <5> <4> 3 2 1 0 Address After reset R/W CSIM1A0 CSIE10 DIR10 ATE0 LSCK10 0 0 SCL101 SCL100 FF78H 00H R/W Specification of operation enable/disable ...
Page 223 - The interval time depends only on the CPU processing.; : Serial clock frequency
CHAPTER 12 SERIAL INTERFACE 1A0 User’s Manual U15331EJ4V1UD 223 Figure 12-4. Format of Automatic Data Transmit/Receive Interval Specification Register 0 (2/2) Symbol <7> 6 5 <4> <3> <2> <1> <0> Address After reset R/W ADTI0 ADTI07 0 0 ADTI04 ADTI03 ADTI02 ADTI01 A...
Page 224 - Serial Interface 1A0 Operation
CHAPTER 12 SERIAL INTERFACE 1A0 224 User’s Manual U15331EJ4V1UD 12.4 Serial Interface 1A0 Operation Serial interface 1A0 provides the following three modes. • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function 12.4.1 Operation stop mode In ...
Page 229 - Figure 12-6. Circuit of Switching in Transfer Bit Order
CHAPTER 12 SERIAL INTERFACE 1A0 User’s Manual U15331EJ4V1UD 229 (3) MSB/LSB switching as the start bit In the 3-wire serial I/O mode, transfer can be selected to start from the MSB or LSB. Figure 12-6 shows the configuration of serial I/O shift register 1A0 (SIO1A0) and the internal bus. As shown in...
Page 235 - operation the written value has no meaning.
CHAPTER 12 SERIAL INTERFACE 1A0 User’s Manual U15331EJ4V1UD 235 (2) Automatic transmit/receive data setting (a) Transmit data setting <1> Write transmit data from the least significant address FFA0H of buffer RAM (up to FFAFH). The transmit data should be in the order from higher address to lo...
Page 236 - CSIIF10: Interrupt request flag
CHAPTER 12 SERIAL INTERFACE 1A0 236 User’s Manual U15331EJ4V1UD (3) Communication operation (a) Basic transmit/receive mode This transmit/receive mode is the same as the 3-wire serial I/O mode in which the specified number of data are transmitted/received in 8-bit units. Serial transfer is started w...
Page 237 - ADTP0: Automatic data transmit/receive address pointer 0
CHAPTER 12 SERIAL INTERFACE 1A0 User’s Manual U15331EJ4V1UD 237 Figure 12-8. Basic Transmit/Receive Mode Flowchart Remark ADTP0: Automatic data transmit/receive address pointer 0 ADTI0: Automatic data transmit/receive interval specification register 0 SIO1A0: Serial I/O shift register 1A0 TRF0: Bit ...
Page 240 - Figure 12-10. Basic Transmit Mode Operation Timing
CHAPTER 12 SERIAL INTERFACE 1A0 240 User’s Manual U15331EJ4V1UD (b) Basic transmit mode In this mode, the specified number of 8-bit unit data are transmitted. Serial transfer is started when any data is written to serial I/O shift register 1A0 (SIO1A0) while bit 7 (CSIE10) of serial operation mode r...
Page 241 - Figure 12-11. Basic Transmit Mode Flowchart; Automatic data transmit/receive address pointer 0
CHAPTER 12 SERIAL INTERFACE 1A0 User’s Manual U15331EJ4V1UD 241 Figure 12-11. Basic Transmit Mode Flowchart Remark ADTP0: Automatic data transmit/receive address pointer 0 ADTI0: Automatic data transmit/receive interval specification register 0 SIO1A0: Serial I/O shift register 1A0 TRF0: Bit 3 of au...
Page 244 - Figure 12-13. Repeat Transmit Mode Operation Timing
CHAPTER 12 SERIAL INTERFACE 1A0 244 User’s Manual U15331EJ4V1UD (c) Repeat transmit mode In this mode, data stored in the buffer RAM is transmitted repeatedly. Serial transfer is started by writing any data to serial shift I/O register 1A0 (SIO1A0) when bit 7 (CSIE10) of serial operation mode regist...
Page 245 - Figure 12-14. Repeat Transmit Mode Flowchart
CHAPTER 12 SERIAL INTERFACE 1A0 User’s Manual U15331EJ4V1UD 245 Figure 12-14. Repeat Transmit Mode Flowchart Start Write transmit data in buffer RAM Set ADTP0 to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Set the transmission/reception operation interv...
Page 247 - (c) Upon completion of transmission of 6 bytes
CHAPTER 12 SERIAL INTERFACE 1A0 User’s Manual U15331EJ4V1UD 247 Figure 12-15. Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmit Mode) (2/2) (c) Upon completion of transmission of 6 bytes Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) Transmit data 4 (T4) Transmit data 5...
Page 248 - (d) Automatic transmission/reception suspension and restart; CSIE10: Bit 7 of serial operation mode register 1A0 (CSIM1A0)
CHAPTER 12 SERIAL INTERFACE 1A0 248 User’s Manual U15331EJ4V1UD (d) Automatic transmission/reception suspension and restart Automatic transmission/reception can be temporarily suspended by setting bit 7 (CSIE10) of serial operation mode register 1A0 (CSIM1A0) to 0. During 8-bit data transfer, the tr...
Page 249 - (4) Timing of interrupt request signal generation; . If ADTI07 is set to 1, whichever is greater of the; ) determined by the CPU; Figure 12-17. Interval Time of Automatic Transmission/Reception
CHAPTER 12 SERIAL INTERFACE 1A0 User’s Manual U15331EJ4V1UD 249 (4) Timing of interrupt request signal generation The interrupt request signal is generated in synchronization with the timing shown in Table 12-2. Table 12-2. Timing of Interrupt Request Signal Generation Operation Mode Timing of Inter...
Page 250 - CHAPTER 13 LCD CONTROLLER/DRIVER; The functions of the LCD controller/driver of the; Usable mask option or port function register; Table 13-1. Maximum Number of Display Pixels; LCD Controller/Driver Configuration; The LCD controller/driver includes the following hardware.
250 User’s Manual U15331EJ4V1UD CHAPTER 13 LCD CONTROLLER/DRIVER 13.1 LCD Controller/Driver Functions The functions of the LCD controller/driver of the µ PD789489 Subseries are as follows. (1) Automatic output of segment and common signals based on automatic display data memory read (2) Two differen...
Page 251 - Figure 13-1. Correspondence with LCD Display RAM; Bits 4 to 7 are fixed to 0.
CHAPTER 13 LCD CONTROLLER/DRIVER User’s Manual U15331EJ4V1UD 251 The correspondence with the LCD display RAM is shown in Figure 13-1 below. Figure 13-1. Correspondence with LCD Display RAM Address Bit Segment 7 6 5 4 3 2 1 0 FA1BH 0 0 0 0 → S27 Note FA1AH 0 0 0 0 → S26 Note FA19H 0 0 0 0 → S25 Note ...
Page 253 - Registers Controlling LCD Controller/Driver
CHAPTER 13 LCD CONTROLLER/DRIVER User’s Manual U15331EJ4V1UD 253 13.3 Registers Controlling LCD Controller/Driver The LCD controller/driver is controlled by the following three registers. • LCD display mode register 0 (LCDM0) • LCD clock control register 0 (LCDC0) • LCD voltage boost control registe...
Page 254 - Figure 13-3. Format of LCD Display Mode Register 0
CHAPTER 13 LCD CONTROLLER/DRIVER 254 User’s Manual U15331EJ4V1UD (1) LCD display mode register 0 (LCDM0) LCDM0 specifies whether to enable display. It also specifies whether to enable booster circuit operation, segment pin/common pin output, and the display mode. LCDM0 is set with a 1-bit or 8-bit m...
Page 255 - Figure 13-4. Format of LCD Clock Control Register 0; Specify an LCD source clock (f; Set the frame frequency to 128 Hz or lower.; As an example, Table 13-3 lists the frame frequencies used when f
CHAPTER 13 LCD CONTROLLER/DRIVER User’s Manual U15331EJ4V1UD 255 (2) LCD clock control register 0 (LCDC0) LCDC0 specifies the LCD source clock and LCD clock. The frame frequency is determined according to the LCD clock and number of time slices. LCDC0 is set with a 1-bit or 8-bit memory manipulation...
Page 256 - Figure 13-5. Format of LCD Voltage Boost Control Register 0
CHAPTER 13 LCD CONTROLLER/DRIVER 256 User’s Manual U15331EJ4V1UD (3) LCD voltage boost control register 0 (LCDVA0) LCDVA0 controls the voltage boost level during the voltage boost operation. LCDVA0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets LCDVA0 to 00H. Figure 1...
Page 257 - Set the LCD clock using LCD clock control register 0 (LCDC0).; ) after setting VAON0 (refer to CHAPTER 22 ELECTRICAL; LCD Display Data Memory; can be displayed on the LCD panel using the LCD controller/driver.
CHAPTER 13 LCD CONTROLLER/DRIVER User’s Manual U15331EJ4V1UD 257 13.4 Setting LCD Controller/Driver Set the LCD controller/driver using the following procedure. <1> Set the LCD clock using LCD clock control register 0 (LCDC0). <2> Set the voltage boost level using LCD voltage boost contr...
Page 258 - Common and Segment Signals; difference becomes lower than V; problem, this LCD panel is driven with AC voltage.; signals; and segment signals.
CHAPTER 13 LCD CONTROLLER/DRIVER 258 User’s Manual U15331EJ4V1UD 13.6 Common and Segment Signals Each pixel of the LCD panel turns on when the potential difference between the corresponding common and segment signals becomes higher than a specific voltage (LCD drive voltage, V LCD ). It turns off wh...
Page 259 - Figure 13-8. Voltages and Phases of Common and Segment Signals; T: One LCD clock period
CHAPTER 13 LCD CONTROLLER/DRIVER User’s Manual U15331EJ4V1UD 259 Figure 13-7. Common Signal Waveforms COMn (Three-time-slice mode) T F = 3 × T V LC0 V SS V LCD V LC1 V LC2 T F = 4 × T COMn (Four-time-slice mode) V LC0 V LCD V LC1 V LC2 V SS T: One LCD clock period T F : Frame frequency Figure 13-8. ...
Page 260 - generated to turn on the corresponding LCD segment.
CHAPTER 13 LCD CONTROLLER/DRIVER 260 User’s Manual U15331EJ4V1UD 13.7 Display Modes 13.7.1 Three-time-slice display example Figure 13-10 shows how a nine-digit LCD panel having the display pattern shown in Figure 13-9 is connected to the segment signals (S0 to S26) and the common signals (COM0 to CO...
Page 263 - to turn on the corresponding LCD segment.
CHAPTER 13 LCD CONTROLLER/DRIVER User’s Manual U15331EJ4V1UD 263 13.7.2 Four-time-slice display example Figure 13-13 shows how a 14-digit LCD panel having the display pattern shown in Figure 13-12 is connected to the segment signals (S0 to S27) and the common signals (COM0 to COM3) of the µ PD789489...
Page 266 - Supplying LCD Drive Voltages V
CHAPTER 13 LCD CONTROLLER/DRIVER 266 User’s Manual U15331EJ4V1UD 13.8 Supplying LCD Drive Voltages V LC0 , V LC1 , and V LC2 The µ PD789489 Subseries contains a booster circuit ( × 3 only) to generate a supply voltage to drive the LCD. The internal LCD reference voltage is output from the V LC2 pin....
Page 267 - The multiplier has the following function.; Multiplier Configuration
User’s Manual U15331EJ4V1UD 267 CHAPTER 14 MULTIPLIER 14.1 Multiplier Function The multiplier has the following function. • Calculation of 8 bits × 8 bits = 16 bits 14.2 Multiplier Configuration (1) 16-bit multiplication result storage register 0 (MUL0) This register stores the 16-bit result of mult...
Page 268 - CHAPTER 14 MULTIPLIER; Figure 14-1. Block Diagram of Multiplier
CHAPTER 14 MULTIPLIER 268 User’s Manual U15331EJ4V1UD Figure 14-1. Block Diagram of Multiplier Internal bus Selector Counter value 3 CPU clock Start Clear Counter output 16-bit adder 16-bit multiplication result storage register 0 (Master) (MUL0) 16-bit multiplication result storage register 0 (Slav...
Page 269 - Multiplier Control Register; The multiplier is controlled by the following register.; Figure 14-2. Format of Multiplier Control Register 0
CHAPTER 14 MULTIPLIER User’s Manual U15331EJ4V1UD 269 14.3 Multiplier Control Register The multiplier is controlled by the following register. • Multiplier control register 0 (MULC0) (1) Multiplier control register 0 (MULC0) MULC0 indicates the operating status of the multiplier after operation, as ...
Page 270 - Multiplier Operation; The multiplier of the
CHAPTER 14 MULTIPLIER 270 User’s Manual U15331EJ4V1UD 14.4 Multiplier Operation The multiplier of the µ PD789489 Subseries can execute the calculation of 8 bits × 8 bits = 16 bits. Figure 14-3 shows the operation timing of the multiplier where MRA0 is set to AAH and MRB0 is set to D3H. <1> Cou...
Page 271 - Type A reception mode ... Guide pulse (half clock) provided; Remote Controller Receiver Configuration; The remote controller receiver includes the following hardware.; Table 15-1. Remote Controller Receiver Configuration
User’s Manual U15331EJ4V1UD 271 CHAPTER 15 REMOTE CONTROLLER RECEIVER ( µ PD789489, 78F9489 ONLY) 15.1 Remote Controller Receiver Functions The remote controller receiver uses the following remote controller modes. • Type A reception mode … Guide pulse (half clock) provided 15.2 Remote Controller Re...
Page 272 - Figure 15-1. Block Diagram of Remote Controller Receiver; Remote controller stops operation (RMEN
CHAPTER 15 REMOTE CONTROLLER RECEIVER ( µ PD789489, 78F9489 ONLY) User’s Manual U15331EJ4V1UD 272 Figure 15-1. Block Diagram of Remote Controller Receiver RIN/P34 Noise canceler f X /2 6 f X /2 7 f X /2 8 f XT Clock counter Selector Remote controller receive control register ( RMCN) Internal bus RMI...
Page 273 - reading occurs at another timing, the value is not guaranteed.
CHAPTER 15 REMOTE CONTROLLER RECEIVER ( µ PD789489, 78F9489 ONLY) User’s Manual U15331EJ4V1UD 273 (2) Remote controller receive data register (RMDR) This register holds the remote controller reception data. When the remote controller receive shift register (RMSR) overflows, the data in RMSR is trans...
Page 276 - and then change the value.
CHAPTER 15 REMOTE CONTROLLER RECEIVER ( µ PD789489, 78F9489 ONLY) User’s Manual U15331EJ4V1UD 276 (12) Remote controller receive end-width select register (RMER) This register determines the interval between the timing at which the INTREND signal is output. RMER is set with an 8-bit memory manipulat...
Page 277 - Registers to Control Remote Controller Receiver; Remote controller receive control register (RMCN); : Operation clock inside remote controller receiver
CHAPTER 15 REMOTE CONTROLLER RECEIVER ( µ PD789489, 78F9489 ONLY) User’s Manual U15331EJ4V1UD 277 15.3 Registers to Control Remote Controller Receiver The remote controller receiver is controlled by the following register. • Remote controller receive control register (RMCN) (1) Remote controller rec...
Page 278 - controller reception (RMEN; : Oscillation frequency of main system clock; : Oscillation frequency of subsystem clock
CHAPTER 15 REMOTE CONTROLLER RECEIVER ( µ PD789489, 78F9489 ONLY) User’s Manual U15331EJ4V1UD 278 Figure 15-3. Format of Remote Controller Receive Control Register (2/2) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W RMCN RMEN NCW PRSEN RMIN 0 0 RMCK1 RMCK0 FF60H 00H R/W RMCK1 RMCK0 Selection of sou...
Page 279 - Operation of Remote Controller Receiver; Type A reception mode with guide pulse (half clock); Figure 15-4. Example of Type A Data Format
CHAPTER 15 REMOTE CONTROLLER RECEIVER ( µ PD789489, 78F9489 ONLY) User’s Manual U15331EJ4V1UD 279 15.4 Operation of Remote Controller Receiver The following remote controller reception mode is used for this remote controller receiver. • Type A reception mode with guide pulse (half clock) 15.4.1 Form...
Page 280 - Figure 15-5. Operation Flow of Type A Reception Mode; Read RMDR before data has been set to all the bits of RMSR.
CHAPTER 15 REMOTE CONTROLLER RECEIVER ( µ PD789489, 78F9489 ONLY) User’s Manual U15331EJ4V1UD 280 Figure 15-5. Operation Flow of Type A Reception Mode Note Read RMDR before data has been set to all the bits of RMSR. Longer than END interval? No Yes Start Yes No Generate INTGP Set data to all bits of...
Page 281 - (1) Guide pulse high level width determination
CHAPTER 15 REMOTE CONTROLLER RECEIVER ( µ PD789489, 78F9489 ONLY) User’s Manual U15331EJ4V1UD 281 15.4.3 Timing Operation varies depending on the positions of the RIN input waveform below. (1) Guide pulse high level width determination Relationship Between RMGPHS/RMGPHL/Counter Position of Waveform ...
Page 282 - (3) Data high level width determination
CHAPTER 15 REMOTE CONTROLLER RECEIVER ( µ PD789489, 78F9489 ONLY) User’s Manual U15331EJ4V1UD 282 (3) Data high level width determination Relationship Between RMDH0S/RMDH0L/RMDH1S/RMDH1L/Counter Position of Waveform Corresponding Operation Counter < RMDH0S <1>: Short Error interrupt INTRERR...
Page 285 - Error interrupt generation timing
CHAPTER 15 REMOTE CONTROLLER RECEIVER ( µ PD789489, 78F9489 ONLY) User’s Manual U15331EJ4V1UD 285 15.4.5 Error interrupt generation timing After the guide pulse has been detected normally, the INTRERR signal is generated under any of the following conditions. • Counter < RMDLS at the rising edge ...
Page 286 - Figure 15-7. Generation Timing of INTRERR Signal
CHAPTER 15 REMOTE CONTROLLER RECEIVER ( µ PD789489, 78F9489 ONLY) User’s Manual U15331EJ4V1UD 286 Figure 15-7. Generation Timing of INTRERR Signal RIN INTRERR RIN INTRERR RIN INTRERR RIN INTRERR RIN INTRERR RIN INTRERR RIN INTRERR INTREND RIN INTRERR RIN INTRERR Example 1Counter < RMGPHS → INTRER...
Page 290 - Interrupt Sources and Configuration
290 User’s Manual U15331EJ4V1UD CHAPTER 16 INTERRUPT FUNCTIONS 16.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally. It does not undergo interrupt priority control and is given top priority ov...
Page 291 - time. 0 is the highest priority and 15 is the lowest.
CHAPTER 16 INTERRUPT FUNCTIONS User’s Manual U15331EJ4V1UD 291 Table 16-1. Interrupt Sources ( µ PD789488, 78F9488) Interrupt Source Interrupt Type Priority Note 1 Name Trigger Internal/ External Vector Table Address Basic Configuration Type Note 2 Non-maskable − INTWDT Watchdog timer overflow (with...
Page 292 - CHAPTER 16 INTERRUPT FUNCTIONS; time. 0 is the highest priority and 21 is the lowest.
CHAPTER 16 INTERRUPT FUNCTIONS 292 User’s Manual U15331EJ4V1UD Table 16-2. Interrupt Sources ( µ PD789489, 78F9489) Interrupt Source Interrupt Type Priority Note 1 Name Trigger Internal/ External Vector Table Address Basic Configuration Type Note 2 Non-maskable − INTWDT Watchdog timer overflow (with...
Page 293 - Figure 16-1. Basic Configuration of Interrupt Function; External interrupt mode register 0
CHAPTER 16 INTERRUPT FUNCTIONS User’s Manual U15331EJ4V1UD 293 Figure 16-1. Basic Configuration of Interrupt Function (A) Internal non-maskable interrupt Internal bus Interrupt request Vector tableaddress generator Standby release signal (B) Internal maskable interrupt MK IF IE Internal bus Interrup...
Page 294 - Registers Controlling Interrupt Function; Interrupt request flag registers (IF0 to IF2); Table 16-3. Flags Corresponding to Interrupt Request Signal Names
CHAPTER 16 INTERRUPT FUNCTIONS 294 User’s Manual U15331EJ4V1UD 16.3 Registers Controlling Interrupt Function The following five types of registers are used to control the interrupt functions. • Interrupt request flag registers (IF0 to IF2) • Interrupt mask flag registers (MK0 to MK2) • External inte...
Page 295 - Figure 16-2. Format of Interrupt Request Flag Registers
CHAPTER 16 INTERRUPT FUNCTIONS User’s Manual U15331EJ4V1UD 295 (1) Interrupt request flag registers (IF0 to IF2) An interrupt request flag is set (1) when the corresponding interrupt request is generated, or when an instruction is executed. It is cleared (0) when the interrupt request is acknowledge...
Page 296 - Figure 16-3. Format of Interrupt Mask Flag Registers
CHAPTER 16 INTERRUPT FUNCTIONS 296 User’s Manual U15331EJ4V1UD (2) Interrupt mask flag registers (MK0 to MK2) Interrupt mask flags are used to enable and disable the corresponding maskable interrupts. MK0 to MK2 are set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets these re...
Page 297 - Figure 16-4. Format of External Interrupt Mode Registers
CHAPTER 16 INTERRUPT FUNCTIONS User’s Manual U15331EJ4V1UD 297 (3) External interrupt mode registers (INTM0, INTM1) These registers are used to specify the valid edge for INTP0 to INTP3. INTM0 and INTM1 are set with an 8-bit memory manipulation instruction. RESET input sets these registers to 00H. F...
Page 298 - Figure 16-5. Program Status Word Configuration
CHAPTER 16 INTERRUPT FUNCTIONS 298 User’s Manual U15331EJ4V1UD (4) Program status word (PSW) The program status word is used to hold the instruction execution results and the current status of the interrupt requests. The IE flag, used to enable and disable maskable interrupts, is mapped to the PSW. ...
Page 299 - Figure 16-6. Format of Key Return Mode Register 00; For selecting the pin to be used as falling edge input.
CHAPTER 16 INTERRUPT FUNCTIONS User’s Manual U15331EJ4V1UD 299 (5) Key return mode register 00 (KRM00) This register is used to set the pin that is to detect the key return signal (rising edge of port 0). KRM00 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this regis...
Page 300 - Figure 16-8. Format of Key Return Mode Register 01; For selecting the pin to be used as falling edge input
CHAPTER 16 INTERRUPT FUNCTIONS 300 User’s Manual U15331EJ4V1UD (6) Key return mode register 01 (KRM01) ( µ PD789489, 78F9489 only) This register is used to set the pin that is to detect the key return signal (falling edge of port 6). KRM01 is set with a 1-bit or 8-bit memory manipulation instruction...
Page 301 - Interrupt Servicing Operation; Non-maskable interrupt request acknowledgment operation
CHAPTER 16 INTERRUPT FUNCTIONS User’s Manual U15331EJ4V1UD 301 16.4 Interrupt Servicing Operation 16.4.1 Non-maskable interrupt request acknowledgment operation The non-maskable interrupt request is unconditionally acknowledged even when interrupts are disabled. It is not subject to interrupt priori...
Page 302 - Figure 16-12. Non-Maskable Interrupt Request Acknowledgment
CHAPTER 16 INTERRUPT FUNCTIONS 302 User’s Manual U15331EJ4V1UD Figure 16-10. Flow from Generation of Non-Maskable Interrupt Request to Acknowledgment Start WDTM4 = 1 (watchdog timer mode is selected) Interval timer No WDT overflows No Yes Reset processing No Yes Yes Interrupt request is generated In...
Page 303 - Maskable interrupt request acknowledgment operation; the BT or BF instruction.
CHAPTER 16 INTERRUPT FUNCTIONS User’s Manual U15331EJ4V1UD 303 16.4.2 Maskable interrupt request acknowledgment operation A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. A vectored interrupt is ac...
Page 304 - Figure 16-15. Interrupt Request Acknowledgment Timing
CHAPTER 16 INTERRUPT FUNCTIONS 304 User’s Manual U15331EJ4V1UD Figure 16-14. Interrupt Request Acknowledgment Timing (Example: MOV A, r) Clock CPU MOV A, r Saving PSW and PC, andjump to interrupt servicing 8 clocks Interrupt servicing program Interrupt If the interrupt request has generated an inter...
Page 305 - Figure 16-16. Example of Multiple Interrupt Servicing
CHAPTER 16 INTERRUPT FUNCTIONS User’s Manual U15331EJ4V1UD 305 Figure 16-16. Example of Multiple Interrupt Servicing Example 1. Acknowledging multiple interrupts INTyy EI Main servicing EI INTyy servicing INTxx servicing RETI IE = 0 INTxx RETI IE = 0 The interrupt request INTyy is acknowledged durin...
Page 306 - Putting interrupt requests on hold
CHAPTER 16 INTERRUPT FUNCTIONS 306 User’s Manual U15331EJ4V1UD 16.4.4 Putting interrupt requests on hold If an interrupt request (such as a maskable, non-maskable, or external interrupt) is generated when a certain type of instruction is being executed, the interrupt request will not be acknowledged...
Page 307 - execute the STOP instruction.
User’s Manual U15331EJ4V1UD 307 CHAPTER 17 STANDBY FUNCTION 17.1 Standby Function and Configuration 17.1.1 Standby function The standby function is used to reduce the power consumption of the system and can be effected in the following two modes. (1) HALT mode This mode is set when the HALT instruct...
Page 308 - CHAPTER 17 STANDBY FUNCTION; Register controlling standby function; , to stabilize oscillation after RESET input.
CHAPTER 17 STANDBY FUNCTION 308 User’s Manual U15331EJ4V1UD 17.1.2 Register controlling standby function The wait time after the STOP mode is released upon interrupt request generation until oscillation stabilizes is controlled by the oscillation stabilization time selection register (OSTS). OSTS is...
Page 309 - Standby Function Operation; Operation is enabled when the 24-bit counter mode is selected.
CHAPTER 17 STANDBY FUNCTION User’s Manual U15331EJ4V1UD 309 17.2 Standby Function Operation 17.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. The operation statuses in the HALT mode are shown in the following table. Table 17-1. Operation Statuses in HALT Mode HAL...
Page 310 - The HALT mode can be released by the following three sources.; (a) Release by unmasked interrupt request; The wait time is as follows:
CHAPTER 17 STANDBY FUNCTION 310 User’s Manual U15331EJ4V1UD (2) Releasing HALT mode The HALT mode can be released by the following three sources. (a) Release by unmasked interrupt request The HALT mode is released by an unmasked interrupt request. In this case, if interrupts are enabled to be acknow...
Page 311 - Figure 17-3. Releasing HALT Mode by RESET Input; Table 17-2. Operation After Releasing HALT Mode
CHAPTER 17 STANDBY FUNCTION User’s Manual U15331EJ4V1UD 311 (c) Release by RESET input When the HALT mode is released by the RESET signal, execution branches to the reset vector address in the same manner as the ordinary reset operation, and program execution is started. Figure 17-3. Releasing HALT ...
Page 312 - (1) Setting and operation status of STOP mode; The STOP mode is set by executing the STOP instruction.; Table 17-3. Operation Statuses in STOP Mode; 0 is operable) is selected as the count clock.
CHAPTER 17 STANDBY FUNCTION 312 User’s Manual U15331EJ4V1UD 17.2.2 STOP mode (1) Setting and operation status of STOP mode The STOP mode is set by executing the STOP instruction. Caution Because the standby mode can be released by an interrupt request signal, the standby mode is released as soon as ...
Page 313 - The STOP mode can be released by the following two sources.
CHAPTER 17 STANDBY FUNCTION User’s Manual U15331EJ4V1UD 313 (2) Releasing STOP mode The STOP mode can be released by the following two sources. (a) Release by unmasked interrupt request The STOP mode can be released by an unmasked interrupt request. In this case, if interrupts are enabled to be ackn...
Page 314 - Figure 17-5. Releasing STOP Mode by RESET Input; Table 17-4. Operation After Releasing STOP Mode
CHAPTER 17 STANDBY FUNCTION 314 User’s Manual U15331EJ4V1UD (b) Release by RESET input When the STOP mode is released by the RESET signal, the reset operation is performed after the oscillation stabilization time has elapsed. Figure 17-5. Releasing STOP Mode by RESET Input STOP instruction RESET sig...
Page 315 - CHAPTER 18 RESET FUNCTION; oscillation stabilization time (2; Cautions 1. For an external reset, input a low level for 10
User’s Manual U15331EJ4V1UD 315 CHAPTER 18 RESET FUNCTION The following two operations are available to generate reset signals. (1) External reset input by RESET pin (2) Internal reset by watchdog timer program loop time detection External and internal reset have no functional differences. In both c...
Page 316 - Figure 18-2. Reset Timing by RESET Input
CHAPTER 18 RESET FUNCTION 316 User’s Manual U15331EJ4V1UD Figure 18-2. Reset Timing by RESET Input X1 RESET Internal reset signal Port pin During normaloperation Delay Delay Hi-Z Reset period(oscillation stops) Normal operation(reset processing) Oscillationstabilizationtime wait Figure 18-3. Reset T...
Page 317 - In standby mode, RAM enters the hold state after reset.
CHAPTER 18 RESET FUNCTION User’s Manual U15331EJ4V1UD 317 Table 18-1. Status of Hardware After Reset (1/2) Hardware Status After Reset Program counter (PC) Note 1 Contents of reset vector table (0000H, 0001H) set Stack pointer (SP) Undefined Program status word (PSW) 02H Data memory Undefined Note 2...
Page 319 - CHAPTER 19 FLASH MEMORY VERSION; CHAPTER 22 ELECTRICAL SPECIFICATIONS (
User’s Manual U15331EJ4V1UD 319 CHAPTER 19 FLASH MEMORY VERSION The µ PD78F9488 is available as the flash memory version of the µ PD789488 (mask ROM version). The µ PD78F9489 is available as the flash memory version of the µ PD789489 (mask ROM version). The differences between the µ PD78F9488, 78F94...
Page 320 - Flash Memory Characteristics; Easy data adjustment when starting mass production; USB is supported by Flashpro IV only.; Figure 19-1. Environment for Writing Program to Flash Memory
CHAPTER 19 FLASH MEMORY VERSION 320 User’s Manual U15331EJ4V1UD 19.1 Flash Memory Characteristics Flash memory programming is performed by connecting a dedicated flash programmer (Flashpro III (part no. FL- PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)) to the target system with the µ PD78F9488...
Page 321 - programmer and; ELECTRICAL SPECIFICATIONS (; Only 2 MHz or 4 MHz can be selected for Flashpro III.; Figure 19-2. Communication Mode Selection Format
CHAPTER 19 FLASH MEMORY VERSION User’s Manual U15331EJ4V1UD 321 19.1.2 Communication mode Use the communication mode shown in Table 19-2 to perform communication between the dedicated flash programmer and µ PD78F9488 or 78F9489. Table 19-2. Communication Mode List TYPE Setting Note 1 CPU Clock Commu...
Page 322 - not connect the CLK pin.; Caution The; voltage before starting programming.
CHAPTER 19 FLASH MEMORY VERSION 322 User’s Manual U15331EJ4V1UD Figure 19-3. Example of Connection with Dedicated Flash Programmer (a) 3-wire serial I/O Dedicated flash programmer VPP1 VDD RESET SCK SO SI CLK Note 1 GND V PP V DD RESET SCK20 SI20 SO20 X1 V SS PD78F9488 PD78F9489 µ µ (b) 3-wire seria...
Page 323 - Pin Connection List; voltage must be supplied before programming is started.
CHAPTER 19 FLASH MEMORY VERSION User’s Manual U15331EJ4V1UD 323 If Flashpro III/Flashpro IV is used as a dedicated flash programmer, the following signals are generated for the µ PD78F9488 and 78F9489. For details, refer to the manual of Flashpro III/Flashpro IV. Table 19-3. Pin Connection List Sign...
Page 324 - Pin Connection Example
CHAPTER 19 FLASH MEMORY VERSION 324 User’s Manual U15331EJ4V1UD 19.1.3 On-board pin processing When performing programming on the target system, provide a connector on the target system to connect the dedicated flash programmer. An on-board function that allows switching between normal operation mod...
Page 325 - conflict
CHAPTER 19 FLASH MEMORY VERSION User’s Manual U15331EJ4V1UD 325 (1) Signal conflict If the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a signal conflict occurs. To prevent this, isolate the connection with the other...
Page 326 - or V
CHAPTER 19 FLASH MEMORY VERSION 326 User’s Manual U15331EJ4V1UD <RESET pin> If the reset signal of the dedicated flash programmer is connected to the RESET pin connected to the reset signal generator on-board, a signal conflict occurs. To prevent this, isolate the connection with the reset sig...
Page 327 - Connection of adapter for flash writing
CHAPTER 19 FLASH MEMORY VERSION User’s Manual U15331EJ4V1UD 327 19.1.4 Connection of adapter for flash writing The following figure shows an example of recommended connection when the adapter for flash writing is used. Figure 19-8. Wiring Example for Flash Writing Adapter with 3-Wire Serial I/O GND ...
Page 329 - Figure 19-10. Wiring Example for Flash Writing Adapter with UART
CHAPTER 19 FLASH MEMORY VERSION User’s Manual U15331EJ4V1UD 329 Figure 19-10. Wiring Example for Flash Writing Adapter with UART GND VDD SI SO SCK CLKOUT RESET VPP RESERVE/HS WRITER INTERFACE VDD (2.7 to 5.5 V) GND 123456789 1011121314151617181920 6059585756555453525150494847464544434241 80 79 78 77...
Page 330 - (1) When using HALT mode with subclock multiplied by four; Observe the following constraints when using the flash version (
CHAPTER 19 FLASH MEMORY VERSION 330 User’s Manual U15331EJ4V1UD 19.2 Cautions on µ PD78F9488 and 78F9489 (1) When using HALT mode with subclock multiplied by four Observe the following constraints when using the flash version ( µ PD78F9488 and 78F9489) in the HALT mode with the subclock multiplied b...
Page 331 - CHAPTER 20 MASK OPTIONS; Caution The flash memory products (
User’s Manual U15331EJ4V1UD 331 CHAPTER 20 MASK OPTIONS The µ PD789488 and 789489 have the following mask options. • Pin function The segment pins of the LCD and port 7 (input port) can be selected in 1-bit units. <1> S (16 + n) <2> P7n (n = 0 to 3) The segment pins of the LCD and port 8...
Page 332 - CHAPTER 21 INSTRUCTION SET; This chapter lists the instruction set of the; Operand identifiers and description methods; Absolute address specification; Table 21-1. Operand Identifiers and Description Methods; Table 3-4 Special Function Registers; for symbols of special function registers.
332 User’s Manual U15331EJ4V1UD CHAPTER 21 INSTRUCTION SET This chapter lists the instruction set of the µ PD789489 Subseries. For details of the operation and machine language (instruction code) of each instruction, refer to 78K/0S Series Instructions User’s Manual (U11047E) . 21.1 Operation 21.1.1...
Page 333 - Description of “Operation” column
CHAPTER 21 INSTRUCTION SET User’s Manual U15331EJ4V1UD 333 21.1.2 Description of “Operation” column A: A register; 8-bit accumulator X: X register B: B register C: C register D: D register E: E register H: H register L: L register AX: AX register pair; 16-bit accumulator BC: BC register pair DE: DE ...
Page 334 - Operation List; One instruction clock cycle is one CPU clock cycle (f; ) selected by the processor clock control
CHAPTER 21 INSTRUCTION SET 334 User’s Manual U15331EJ4V1UD 21.2 Operation List Mnemonic Operands Bytes Clocks Operation Flag Z AC CY MOV r, #byte 3 6 r ← byte saddr, #byte 3 6 (saddr) ← byte sfr, #byte 3 6 sfr ← byte A, r Note 1 2 4 A ← r r, A Note 1 2 4 r ← A A, saddr 2 4 A ← (saddr) saddr, A 2 4 (...
Page 339 - Instructions Listed by Addressing Type; instructions
CHAPTER 21 INSTRUCTION SET User’s Manual U15331EJ4V1UD 339 21.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH, POP, DBNZ 2nd Operand 1st Operand #byte A r sfr saddr !addr16 PSW [DE] [HL] [HL+byte]...
Page 342 - Absolute Maximum Ratings (T; When supply voltage rises
342 User’s Manual U15331EJ4V1UD CHAPTER 22 ELECTRICAL SPECIFICATIONS ( µ PD789488, 78F9488, 789489, 78F9489) Absolute Maximum Ratings (T A = 25 ° C) Parameter Symbol Conditions Ratings Unit V DD Power supply voltage AV DD V DD = AV DD − 0.3 to +6.5 V V PP µ PD78F9488, 78F9489 only, Note 1 − 0.3 to +...
Page 344 - Indicates only oscillator characteristics. Refer to
CHAPTER 22 ELECTRICAL SPECIFICATIONS ( µ PD789488, 78F9488, 789489, 78F9489) 344 User’s Manual U15331EJ4V1UD Main System Clock Oscillator Characteristics (T A = –40 to +85 ° C, V DD = 1.8 to 5.5 V) Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit Oscillation frequency (f X ) No...
Page 345 - reaches oscillation voltage range MIN.
CHAPTER 22 ELECTRICAL SPECIFICATIONS ( µ PD789488, 78F9488, 789489, 78F9489) User’s Manual U15331EJ4V1UD 345 Subsystem Clock Oscillator Characteristics (T A = –40 to +85 ° C, V DD = 1.8 to 5.5 V) Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit Oscillation frequency (f XT ) Not...
Page 346 - DC Characteristics (T; Only when selected by a mask option or port function register
CHAPTER 22 ELECTRICAL SPECIFICATIONS ( µ PD789488, 78F9488, 789489, 78F9489) 346 User’s Manual U15331EJ4V1UD DC Characteristics (T A = –40 to +85 ° C, V DD = 1.8 to 5.5 V) (1/6) Parameter Symbol Conditions MIN. TYP. MAX. Unit Per pin 10 mA Output current, low I OL All pins 80 mA Per pin –1 mA Output...
Page 348 - When the main system clock is stopped; and AV
CHAPTER 22 ELECTRICAL SPECIFICATIONS ( µ PD789488, 78F9488, 789489, 78F9489) 348 User’s Manual U15331EJ4V1UD DC Characteristics (T A = –40 to +85 ° C, V DD = 1.8 to 5.5 V) (3/6) Parameter Symbol Conditions MIN. TYP. MAX. Unit V DD = 5.0 V ± 10% Note 2 2 3.5 mA V DD = 3.0 V ± 10% Note 3 0.4 1 mA I DD...
Page 352 - AC Characteristics
CHAPTER 22 ELECTRICAL SPECIFICATIONS ( µ PD789488, 78F9488, 789489, 78F9489) 352 User’s Manual U15331EJ4V1UD AC Characteristics (1) Basic operation (T A = –40 to +85 ° C, V DD = 1.8 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit V DD = 2.7 to 5.5 V 0.4 8.0 µ s Operating with main system c...
Page 356 - AC Timing Measurement Points (Excluding X1 and XT1 Inputs); INTP0 to INTP3
CHAPTER 22 ELECTRICAL SPECIFICATIONS ( µ PD789488, 78F9488, 789489, 78F9489) 356 User’s Manual U15331EJ4V1UD AC Timing Measurement Points (Excluding X1 and XT1 Inputs) 0.8V DD 0.2V DD Point of measurement 0.8V DD 0.2V DD Clock Timing 1/f X t XL t XH X1 input V IH4 (MIN.) V IL4 (MAX.) 1/f XT t XTL t ...
Page 357 - RESET Input Timing
CHAPTER 22 ELECTRICAL SPECIFICATIONS ( µ PD789488, 78F9488, 789489, 78F9489) User’s Manual U15331EJ4V1UD 357 Key Return Input Timing t KRL KR0 to KR7 ( PD789488, 78F9488) , KR00 to KR07, KR10 to KR17 ( PD789489, 78F9489) µ µ RESET Input Timing RESET t RSL Serial Transfer Timing 3-wire serial I/O mod...
Page 358 - Excludes quantization error (; FSR: Full scale range
CHAPTER 22 ELECTRICAL SPECIFICATIONS ( µ PD789488, 78F9488, 789489, 78F9489) 358 User’s Manual U15331EJ4V1UD 10-Bit A/D Converter Characteristics (T A = –40 to +85 ° C, 1.8 V ≤ AV DD = V DD ≤ 5.5 V, AV SS = V SS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution 10 10 10 bit 4.5 V ≤ A...
Page 359 - LCD Characteristics (T
CHAPTER 22 ELECTRICAL SPECIFICATIONS ( µ PD789488, 78F9488, 789489, 78F9489) User’s Manual U15331EJ4V1UD 359 LCD Characteristics (T A = –40 to +85 ° C, V DD = 1.8 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit GAIN = 1 0.84 1.0 1.165 V LCD output voltage variation range V LCD2 C1 to C4 No...
Page 360 - Data Retention Timing (STOP Mode Release by RESET); Oscillation Stabilization Wait Time (T; Selection of 2
CHAPTER 22 ELECTRICAL SPECIFICATIONS ( µ PD789488, 78F9488, 789489, 78F9489) 360 User’s Manual U15331EJ4V1UD Data Retention Timing (STOP Mode Release by RESET) V DD Data retention mode STOP mode HALT mode Internal reset operation Operation mode t SREL t WAIT STOP instruction execution V DDDR RESET D...
Page 361 - Flash Memory Writing and Erasing Characteristics (T
CHAPTER 22 ELECTRICAL SPECIFICATIONS ( µ PD789488, 78F9488, 789489, 78F9489) User’s Manual U15331EJ4V1UD 361 Flash Memory Writing and Erasing Characteristics (T A = 10 to 40 ° C, V DD = 1.8 to 5.5 V) ( µ PD78F9488, 78F9489 only) Parameter Symbol Conditions MIN. TYP. MAX. Unit Write/erase operating f...
Page 362 - CHAPTER 23 CHARACTERISTICS CURVES OF LCD CONTROLLER/DRIVER; LCD output voltage/Voltage boosting time
362 User’s Manual U15331EJ4V1UD CHAPTER 23 CHARACTERISTICS CURVES OF LCD CONTROLLER/DRIVER (REFERENCE VALUES) (1) Characteristics curves of voltage boosting stabilization time The following shows the characteristics curves of the time from the start of voltage boosting (VAON0 = 1) and the changes in...
Page 363 - (2) Temperature characteristics of LCD output voltage
CHAPTER 23 CHARACTERISTICS CURVES OF LCD CONTROLLER/DRIVER (REFERENCE VALUES) User’s Manual U15331EJ4V1UD 363 (2) Temperature characteristics of LCD output voltage The following shows the temperature characteristics curves of LCD output voltage. LCD output voltage [V] V LCD2 V LCD1 V LCD0 V LCD2 V L...
Page 364 - CHAPTER 24 PACKAGE DRAWINGS; N O T E; detail of lead end
364 User’s Manual U15331EJ4V1UD CHAPTER 24 PACKAGE DRAWINGS 80-PIN PLASTIC QFP (14x14) N O T E Each lead centerline is located within 0.13 mm ofits true position (T.P.) at maximum material condition. I T E M M I L L I M E T E R S A B D G 1 7 . 2 0 ± 0 . 2 0 1 4 . 0 0 ± 0 . 2 0 0 . 1 3 0 . 8 2 5 I 1 ...
Page 366 - CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS; After opening the dry peak, store it at 25
366 User’s Manual U15331EJ4V1UD CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS The µ PD789489 subseries should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. Fo...
Page 368 - After opening the dry pack, store it at 25
CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS 368 User’s Manual U15331EJ4V1UD Table 25-1. Surface Mounting Type Soldering Conditions (3/3) (5) µ PD789488GC- ××× -8BT-A: 80-pin plastic QFP (14x14) µ PD78F9488GC-8BT-A: 80-pin plastic QFP (14x14) µ PD789489GC- ××× -8BT-A: 80-pin plastic QFP (14x14) µ PD7...
Page 369 - APPENDIX A DEVELOPMENT TOOLS; Support for PC98-NX Series
369 User’s Manual U15331EJ4V1UD APPENDIX A DEVELOPMENT TOOLS The following development tools are available for development of systems using the µ PD789489 Subseries. Figure A-1 shows development tools. • Support for PC98-NX Series Unless specified otherwise, the products supported by IBM PC/AT™ comp...
Page 370 - C library source file is not included in the software package.
APPENDIX A DEVELOPMENT TOOLS User’s Manual U15331EJ4V1UD 370 Figure A-1. Development Tools Language processing software · Assembler package · C compiler package · Device file · C library source file Note 1 Debugging software · Integrated debugger · System simulator Host machine (PC or EWS) Interface...
Page 371 - A.1 Software Package; Software package
APPENDIX A DEVELOPMENT TOOLS User’s Manual U15331EJ4V1UD 371 A.1 Software Package Software tools for development of the 78K/0S Series are combined in this package. The following tools are included. RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S, and device files SP78K0S Software package Part number: µ S ××××...
Page 372 - A.3 Control Software
APPENDIX A DEVELOPMENT TOOLS 372 User’s Manual U15331EJ4V1UD Remark ×××× in the part number differs depending on the host machine and operating system to be used. µ S ×××× RA78K0S µ S ×××× CC78K0S ×××× Host Machine OS Supply Medium AB13 Japanese Windows 3.5" 2HD FD BB13 English Windows AB17 Japa...
Page 375 - APPENDIX B NOTES ON TARGET SYSTEM DESIGN; Table B-1. Distance Between IE System and Conversion Adapter; Target system
User’s Manual U15331EJ4V1UD 375 APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figures B-1 to B-6 show the conditions when connecting the emulation probe to the conversion adapter or conversion socket. Follow the configuration below and consider the shape of parts to be mounted on the target system when d...
Page 376 - APPENDIX B NOTES ON TARGET SYSTEM DESIGN
APPENDIX B NOTES ON TARGET SYSTEM DESIGN User’s Manual U15331EJ4V1UD 376 Figure B-2. Connection Conditions of Target System (When NP-80GC-TQ Is Used) Emulation probeNP-80GC-TQ Emulation boardIE-789488-NS-EM1 24.8 mm 25 mm 40 mm 34 mm Target system 21 mm Pin 1 11 mm 21 mm Conversion adapter TGC-080SB...
Page 379 - APPENDIX C REGISTER INDEX
379 User’s Manual U15331EJ4V1UD APPENDIX C REGISTER INDEX C.1 Register Index (Register Names in Alphabetic Order) [A] A/D conversion result register 0 (ADCRL0) .......................................................................................................... 174 A/D converter mode register 0...
Page 385 - APPENDIX D REVISION HISTORY
User’s Manual U15331EJ4V1UD 385 APPENDIX D REVISION HISTORY The following table shows the revision history up to this edition. The “Applied to:” column indicates the chapters of each edition in which the revision was applied. (1/4) Edition Major Revision from Previous Edition Applied to: Correction ...
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