NEC PD78058F - Manuals

7 PREFACE Readers This manual has been prepared for user engineers who want to understand the functions of the µ PD78058F and 78058FY Subseries and design and develop its application systems and programs. Affected versions are each of the versions in the following Subseries. µ PD78058F Subseries : µ...

9 Chapter Organization This manual divides the descriptions for the µ PD78058F and 78058FY Subseries into different chapters as shown below. Read only the chapters related to the device you use. Chapter µ PD78058F Subseries µ PD78058FY Subseries Chapter 1 Outline ( µ PD78058F Subseries) √ — Chapter ...

11 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Related Documents for µ PD78058F Subseries Document Name Document No. Japanese English µ PD78056F, 78058F Data Sheet U11795J U11795E µ PD78...

16 3.2.14 AV SS .............................................................................................................................................. 71 3.2.15 RESET ................................................................................................................................

18 7.4.2 Subsystem clock oscillator ........................................................................................................... 162 7.4.3 Scaler ..............................................................................................................................................

19 CHAPTER 11 WATCHDOG TIMER ...................................................................................................... 245 11.1 Watchdog Timer Functions ................................................................................................ 245 11.2 Watchdog Timer Configuration...

20 16.4.3 SBI mode operation ................................................................................................................. 305 16.4.4 2-wire serial I/O mode operation ............................................................................................. 331 16.4.5 SCK0/P27...

22 26.3.3 PROM read procedure ............................................................................................................ 546 26.4 Screening of One-Time PROM Versions ........................................................................... 547 CHAPTER 27 INSTRUCTION SET ............

35 CHAPTER 1 OUTLINE ( µ PD78058F SUBSERIES) 1.1 Features Compared to the conventional µ PD78054 Subseries, EMI (Electro Magnetic Interference) noise has been reduced. On-chip high-capacity ROM and RAM Program Memory (ROM) Part Number Item µ PD78056F µ PD78058F µ PD78P058F 48 Kbytes 60 Kbytes 60 Kby...

36 CHAPTER 1 OUTLINE ( µ PD78058F SUBSERIES) 1.2 Applications In the case of the µ PD78056F, 78058F and 78P058F, Cellular phones, pagers, printers, AV equipment, air conditioners, cameras, PPC’s, fuzzy home appliances, vending machines, etc. In the case of the µ PD78058F (A), Controllers for car ele...

38 CHAPTER 1 OUTLINE ( µ PD78058F SUBSERIES) 1.5 Pin Configuration (Top View) (1) Normal operating mode 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) µ PD78056FGC- ××× -3B9, 78058FGC- ××× -3B9, 78058FGC(A)- ××× -3B9, 78P058FGC-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) µ...

39 CHAPTER 1 OUTLINE ( µ PD78058F SUBSERIES) Pin Identifications A8 to A15 : Address Bus AD0 to AD7 : Address/Data Bus ANI0 to ANI7 : Analog Input ANO0, ANO1 : Analog Output ASCK : Asynchronous Serial Clock ASTB : Address Strobe AV DD : Analog Power Supply AV REF0, 1 : Analog Reference Voltage AV SS...

40 CHAPTER 1 OUTLINE ( µ PD78058F SUBSERIES) (2) PROM programming mode 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) µ PD78P058FGC-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) µ PD78P058FGC-8BT Cautions 1. (L) : Connect independently to V SS via a pull-down resistor. 2. V ...

41 CHAPTER 1 OUTLINE ( µ PD78058F SUBSERIES) 1.6 78K/0 Series Expansion The 78K/0 Series expansion is shown below. The names in frames are subseries. Note Under planning PD780964 PD78098 80-pin IEBus controller was added to the PD78054 PD78044F 80-pin Basic subseries for driving FIP. Display output ...

43 CHAPTER 1 OUTLINE ( µ PD78058F SUBSERIES) 1.7 Block Diagram Remarks 1. The internal ROM and RAM capacities depend on the product. 2. Pin connection in parentheses is intended for the µ PD78P058F. 16-bit TIMER/EVENT COUNTER 8-bit TIMER/EVENT COUNTER 1 WATCHDOG TIMER WATCH TIMER SERIALINTERFACE 0 S...

44 CHAPTER 1 OUTLINE ( µ PD78058F SUBSERIES) 1.8 Outline of Function ROM Mask ROM PROM 48 Kbytes 60 Kbytes 60 Kbytes Note 1 High-speed RAM 1024 bytes 1024 bytes Note 1 Buffer RAM 32 bytes Expansion RAM None 1024 bytes 1024 bytes Note 2 Memory space 64 Kbytes General register 8 bits × 8 × 4 banks Wit...

45 CHAPTER 1 OUTLINE ( µ PD78058F SUBSERIES) Buzzer output 1.2 kHz, 2.4 kHz, 4.9 KHz, 9.8 kHz (main system clock at 5.0-MHz operation) Vectored Maskable Internal: 13 interrupt External: 7 sources Non-maskable Internal: 1 Software 1 Test input Internal: 1 External: 1 Supply voltage V DD = 2.7 to 6.0 ...

46 CHAPTER 1 OUTLINE ( µ PD78058F SUBSERIES) 1.10 Mask Options There are mask options in the mask ROM versions ( µ PD78056F, 78058F). By specifying the mask option when ordering, you can have the pull-up resistors shown in Table 1-2 incorporated on-chip. If a mask option is used when pull-up resisto...

48 CHAPTER 2 OUTLINE ( µ PD78058FY SUBSERIES) 2.2 Applications In the case of the µ PD78056FY, 78058FY and 78P058FY, Cellular phones, pagers, printers, AV equipment, air conditioners, cameras, PPCs, fuzzy home appliances, vending machines, etc. In the case of the µ PD78058FY (A), Controllers for car...

50 CHAPTER 2 OUTLINE ( µ PD78058FY SUBSERIES) 2.5 Pin Configuration (Top View) (1) Normal operating mode 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) µ PD78056FYGC- ××× -3B9, 78058FYGC- ××× -3B9, 78058FYGC(A)- ××× -3B9, µ PD78P058FYGC-3B9 80-pin plastic QFP (14 × 14 mm, Resin thickness: ...

56 CHAPTER 2 OUTLINE ( µ PD78058FY SUBSERIES) 2.8 Outline of Function ROM Mask ROM PROM 48 Kbytes 60 Kbytes 60 Kbytes Note 1 High-speed RAM 1024 bytes 1024 bytes Note 1 Buffer RAM 32 bytes Expansion RAM None 1024 bytes 1024 bytes Note 2 Memory space 64 Kbytes General register 8 bits × 8 × 4 banks Wi...

57 CHAPTER 2 OUTLINE ( µ PD78058FY SUBSERIES) Vectored Maskable Internal: 13 interrupt External: 7 sources Non-maskable Internal: 1 Software 1 Test input Internal: 1 External: 1 Supply voltage V DD = 2.7 to 6.0 V Operating ambient temperature T A = –40 to +85 ° C Package • 80-pin plastic QFP (14 × 1...

58 CHAPTER 2 OUTLINE ( µ PD78058FY SUBSERIES) 2.10 Mask Options The mask ROM versions ( µ PD78056FY, 78058FY) provide pull-up resistor mask options which allow users to specify whether to connect a pull-up resistor to a specific port pin when the user places an order for the device production. Using...

59 Pin Name Input/Output Function After Reset Alternate Function P00 Input Port 0. Input only Input INTP0/TI00 P01 Input/ 8-bit input/output port. Input/output mode can be specified Input INTP1/TI01 P02 output bit-wise. INTP2 P03 If used as an input port, an on-chip INTP3 P04 pull-up resistor can be...

60 CHAPTER 3 PIN FUNCTION ( µ PD78058F SUBSERIES) (1) Port pins (2/3) Pin Name Input/Output Function After Reset Alternate Function P30 Input/ Port 3. Input TO0 P31 output 8-bit input/output port. TO1 P32 Input/output mode can be specified bit-wise. TO2 P33 If used as an input port, an on-chip pull-...

61 CHAPTER 3 PIN FUNCTION ( µ PD78058F SUBSERIES) (1) Port pins (3/3) Pin Name Input/Output Function After Reset Alternate Function P120 to P127 Input/ Port 12. Input RTP0 to RTP7 output 8-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, an on-chip pull-u...

63 CHAPTER 3 PIN FUNCTION ( µ PD78058F SUBSERIES) (2) Non-port pins (2/2) Pin Name Input/Output Function After Reset Alternate Function AD0 to AD7 Input/Output Low-order address/data bus when expanding external memory Input P40 to P47 A8 to A15 Output High-order address bus when expanding external m...

65 CHAPTER 3 PIN FUNCTION ( µ PD78058F SUBSERIES) 3.2 Description of Pin Functions 3.2.1 P00 to P07 (Port 0) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt request input, an external count clock input to the timer, a capture trigger ...

67 CHAPTER 3 PIN FUNCTION ( µ PD78058F SUBSERIES) (d) BUSY Serial interface automatic transmit/receive busy input pins (e) STB Serial interface automatic transmit/receive strobe output pins Caution When this port is used as a serial interface pin, the I/O and output latches must be set according to ...

69 CHAPTER 3 PIN FUNCTION ( µ PD78058F SUBSERIES) (1) Port mode These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with port mode register 6 (PM6). P60 to P63 are N-ch open drain outputs. Mask ROM version can contain pull-up resistors with the m...

70 CHAPTER 3 PIN FUNCTION ( µ PD78058F SUBSERIES) 3.2.9 P120 to P127 (Port 12) These are 8-bit input/output ports. Besides serving as input/output ports, they function as a real-time output port. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit inp...

72 CHAPTER 3 PIN FUNCTION ( µ PD78058F SUBSERIES) 3.2.21 IC (Mask ROM version only) The IC (Internally Connected) pin is provided to set the test mode to check the µ PD78058F Subseries at delivery. Connect it directly to the V SS with the shortest possible wire in the normal operating mode. When a v...

78 CHAPTER 4 PIN FUNCTION ( µ PD78058FY SUBSERIES) N-ch open drain input/output port.On-chip pull-up resistor can bespecified by mask option.(Mask ROM version only).LEDs can be driven directly. (1) Port pins (2/3) Pin Name Input/Output Function After Reset Alternate Function P30 Input/ Port 3. Input...

81 CHAPTER 4 PIN FUNCTION ( µ PD78058FY SUBSERIES) (2) Non-port pins (2/2) Pin Name Input/Output Function After Reset Alternate Function AD0 to AD7 Input/Output Low-order address/data bus when expanding external memory Input P40 to P47 A8 to A15 Output High-order address bus when expanding external ...

83 CHAPTER 4 PIN FUNCTION ( µ PD78058FY SUBSERIES) 4.2 Description of Pin Functions 4.2.1 P00 to P07 (Port 0) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt request input, an external count clock input to the timer, a capture trigger...

95 CHAPTER 5 CPU ARCHITECTURE 5.1 Memory Spaces 64-Kbyte memory spaces can be accessed in the µ PD78058F, 78058FY Subseries. Figures 5-1 to 5-3 show memory maps. Figure 5-1. Memory Map ( µ PD78056F, 78056FY) 0000H Data memory space General Registers 32 × 8 bits Internal ROM 49152 × 8 bits BFFFH 1000...

96 CHAPTER 5 CPU ARCHITECTURE Figure 5-2. Memory Map ( µ PD78058F, 78058FY) Note When internal ROM size is 60 Kbytes, the area F000H to F3FFH cannot be used. F000H to F3FFH can be used as external memory by setting the internal ROM size to less than 56 Kbytes by the memory size switching register (I...

98 CHAPTER 5 CPU ARCHITECTURE 5.1.1 Internal program memory space The µ PD78056F and µ PD78056FY are Mask ROM with a 49152 x 8 bit configuration, the µ PD78058F and µ PD78058FY are Mask ROM with a 61440 x 8 bit configuration and the µ PD78P058F and µ PD78P058FY are PROM with a 61440 x 8 bit configur...

99 CHAPTER 5 CPU ARCHITECTURE (2) CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) CALLF instruction entry area The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CA...

100 CHAPTER 5 CPU ARCHITECTURE 5.1.5 Data memory addressing The method to specify the address of the instruction to be executed next, or the address of a register or memory to be manipulated when an instruction is executed is called addressing. The address of the instruction to be executed next is a...

101 CHAPTER 5 CPU ARCHITECTURE Figure 5-5. Data Memory Addressing ( µ PD78058F, 78058FY) Note When internal ROM size is 60 Kbytes, the area F000H to F3FFH cannot be used. F000H to F3FFH can be used as external memory by setting the internal ROM size to less than 56 Kbytes by the memory size switchin...

103 CHAPTER 5 CPU ARCHITECTURE 5.2 Processor Registers The µ PD78058F and 78058FY Subseries units incorporate the following processor registers. 5.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (...

104 CHAPTER 5 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When IE = 0, all interrupts except non-maskable interrupt requests are disabled (DI status). When IE = 1, interrupts are enabled (EI status). At this time, acknow...

105 CHAPTER 5 CPU ARCHITECTURE RETI and RETB Instruction PSW PC15-PC8 PC15-PC8 PC7-PC0 Register Pair Lower SP SP + 2 SP Register Pair Upper RET Instruction POP rp Instruction SP + 1 PC7-PC0 SP SP + 2 SP SP + 1 SP + 2 SP SP + 1 SP SP + 3 Interrupt andBRK Instruction PSW PC15-PC8 PC15-PC8 PC7-PC0 Regi...

106 CHAPTER 5 CPU ARCHITECTURE 5.2.2 General registers A general register is mapped at particular addresses (FEE0H to FEFFH) of the data memory. It consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L and H). Each register can also be used as an 8-bit register. Two...

107 CHAPTER 5 CPU ARCHITECTURE Figure 5-12. General Register Configuration (a) Absolute Name (b) Function Name BANK0 BANK1 BANK2 BANK3 FEFFH FEF8HFEF7H FEE0H RP3 RP2 RP1 RP0 R7 15 0 7 0 R6 R5 R4 R3 R2 R1 R0 16-Bit Processing 8-Bit Processing FEE0HFEEFH FEE8HFEE7H BANK0 BANK1 BANK2 BANK3 FEFFH FEF8HF...

110 CHAPTER 5 CPU ARCHITECTURE Address Special-Function Register (SFR) Name Symbol R/W After Reset FF38H Correction address register 0 Note CORAD0 R/W — — √ 0000H FF39H FF3AH Correction address register 1 Note CORAD1 — — √ FF3BH FF40H Timer clock select register 0 TCL0 √ √ — 00H FF41H Timer clock se...

112 CHAPTER 5 CPU ARCHITECTURE 15 0 PC + 15 0 8 7 6 S 15 0 PC α jdisp8 When S = 0, all bits of α are 0. When S = 1, all bits of α are 1. PC indicates the start addressof the instructionafter the BR instruction. ... 5.3 Instruction Address Addressing An instruction address is determined by program co...

113 CHAPTER 5 CPU ARCHITECTURE 5.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. The CALL !addr16 and BR !add...

115 CHAPTER 5 CPU ARCHITECTURE 7 0 rp 0 7 A X 15 0 PC 8 7 5.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustra...

116 CHAPTER 5 CPU ARCHITECTURE 5.4 Operand Address Addressing The following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 5.4.1 Implied addressing [Function] The register which functions as an accumulator (A and...

117 CHAPTER 5 CPU ARCHITECTURE 5.4.2 Register addressing [Function] This addressing accesses a general register as an operand. The general register accessed is specified by the register bank select flags (RBS0 and RBS1) and register specify code (Rn or RPn) in an instruction code. Register addressin...

118 CHAPTER 5 CPU ARCHITECTURE 5.4.3 Direct addressing [Function] This addressing directly addresses the memory indicated by the immediate data in an instruction word. [Operand format] Identifier Description addr16 Label or 16-bit immediate data [Description example] MOV A, !0FE00H; when setting !ad...

120 CHAPTER 5 CPU ARCHITECTURE 15 0 Short Direct Memory Effective Address 1 1 1 1 1 1 1 8 7 0 7 OP code saddr-offset α [Description example] MOV 0FE30H, #50H; when setting saddr to FE30H and immediate data to 50H Operation code 0 0 0 1 0 0 0 1 OP code 0 0 1 1 0 0 0 0 30H (saddr-offset) 0 1 0 1 0 0 0...

123 CHAPTER 5 CPU ARCHITECTURE 5.4.7 Based addressing [Function] This addressing addresses the memory by adding 8-bit immediate data to the contents of the HL register pair which is used as a base register and by using the result of the addition. The HL register pair to be accessed is in the registe...

125 CHAPTER 6 PORT FUNCTIONS 6.1 Port Functions The µ PD78058F and 78058FY Subseries units incorporate two input ports and sixty-seven input/output ports. Figure 6-1 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control ope...

126 CHAPTER 6 PORT FUNCTIONS Pin Name Function Alternate Function P00 Port 0. Input only INTP0/TI00 P01 8-bit input/output port. Input/output mode can be specified INTP1/TI01 P02 bit-wise. INTP2 P03 If used as an input port, an on-chip pull-up INTP3 P04 resistor can be used by software. INTP4 P05 IN...

127 CHAPTER 6 PORT FUNCTIONS P70 SI2/RxD P71 SO2/TxD P72 SCK2/ASCK P120 to P127 RTP0 to RTP7 P130 and P131 ANO0, ANO1 Table 6-1. Port Functions ( µ PD78058F Subseries) (2/2) Pin Name Function Alternate Function P60 Port 6. N-ch open-drain input/output port. — P61 8-bit input/output port. On-chip pul...

130 CHAPTER 6 PORT FUNCTIONS Control register 6.2 Port Configuration A port consists of the following hardware: Table 6-3. Port Configuration Item Configuration Port mode register (PMm: m = 0 to 3, 5 to 7, 12, 13) Pull-up resistor option register (PUOH, PUOL) Memory expansion mode register (MM) Note...

131 CHAPTER 6 PORT FUNCTIONS P00/INTP0/TI00,P07/XT1 RD Internal bus Figure 6-2. P00 and P07 Block Diagram Figure 6-3. P01 to P06 Block Diagram PUO : Pull-up resistor option register PM : Port mode register RD : Port 0 read signal WR : Port 0 write signal P-ch WR PM WR PORT RD WR PUO AV DD P01/INTP1/...

133 CHAPTER 6 PORT FUNCTIONS 6.2.3 Port 2 ( µ PD78058F Subseries) Port 2 is an 8-bit input/output port with output latch. P20 to P27 pins can specify the input mode/output mode in 1-bit units with the port mode register 2 (PM2). When P20 to P27 pins are used as input ports, an on-chip pull-up resist...

135 CHAPTER 6 PORT FUNCTIONS 6.2.4 Port 2 ( µ PD78058FY Subseries) Port 2 is an 8-bit input/output port with output latch. P20 to P27 pins can specify the input mode/output mode in 1-bit units with the port mode register 2 (PM2). When P20 to P27 pins are used as input ports, an on-chip pull-up resis...

138 CHAPTER 6 PORT FUNCTIONS P40 P41 P42 P43 P44 P45 P46 P47 Falling EdgeDetection Circuit KRMK KRIF Set Signal Standby ReleaseSignal 6.2.6 Port 4 Port 4 is an 8-bit input/output port with output latch. P40 to P47 pins can specify the input mode/output mode in 8-bit units with the memory expansion m...

140 CHAPTER 6 PORT FUNCTIONS 6.2.8 Port 6 Port 6 is an 8-bit input/output port with output latch. P60 to P67 pins can specify the input mode/output mode in 1-bit units with the port mode register 6 (PM6). This port has functions related to pull-up resistors as shown below. These functions depending ...

146 CHAPTER 6 PORT FUNCTIONS 6.3 Port Function Control Registers The following four types of registers control the ports. • Port mode registers (PM0 to PM3, PM5 to PM7, PM12, PM13) • Pull-up resistor option register (PUOH, PUOL) • Memory expansion mode register (MM) • Key return mode register (KRM) ...

149 CHAPTER 6 PORT FUNCTIONS (2) Pull-up resistor option register (PUOH, PUOL) This register is used to set whether to use an internal pull-up resistor at each port or not. A pull-up resistor is internally used at bits which are set to the input mode at a port where on-chip pull-up resistor use has ...

150 CHAPTER 6 PORT FUNCTIONS (3) Memory expansion mode register (MM) This register is used to set input/output of port 4. MM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 10H. Figure 6-21. Memory Expansion Mode Register Format Note The full address m...

151 CHAPTER 6 PORT FUNCTIONS KRIF Key Return Signal Detection Flag 0 1 Not Detected Detected (Falling edge detection of port 4) 0 0 0 0 KRM FFF6H 7 6 5 4 3 2 Symbol 1 0 KRMK KRIF 0 0 KRMK Standby Mode Control by Key Return Signal 0 1 Standby mode release enabled Standby mode release disabled Address...

152 CHAPTER 6 PORT FUNCTIONS 6.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 6.4.1 Writing to input/output port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents ar...

153 CHAPTER 6 PORT FUNCTIONS 6.4.3 Operations on input/output port (1) Output mode An operation is performed on the output latch contents, and the result is written to the output latch. The output latch contents are output from the pins. Once data is written to the output latch, it is retained until...

155 CHAPTER 7 CLOCK GENERATOR 7.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are available. (1) Main system clock oscillator This circuit oscillates at frequencies of 1 to 5....

156 CHAPTER 7 CLOCK GENERATOR Figure 7-1. Block Diagram of Clock Generator Subsystem Clock Oscillator Main SystemClock Oscillator X2 X1 XT2 XT1/P07 FRC STOP MCC FRC CLS CSS PCC2 PCC1 Internal Bus Standby Control Circuit To INTP0 Sampling Clock 2 f XX 2 2 f XX 2 3 f XX 2 4 f XX Prescaler Clock to Per...

157 CHAPTER 7 CLOCK GENERATOR 7.3 Clock Generator Control Register The clock generator is controlled by the following two registers: • Processor clock control register (PCC) • Oscillation mode selection register (OSMS) (1) Processor clock control register (PCC) The PCC sets whether to use CPU clock ...

158 CHAPTER 7 CLOCK GENERATOR Figure 7-3. Processor Clock Control Register Format Notes 1. Bit 5 is Read Only. 2. When the CPU is operating on the subsystem clock, MCC should be used to stop the main system clock oscillation. A STOP instruction should not be used. Caution Bit 3 must be set to 0. Rem...

159 CHAPTER 7 CLOCK GENERATOR The fastest instruction of the µ PD78075F and 78075FY Subseries can be executed in two clocks of the CPU clock. The relationship between the CPU clock (f CPU ) and the minimum instruction execution time is shown in Table 7-2. Table 7-2. Relationship Between CPU Clock an...

160 CHAPTER 7 CLOCK GENERATOR Figure 7-5. Main System Clock Waveform due to Writing to OSMS Caution 2. When writing “1” to MCS, V DD must be 2.7 V or higher before the write execution. Remarks f xx : Main system clock frequency (fx or fx/2) f x : Main system clock oscillation frequency Write to OSMS...

161 CHAPTER 7 CLOCK GENERATOR 7.4 System Clock Oscillator 7.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 5.0 MHz) connected to the X1 and X2 pins. External clocks can be input to the main system clock oscillat...

162 CHAPTER 7 CLOCK GENERATOR 7.4.2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 and XT2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the XT1 ...

163 CHAPTER 7 CLOCK GENERATOR Figure 7-8. Examples of Resonator with Incorrect Connection (2/2) (c) Changing high current is too near a (d) Current flows through the grounding line signal line of the resonator (potential at points A, B, and C fluctuate) (e) Signals are fetched Remark When using a su...

164 CHAPTER 7 CLOCK GENERATOR 7.4.3 Scaler The scaler divides the main system clock oscillator output (f XX ) and generates various clocks. 7.4.4 When no subsystem clocks are used If it is not necessary to use subsystem clocks for low power consumption operations and clock operations, connect the XT...

165 CHAPTER 7 CLOCK GENERATOR 7.5 Clock Generator Operations The clock generator generates the following various types of clocks and controls the CPU operating mode including the standby mode. • Main system clock f XX • Subsystem clock f XT • CPU clock f CPU • Clock to peripheral hardware The follow...

166 CHAPTER 7 CLOCK GENERATOR MCC CSS CLS Main System Clock Oscillation Subsystem Clock Oscillation CPU Clock L L Oscillation does not stop. 7.5.1 Main system clock operations When operated with the main system clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 0), the foll...

167 CHAPTER 7 CLOCK GENERATOR MCC CSS CLS Main System Clock Oscillation Subsystem Clock Oscillation CPU Clock Figure 7-9. Main System Clock Stop Function (2/2) (c) Operation when CSS is set after setting MCC with main system clock operation 7.5.2 Subsystem clock operations When operated with the sub...

168 CHAPTER 7 CLOCK GENERATOR Table 7-3. Maximum Time Required for CPU Clock Switchover × × × × 1 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 CSS 0 0 0 0 × PCC0 PCC1 PCC2 1 × 1 PCC0 CSS PCC2 PCC1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 × 1 × × 1 8 instructions 2 instructions 4 instructions 4 instructions 16 instructions 2 ...

169 CHAPTER 7 CLOCK GENERATOR V DD RESET Interrupt Request Signal System Clock CPU Clock Wait (26.2 ms : 5.0 MHz) Internal Reset Operation MinimumSpeedOperation Maximum SpeedOperation Subsystem ClockOperation f XX f XX f XT f XX High-SpeedOperation 7.6.2 System clock and CPU clock switching procedur...

171 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.1 Overview of the µ PD78058F and 78058FY Subseries On-Chip Timers This chapter describes the 16-bit timer/event counter and begins with an overview of the on-chip timers and related devices of the µ PD78058F and 78058FY Subseries. (1) 16-bit timer/event cou...

173 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.2 16-Bit Timer/Event Counter Functions The 16-bit timer/event counter (TM0) has the following functions. • Interval timer • PWM output • Pulse width measurement • External event counter • Square-wave output • One-shot pulse output PWM output and pulse width...

174 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (5) Square-wave output TM0 can output a square wave with any selected frequency. Table 8-3. 16-Bit Timer/Event Counter Square-Wave Output Ranges Minimum Pulse Width Maximum Pulse Width Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 2 × TI00 input ...

175 CHAPTER 8 16-BIT TIMER/EVENT COUNTER TCL06 TCL05 TCL04 Timer Clock Selection Register 0 3 Internal bus Capture/Compare Control Register 0 CRC02 CRC01 CRC00 Selector TI01/P01/INTP1 INTTM3 2f XX f XX f XX /2 f XX /2 2 Selector 16-Bit Capture/Compare Register 01 (CR01) Internal Bus 16-Bit Capture/C...

180 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscillation frequency 3. f XT : Subsystem clock oscillation frequency 4. TI00 : 16-bit timer/event counter input pin 5. TM0 : 16-bit timer register 6. MCS : Bit 0 of osci...

181 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 0 0 0 TMC03 TMC02 TMC01 OVF0 7 6 5 4 3 2 1 0 Symbol TMC0 FF48H 00H R/W Address After Reset R/W OVF0 16-Bit Timer Register Overflow Detection 0 Overflow not detected 1 Overflow detected TMC03 TMC02 TMC01 Operating Mode Clear Mode Selection TO0 Output Timing ...

183 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0 7 6 5 4 3 2 1 0 Symbol TOC0 FF4EH 00H R/W Address After Reset R/W TOE0 16-Bit Timer/Event Counter Output Control 0 Output disabled (Port mode) 1 Output enabled TOC01 0 1 In PWM Mode In Other Modes Active level selection ...

184 CHAPTER 8 16-BIT TIMER/EVENT COUNTER PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 7 6 5 4 3 2 1 0 Symbol PM3 FF23H FFH R/W Address After Reset R/W PM3n P3n Pin Input/Output Mode Selection (n = 0 to 7) 0 Output mode (output buffer ON) 1 Input mode (output buffer OFF) (5) Port mode register 3 (PM3) Thi...

185 CHAPTER 8 16-BIT TIMER/EVENT COUNTER ES31 ES30 ES21 ES20 ES11 ES10 0 0 7 6 5 4 3 2 1 0 Symbol INTM0 FFECH 00H R/W Address After Reset R/W ES11 INTP0 Valid Edge Selection ES10 0 Falling edge 0 0 Rising edge 1 1 Setting prohibited 0 1 Both falling and rising edges 1 ES21 INTP1 Valid Edge Selection...

186 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 0 0 0 0 0 SCS1 SCS0 7 6 5 4 3 2 1 0 Symbol SCS FF47H 00H R/W Address After Reset R/W SCS1 SCS0 0 0 0 1 1 0 1 1 INTP0 Sampling Clock Selection MCS = 1 MCS = 0 f XX /2 N f X /2 7 (39.1 kHz) f XX /2 7 f X /2 8 (19.5 kHz) f X /2 5 (156.3 kHz) f XX /2 5 f X /2 6...

187 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 0 0 0 0 0/1 0/1 0 CRC02 CRC01 CRC00 CRC0 CR00 set as compare register 0 0 0 0 1 1 0/1 0 TMC03 TMC02 TMC01 OVF0 TMC0 Clear & start on match TM0 and CR00 8.5 16-Bit Timer/Event Counter Operations 8.5.1 Interval timer operations Setting the 16-bit timer mo...

188 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 16-Bit Capture/Compare Register 00 (CR00) 16-Bit Timer Register (TM0) Selector f XX /2 2 f XX /2 f XX 2f XX INTTM3 TI00/P00/INTP0 OVF0 Clear Circuit INTTM00 Figure 8-11. Interval Timer Configuration Diagram Figure 8-12. Interval Timer Operation Timings Remark...

189 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Table 8-6. 16-Bit Timer/Event Counter Interval Times Minimum Interval Time Maximum Interval Time Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 0 0 0 2 × TI00 input cycle 2 16 × TI00 input cycle TI00 input edge cycle 0 0 1 Setting 2 × 1/f X Settin...

190 CHAPTER 8 16-BIT TIMER/EVENT COUNTER TOE0 TOC01 LVR0 LVS0 TOC04 OSPE OSPT TOC0 1 0/1 × × × × × 0 TO0 Output Enabled Specifies Active Level CRC00 CRC01 CRC02 CRC0 0 0/1 0/1 0 0 0 0 0 CR00 set as compare register TMC0 0 1 0 0 0 0 0 0 OVF0 TMC01 TMC02 TMC03 PWM mode Figure 8-13. Control Register Se...

191 CHAPTER 8 16-BIT TIMER/EVENT COUNTER By integrating 14-bit resolution PWM pulses with an external low-pass filter, they can be converted to an analog voltage and used for electronic tuning and D/A converter applications, etc. The analog output voltage (V AN ) used for D/A conversion with the con...

193 CHAPTER 8 16-BIT TIMER/EVENT COUNTER TMC0 0 0/1 1 0 0 0 0 0 OVF0 TMC01 TMC02 TMC03 Free-Running Mode CRC0 0 0/1 1 0 0 0 0 0 CRC00 CRC01 CRC02 CR00 set as compare register CR01 set as capture register 8.5.4 Pulse width measurement operations It is possible to measure the pulse width of the signal...

194 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Selector f XX /2 2 f XX /2 f XX 2f XX INTTM3 16-Bit Timer Register (TM0) 16-Bit Capture/Compare Register 01 (CR01) OVF0 INTP0 Internal Bus TI00/P00/INTP00 Count Clock TM0 Count Value TI00 Pin Input CR01 Captured Value INTP0 OVF0 0000 0001 D0 D1 FFFF 0000 D2 D...

195 CHAPTER 8 16-BIT TIMER/EVENT COUNTER CRC0 1 0 1 0 0 0 0 0 CRC00 CRC01 CRC02 CR00 set as capture register Captured in CR00 on valid edge of TI01/P01 Pin CR01 set as capture register TMC0 0 0/1 1 0 0 0 0 0 OVF0 TMC01 TMC02 TMC03 Free-Running Mode (2) Measurement of two pulse widths with free-runni...

196 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Count Clock TM0 Count Value TI00 Pin Input CR01 Captured Value INTP0 TI01 Pin Input t CR00 Captured Value INTP1 OVF0 (D1 – D0) × t (10000H – D1 + D2) × t (10000H – D1 + (D2 + 1)) × t (D3 – D2) × t 0000 0001 D0 D1 0000 D3 D2 FFFF D0 D1 D3 D2 D1 Figure 8-21. Ti...

197 CHAPTER 8 16-BIT TIMER/EVENT COUNTER CRC0 1 1 1 0 0 0 0 0 CRC00 CRC01 CRC02 CR00 set as capture register Captured in CR00 on invalid edge ofTI00/P00 Pin CR01 set as capture register TMC0 0 0/1 1 0 0 0 0 0 OVF0 TMC01 TMC02 TMC03 Free-Running Mode (3) Pulse width measurement with free-running coun...

198 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Count Clock TM0 Count Value TI00 Pin Input CR01 Captured Value CR00 Captured Value INTP0 OVF0 (D1-D0) × t (10000H-D1 + D2) × t (D3-D2) × t D1 D3 D0 D2 D3 D2 0000 FFFF D1 D0 0000 0001 t Figure 8-23. Timing of Pulse Width Measurement Operation by Free-Running C...

199 CHAPTER 8 16-BIT TIMER/EVENT COUNTER CRC0 1 1 1 0 0 0 0 0 CRC00 CRC01 CRC02 CR00 set as capture register Captured in CR00 on invalid edge of TI00/P00 Pin CR01 set as capture register TMC0 0 0/1 0 1 0 0 0 0 OVF0 TMC01 TMC02 TMC03 Clear & start with valid edge of TI00/P00 pin (4) Pulse width m...

201 CHAPTER 8 16-BIT TIMER/EVENT COUNTER TI00 Pin Input TM0 Count Value CR00 INTTM0 N 0000 0001 0002 0003 0004 0005 N-1 N 0000 0001 0002 0003 16-Bit Capture/Compare Register 00 (CR00) Clear INTTM00 INTP0 16-Bit Timer Register (TM0) 16-Bit Capture/Compare Register 01 (CR01) Internal Bus TI00 Valid Ed...

202 CHAPTER 8 16-BIT TIMER/EVENT COUNTER TOC0 1 1 0/1 0/1 0 0 0 0 TOE0 TOC01 LVR0 OSPT OSPE TOC04 LVS0 TO0 Output EnabledInversion of output on match of TM0 and CR00Specified TO0 output F/F initial valueNo inversion of output on match of TM0 and CR01 One-shot pulse output disabled CRC0 0 0/1 0/1 0 0...

206 CHAPTER 8 16-BIT TIMER/EVENT COUNTER CRC0 0 0/1 0 0 0 0 0 0 CRC00 CRC01 CRC02 CR00 set as compare register CR01 set as compare register TOC0 1 1 0/1 0/1 1 1 0 0 TOE0 TOC01 LVR0 LVS0 OSPT OSPE TOC04 TO0 Output Enabled Inversion of output on match of TM0 and CR00 Specified TO0 output F/F initial v...

209 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Count Pulse TM0 Count Value Edge Input Interrupt Request Flag Capture Read Signal CR01 Captured Value Capture OperationIgnored X N+1 N N+1 N+2 M M+1 M+2 (4) Capture register data retention timings If the valid edge of the TI00/P00 pin is input during 16-bit c...

210 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Count Pulse CR00 TM0 OVF0 INTTM00 FFFFH FFFEH FFFFH 0000H 0001H (7) Operation of OVF0 flag OFV0 flag is set to 1 in the following case. The clear & start mode on match between TM0 and CR00 is selected. ↓ CR00 is set to FFFFH. ↓ When TM0 is counted up from...

216 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 9.2 8-Bit Timer/Event Counter Configuration The 8-bit timer/event counters 1 and 2 consist of the following hardware. Table 9-5. 8-Bit Timer/Event Counter Configuration Item Configuration Timer register 8 bits × 2 (TM1, TM2) Register Compare register: 8 bits ...

218 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS LVR2 LVS2 TOC15 INTTM2 R S INV Level F/F (LV2) f SCK P32Output Latch PM32 TOE2 TO2/P32 Q LVR1 LVS1 TOC11 INTTM1 R S INV Q P31Output Latch TOE1 PM31 TO1/P31 Level F/F (LV1) Figure 9-2. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1 Remark ...

219 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (1) Compare registers 10 and 20 (CR10, CR20) These are 8-bit registers to compare the value set to CR10 to the 8-bit timer register 1 (TM1) count value, and the value set to CR20 to the 8-bit timer register 2 (TM2) count value, and, if they match, generate an...

221 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS TCL17 TCL16 TCL15 TCL14 TCL13 TCL12 TCL11 TCL10 7 6 5 4 3 2 1 0 Symbol TCL1 FF41H 00H R/W Address After Reset R/W TCL13 TCL12 TCL11 TCL10 0 0 0 0 TI1 falling edge 0 0 0 1 TI1 rising edge 0 1 1 0 0 1 1 1 f XX /2 f X /2 (2.5 MHz) f X /2 2 (1.25 MHz) 1 0 0 0 f X...

222 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 0 1 2 3 4 5 6 7 Symbol TCE1 FF49H 00H R/W Address After Reset R/W TCE2 TMC12 0 0 0 0 0 TMC1 TCE1 8-Bit Timer Register 1 Operation Control 0 Operation stop (TM1 clear to 0) 1 Operation enable TCE2 8-Bit Timer Register 2 Operation Control Operation stop (TM2 cl...

223 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 0 1 2 3 4 5 6 7 Symbol TOE1 TOC11 LVR1 LVS1 TOE2 TOC15 LVR2 LVS2 TOC1 FF4FH 00H R/W Address After Reset R/W TOE1 8-Bit Timer/Event Counter 1 Outptut Control 0 Output disable (port mode) 1 Output enable TOC11 8-Bit Timer/Event Counter 1 Timer Output F/F Contro...

226 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Table 9-6. 8-Bit Timer/Event Counter 1 Interval Time Minimum Interval Time Maximum Interval Time Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 0 0 0 0 TI1 input cycle 2 8 × TI1 input cycle TI1 input edge cycle 0 0 0 1 TI1 input cycle 2 8 × TI1 in...

228 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS TI1 Pin Input TM1 Count Value INTTM1 CR10 00 01 02 03 04 05 N-1 N 00 01 02 03 N (2) External event counter operation The external event counter counts the number of external clock pulses to be input to the TI1/P33 and TI2/ P34 pins with 8-bit timer registers ...

230 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Figure 9-10. Square-Wave Output Operation Timing Note The initial value of TO1 output can be set with bits 2 and 3 (LVR1 and LVS1) of the 8-bit timer output control register (TOC1). 9.4.2 16-bit timer/event counter mode When bit 2 (TMC12) of the 8-bit timer m...

236 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS TI1, TI2, Input CR10, CR20 TM1, TM2 Count Value TO1, TO2 Interrupt Request Flag 00H 00H 00H 00H 00H Count Pulse TM1, TM2 Count Value 00H 01H 02H 03H 04H Timer Start 9.5 Cautions on 8-Bit Timer/Event Counters (1) Timer start errors An error of one clock maximu...

237 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Count Pulse CR10, CR20 TM1, TM2 Count Value X-1 X FFH 00H 01H 02H M N (3) Operation after compare register change during timer count operation If the values after the 8-bit compare registers 10 and 20 (CR10 and CR20) are changed are smaller than those of 8-bi...

240 CHAPTER 10 WATCH TIMER 10.2 Watch Timer Configuration The watch timer consists of the following hardware. Table 10-2. Watch Timer Configuration Item Configuration Counter 5 bits × 1 Timer clock select register 2 (TCL2) Watch timer mode control register (TMC2) 10.3 Watch Timer Control Registers T...

241 CHAPTER 10 WATCH TIMER TMC21 Prescaler Selector INTWT 5-Bit Counter f W 2 14 f W 2 13 INTTM3 To 16-Bit Timer/Event Counter Watch Timer Mode Control Register TMC26 TMC25 TMC24 TMC23 TMC22 TMC21 TMC20 Internal Bus TCL24 Timer ClockSelect Register 2 3 f W 2 4 f W 2 5 f W 2 6 f W 2 7 f W 2 8 f W 2 9...

242 CHAPTER 10 WATCH TIMER TCL27 7 TCL26 6 TCL25 TCL24 4 0 3 2 1 0 FF42H Address TCL2 Symbol TCL22 TCL21 TCL20 5 00H After Reset R / W R / W 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 TCL22 TCL21 TCL20 f XX / 2 3 f XX / 2 4 f XX / 2 5 f XX / 2 6 f XX / 2 7 f XX / 2 8 f XX / 2 9 f XX / 2 11 f X ...

243 CHAPTER 10 WATCH TIMER 0 7 TMC26 6 TMC25 TMC24 4 TMC23 3 2 1 0 FF4AH Address TMC2 Symbol TMC22 TMC21 TMC20 5 00H After Reset R / W R / W 0 1 TMC23 2 14 / f W (0.4 sec) 2 13 / f W (0.2 sec) Watch Flag Set Time Selection 0 0 0 0 1 1 Other than above 0 0 1 1 0 0 0 1 0 1 0 1 TMC26 TMC25 TMC24 2 4 / ...

244 CHAPTER 10 WATCH TIMER 10.4 Watch Timer Operations 10.4.1 Watch timer operation When the 32.768-kHz subsystem clock or 4.19-MHz main system clock is used, the timer operates as a watch timer with a 0.5-second or 0.25-second interval. The watch timer sets the test input flag (WTIF) to 1 at the co...

246 CHAPTER 11 WATCHDOG TIMER (2) Interval timer mode Interrupt requests are generated at the preset time intervals. Table 11-2. Interval Times Interval Time MCS = 1 CS = 0 2 11 × 1/f XX 2 11 × 1/f X (410 µ s) 2 12 × 1/f X (819 µ s) 2 12 × 1/f XX 2 12 × 1/f X (819 µ s) 2 13 × 1/f X (1.64 ms) 2 13 × ...

247 CHAPTER 11 WATCHDOG TIMER Prescaler f XX 2 4 f XX 2 5 f XX 2 6 f XX 2 7 f XX 2 8 f XX 2 9 Selector Watchdog Timer Mode Register Internal Bus Internal Bus TCL22 TCL21 TCL20 f XX /2 3 f XX 2 11 Timer Clock Select Register 2 3 WDTM4 RUN WDTM3 8-Bit Counter TMMK4 RUN TMIF4 INTWDTMaskable InterruptRe...

248 CHAPTER 11 WATCHDOG TIMER 11.3 Watchdog Timer Control Registers The following two types of registers are used to control the watchdog timer. • Timer clock select register 2 (TCL2) • Watchdog timer mode register (WDTM) (1) Timer clock select register 2 (TCL2) This register sets the watchdog timer...

249 CHAPTER 11 WATCHDOG TIMER Figure 11-2. Timer Clock Select Register 2 Format Caution When rewriting TCL2 to other data, stop the timer operation beforehand. Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscillation frequency 3. f XT : Subsystem clock osc...

250 CHAPTER 11 WATCHDOG TIMER RUM 7 0 6 0 WDTM4 4 WDTM3 3 2 1 0 FFF9H Address WDTM Symbol 0 0 0 5 00H After Reset R / W R / W RUN 0 1 Count stop Counter is cleared and counting starts. WDTM3 × 0 1 Interval timer mode Note 2 (Maskable interrupt request occurs upon generation of an overflow.) Watchdog...

251 CHAPTER 11 WATCHDOG TIMER 11.4 Watchdog Timer Operations 11.4.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to detect any runaway. The watchdog timer count clock (runaway detection time interval) can be select...

252 CHAPTER 11 WATCHDOG TIMER 11.4.2 Interval timer operation The watchdog timer operates as an interval timer which generate interrupt request repeatedly at an interval of the preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 0. A count clock (interval time)...

253 CLOE PCL/P35 Pin Output * * CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12.1 Clock Output Control Circuit Functions The clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSI. Clocks selected with the timer cloc...

254 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12.2 Clock Output Control Circuit Configuration The clock output control circuit consists of the following hardware. Table 12-1. Clock Output Control Circuit Configuration Item Configuration Timer clock select register 0 (TCL0) Port mode register 3 (PM3) F...

255 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT CLOE 7 TCL06 6 TCL05 TCL04 4 TCL03 3 2 1 0 FF40H Address TCL0 Symbol TCL02 TCL01 TCL00 5 00H After Reset R / W R / W 0 0 0 0 1 1 1 1 1 Other than above 0 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 TCL03 TCL02 TCL01 f XT (32.768 kHz) f XX f XX / 2 f XX / 2 2 f XX / ...

256 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT Remarks 1. f XX : Main system clock frequency (f X or f X /2) 2. f X : Main system clock oscillation frequency 3. f XT : Subsystem clock oscillation frequency 4. TI00 : 16-bit timer/event counter input pin 5. TM0 : 16-bit timer register 6. MCS : Bit 0 of o...

257 Internal Bus f XX /2 9 f XX /2 10 f XX /2 11 TCL27 TCL26 TCL25 3 PM36 Selector Timer Clock Select Register 2 Port Mode Register 3 BUZ / P36 P36 Output Latch CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 13.1 Buzzer Output Control Circuit Functions The buzzer output control circuit outputs 1.2 kHz, 2....

258 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 13.3 Buzzer Output Function Control Registers The following two types of registers are used to control the buzzer output function. • Timer clock select register 2 (TCL2) • Port mode register 3 (PM3) (1) Timer clock select register 2 (TCL2) This register s...

259 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT TCL27 7 TCL26 6 TCL25 TCL24 4 0 3 2 1 0 FF42H Address TCL2 Symbol TCL22 TCL21 TCL20 5 00H After Reset R / W R / W 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 TCL22 TCL21 TCL20 f XX / 2 3 f XX / 2 4 f XX / 2 5 f XX / 2 6 f XX / 2 7 f XX / 2 8 f XX / 2 ...

260 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT PM37 7 PM36 6 PM35 PM34 4 PM33 3 2 1 0 FF23H Address PM3 Symbol PM32 PM31 PM30 5 FFH After Reset R / W R / W PM3n 0 1 Output mode (output buffer ON) Input mode (output buffer OFF) P3n Pin Input /Output Mode Selection (n = 0 to 7) (2) Port mode register 3 ...

261 CHAPTER 14 A/D CONVERTER 14.1 A/D Converter Functions The A/D converter converts an analog input into a digital value. It consists of 8 channels (ANI0 to ANI7) with an 8-bit resolution. The conversion method is based on successive approximation and the conversion result is held in the 8-bit A/D ...

262 CHAPTER 14 A/D CONVERTER 14.2 A/D Converter Configuration The A/D converter consists of the following hardware. Table 14-1. A/D Converter Configuration Item Configuration Analog input 8 Channels (ANI0 to ANI7) A/D converter mode register (ADM) Control register A/D converter input select register...

263 CHAPTER 14 A/D CONVERTER Figure 14-1. A/D Converter Block Diagram Notes 1. Selector to select the number of channels to be used for analog input. 2. Selector to select the channel for A/D conversion. 3. Bits 0 and 1 of External Interrupt Mode Register 1 (INTM1) ANI0/P10ANI1/P11ANI2/P12ANI3/P13AN...

264 CHAPTER 14 A/D CONVERTER (1) Successive approximation register (SAR) The analog input voltage value and the voltage tap (comparative voltage) value from the serial resistance string are compared and the results are stored in this register from the most significant bit (MSB). If values are stored...

266 CHAPTER 14 A/D CONVERTER Figure 14-2. A/D Converter Mode Register Format Notes 1. Set so that the A/D conversion time is 19.1 µ s or more. 2. Setting prohibited because A/D conversion time is less than 19.1 µ s. Cautions 1. The following sequence is recommended for power consumption reduction of...

267 CHAPTER 14 A/D CONVERTER (2) A/D converter input select register (ADIS) This register determines whether the ANI0/P10 to ANI7/P17 pins should be used for analog input channels or ports. Pins other than those selected as analog input can be used as input/output ports. ADIS is set with an 8-bit me...

268 CHAPTER 14 A/D CONVERTER ES71 7 ES70 6 ES61 ES60 4 ES51 3 2 1 0 FFEDH Address INTM1 Symbol ES50 ES41 ES40 5 00H After Reset R / W R / W ES41 0 0 1 1 ES40 0 1 0 1 Falling edge Rising edge Setting prohibited Both falling and rising edges ES51 0 0 1 1 ES50 0 1 0 1 Falling edge Rising edge Setting p...

269 CHAPTER 14 A/D CONVERTER 14.4 A/D Converter Operations 14.4.1 Basic operations of A/D converter (1) Set the number of analog input channels with A/D converter input select register (ADIS). (2) From among the analog input channels set with ADIS, select one channel for A/D conversion with A/D conv...

270 CHAPTER 14 A/D CONVERTER SAR ADCR INTAD A/ D ConverterOperation Sampling Time Sampling A / D Conversion Conversion Time Undefined 80H C0H or 40H ConversionResult ConversionResult Figure 14-5. A/D Converter Basic Operation A/D conversion operations are performed continuously until bit 7 (CS) of A...

271 CHAPTER 14 A/D CONVERTER 1 512 1 256 3 512 2 256 5 512 3 256 507512 254256 509512 255256 511512 1 255 254 253 3 2 1 0 A /D ConversionResults(ADCR) Input Voltage/AV REF0 14.4.2 Input voltage and conversion results The relation between the analog input voltage input to the analog input pins (ANI0 ...

272 CHAPTER 14 A/D CONVERTER ADM Rewrite CS=1, TRG=1 StandbyState ANIn INTP3 A /D Conversion ADCR INTAD ANIn ANIn ANIn ANIm ANIm ANIn ANIn StandbyState StandbyState ADM Rewrite CS=1, TRG=1 ANIm ANIm ANIm 14.4.3 A/D converter operating mode Select 1 analog input channel from ANI0-ANI7 by the A/D conv...

273 CHAPTER 14 A/D CONVERTER Conversion Start CS=1, TRG=0 A /D Conversion ADCR INTAD ANIn ANIn ANIm ANIn ANIm ANIm ANIn ANIn ADM Rewrite CS=1, TRG=0 ADM Rewrite CS=0, TRG=0 Conversion suspendedConversion results arenot stored Stop (2) A/D conversion operation in software start When bit 6 (TRG) and b...

274 CHAPTER 14 A/D CONVERTER 14.5 A/D Converter Cautions (1) Power consumption in standby mode The A/D converter operates on the main system clock. Therefore, its operation stops in STOP mode or in HALT mode with the subsystem clock. As a current still flows in the AV REF0 pin at this time, this cur...

275 CHAPTER 14 A/D CONVERTER (3) Noise countermeasures In order to maintain 8-bit resolution, attention must be paid to noise on pins AV REF0 and ANI0 to ANI7. Since the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected...

276 CHAPTER 14 A/D CONVERTER A /D Conversion ADCR INTAD ANIn ANIn ANIm ANIm ANIn ANIn ANIm ANIm ADM Rewrite (Start of ANIn Conversion) ADM Rewrite (Start of ANIm Conversion) ADIF is set but ANImconversion has not ended (6) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleare...

277 CHAPTER 14 A/D CONVERTER (7) AV DD pin The AV DD pin is the analog circuit power supply pin, and supplies power to the input circuits of ANI0/P10 to ANI7/P17. Therefore, be sure to apply the same voltage as V DD to this pin even when the application circuit is designed so as to switch to a backu...

279 CHAPTER 15 D/A CONVERTER 15.1 D/A Converter Functions The D/A converter converts a digital input into an analog value. It consists of two 8-bit resolution channels of voltage output type D/A converter. The conversion method used is the R-2R resistor ladder method. D/A conversion is started by se...

280 CHAPTER 15 D/A CONVERTER 15.2 D/A Converter Configuration The D/A converter consists of the following hardware. Table 15-1. D/A Converter Configuration Item Configuration D/A conversion value set register 0 (DACS0) D/A conversion value set register 1 (DACS1) Control register D/A converter mode r...

281 CHAPTER 15 D/A CONVERTER (1) D/A conversion value set register 0, 1 (DACS0, DACS1) DACS0 and DACS1 are registers where values are set for determining the analog voltage output respectively to pins ANO0 and ANO1. DACS0 and DACS1 are set with 8-bit memory manipulation instructions. RESET input set...

282 CHAPTER 15 D/A CONVERTER 0 7 0 6 DAM5 DAM4 4 0 3 2 1 0 FF98H Address DAM Symbol 0 DACE1 DACE0 5 00H After Reset R / W R / W DAM5 0 1 Normal mode Real-time output mode DACE0 0 1 D/A conversion stop D/A conversion enable DACE1 0 1 D/A conversion stop D/A conversion enable DAM4 0 1 Normal mode Real...

283 CHAPTER 15 D/A CONVERTER 15.4 Operations of D/A Converter (1) Select the operation mode for channel 0 using bit 4 (DAM4) of the D/A converter mode register (DAM), and select the operation mode for channel 1 using bit 5 (DAM5). (2) Set data corresponding to the analog voltage values output respec...

284 CHAPTER 15 D/A CONVERTER 15.5 Cautions Related to D/A Converter (1) Output impedance of D/A converter Because the output impedance of the D/A converter is high, use of current flowing from the ANOn pins (n = 0,1) is prohibited. If the input impedance of the load for the converter is low, insert ...

286 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) 16.1 Serial Interface Channel 0 Functions Serial interface channel 0 employs the following four modes. • Operation stop mode • 3-wire serial I/O mode • SBI (serial bus interface) mode • 2-wire serial I/O mode Caution Do not switch the...

288 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) 16.2 Serial Interface Channel 0 Configuration Serial interface channel 0 consists of the following hardware. Table 16-2. Serial Interface Channel 0 Configuration Item Configuration Serial I/O shift register 0 (SIO0) Slave address regi...

289 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) CSIE0 COI WUP CSIM 04 CSIM 03 CSIM 02 CSIM 01 CSIM 00 Serial Operating Mode Register 0 Control Circuit Output Control Selector SI0/SB0/ P25 PM25 Output Control SO0/SB1/ P26 PM26 Output Control SCK0/ P27 PM27 Selector P25Output Latch P...

290 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) (1) Serial I/O shift register 0 (SIO0) This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO0 is set with an 8-...

291 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) (3) SO0 latch This latch holds the SI0/SB0/P25 and SO0/SB1/P26 pin levels. It can be directly controlled by software. In the SBI mode, this latch is set upon termination of the 8th serial clock. (4) Serial clock counter This counter c...

292 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) 16.3 Serial Interface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0. • Timer clock select register 3 (TCL3) • Serial operating mode register 0 (CSIM0) • Serial bus int...

293 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) Serial Interface Channel 0 Serial Clock Selection TCL33 TCL32 TCL31 TCL30 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 f XX /2 f XX /2 2 f XX /2 3 f XX /2 4 f XX /2 5 f XX /2 6 f XX /2 7 f XX /2 8 Setting prohibited...

294 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) (2) Serial operating mode register 0 (CSIM0) This register sets serial interface channel 0 serial clock, operating mode, operation enable/stop wake-up function and displays the address comparator match signal. CSIM0 is set with a 1-bi...

296 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) (3) Serial bus interface control register (SBIC) This register sets serial bus interface operation and displays statuses. SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Figure 16-5. Se...

298 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) (4) Interrupt timing specify register (SINT) This register sets the bus release interrupt and address mask functions and displays the SCK0/P27 pin level status. SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET ...

299 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) 6 5 4 3 2 1 0 7 Symbol CSIM0 CSIE0 COI WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 FF60H 00H R/W Address After Reset R/W CSIE0 0 Serial Interface Channel 0 Operation Control Operation stopped Operation enabled R/W 1 16.4 Serial Interface C...

300 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) 16.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 7...

303 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) RELT CMDT SO0 latch SI0 SCK0 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 CSIIF0 Transfer Start at the Falling Edge of SCK0 End of Transfer (2) Communication operation The 3-wire serial I/O mode ...

304 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) 7 6 Internal Bus 1 0 LSB-first MSB-first Read/Write Gate SI0 Serial I/O Shift Register 0 (SIO0) Read/Write Gate SO0 SCK0 D Q SO0 Latch (4) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to sta...

305 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) 16.4.3 SBI mode operation SBI (Serial Bus Interface) is a high-speed serial interface in compliance with the NEC serial bus format. SBI uses a single master device and employs the clocked serial I/O format with the addition of a bus c...

306 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) (1) SBI functions In the conventional serial I/O format, when a serial bus is configured by connecting two or more devices, many ports and wiring are necessary, to provide chip select signal to identify command and data, and to judge ...

307 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) (2) SBI definition The SBI serial data format and the signals to be used are defined as follows. Serial data to be transferred with SBI consists of three kinds of data: “address”, “command”, and “data”. Figure 16-11 shows the address,...

308 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) SCK0 "H" SB0 (SB1) SCK0 "H" SB0 (SB1) (a) Bus release signal (REL) The bus release signal is a signal with the SB0 (SB1) line which has changed from the low level to the high level when the SCK0 line is at the high lev...

309 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) Master Slave 1 Not Selected Slave 2 Selected Slave 3 Not Selected Slave 4 Not Selected Slave 2Address Transmission SCK0 A7 A6 A5 A4 A3 A2 A1 A0 1 2 3 4 5 6 7 8 SB0 (SB1) Address Command Signal Bus ReleaseSignal (c) Address An address ...

310 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) (d) Command and data The master device transmits commands to, and transmits/receives data to/from the slave device selected by address transmission. Figure 16-16. Commands Figure 16-17. Data 8-bit data following a command signal is de...

311 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) 8 9 ACK SCK0 SB0 (SB1) SCK0 SB0 (SB1) 8 9 10 11 ACK (e) Acknowledge signal (ACK) The acknowledge signal is used to check serial data reception between transmitter and receiver. Figure 16-18. Acknowledge Signal [When output in synchron...

312 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) READY ACK SCK0 SB0 (SB1) BUSY 8 9 (f) Busy signal (BUSY) and ready signal (READY) The BUSY signal is intended to report to the master device that the slave device is preparing for data transmission/reception. The READY signal is inten...

313 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) Notes 1. Bit 6 (COI) is a read-only bit. 2. Can be used as a port. 3. To use the wake-up function (WUP = 1), clear the bit 5 (SIC) of the interrupt timing specify register (SINT) to 0. 4. When CSIE0 = 0, COI becomes 0. 5. In the SBI m...

315 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) R ACKD Acknowledge Detection Clear Conditions (ACKD = 0) • SCK0 fall immediately after the busy mode is released during the transfer start instruction execution.• When CSIE0 = 0 • When RESET input is applied Set Conditions (ACKD = 1) ...

318 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) SCK0 6 SB0 (SB1) ACKT 7 8 9 D2 D1 D0 ACK When set during this period ACK signal is output fora period of one clockjust after setting Figure 16-22. ACKT Operation Caution Do not set ACKT before termination of transfer.

319 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) SB0 (SB1) ACKE If set and cleared during this periodand ACKE = 0 at the falling edge of SCK0 ACK signal is not output D2 D1 D0 SCK0 SB0 (SB1) ACKE 1 2 7 8 9 D7 D6 D2 D1 D0 When ACKE = 0 at this point ACK signal is not output SCK0 Figu...

320 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) SCK0 SB0 (SB1) BSYE 7 8 9 ACK 6 When BSYE = 1 at this point BUSY If reset during this period andBSYE = 0 at the falling edge of SCK0 D2 D1 D0 SB0 (SB1) ACKD ACK 9 SIO0 7 8 D1 6 D2 D0 Transfer StartInstruction Transfer Start SCK0 Figur...

322 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) SCK0 SB0 (SB1) 1 2 7 8 SCK0 SB0 (SB1) 1 2 7 8 CMD SCK0 SB0 (SB1) 1 2 7 8 REL CMD SCK0 SB0 (SB1) 1 2 7 8 9 10 Timing Chart Definition Signal Name Output Device Output Condition Effects on Flag Meaning of Signal Synchronous clock to out...

324 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) (6) Address match detection method In the SBI mode, the master transmits a slave address to select a specific slave device. Coincidence of the addresses can be automatically detected by hardware. CSIIF0 is set only when the slave addr...

327 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) 1 2 3 4 5 6 7 8 9 SCK0 Pin D7 D6 D5 D4 D3 D2 D1 D0 ACK BUSY SB0 (SB1) Pin Program Processing Serial Transmission INTCSI0 Generation ACKD Set SCK0 Stop Hardware Operation ACKT Set Program Processing INTCSI0 Generation ACK Output Hardwa...

328 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) 1 2 3 4 5 6 7 8 9 SCK0 Pin D7 D6 D5 D4 D3 D2 D1 D0 ACK BUSY SB0 (SB1) Pin Program Processing Serial Reception INTCSI0 Generation ACK Output SerialReception Hardware Operation Program Processing INTCSI0 Generation ACKD Set Hardware Ope...

330 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) (10) How to determine the slave busy state When a device is in the master mode, use the following procedure to determine if the slave is in the busy state or not. <1> Detect the generation of an acknowledge signal (ACK) or inter...

331 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) 16.4.4 2-wire serial I/O mode operation The 2-wire serial I/O mode can cope with any communication format by program. Communication is basically carried out with two lines of serial clock (SCK0) and serial data input/output (SB0 or SB...

333 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) 6 5 4 3 2 1 0 7 Symbol SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT RELT When RELT = 1, SO0 Iatch is set to 1. After SO0 Iatch setting, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0. R/W FF61H 00H R/W Address After Rese...

334 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) (2) Communication operation The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization with the serial clock. Shift operation of the serial...

335 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) RELT CMDT SO0 Latch (3) Other signals Figure 16-33 shows RELT and CMDT operations. Figure 16-33. RELT and CMDT Operations (4) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0)...

336 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD78058F SUBSERIES) To InternalCircuit SCK0/P27 P27 Output Latch When CSIE0 = 1 and CSIM01 and CSIM00 are 1 and 0, or 1 and 1. SCK0 (1 while transfer is stopped) From Serial Clock Control Circuit Manipulated by bitmanipulation instruction 16.4.5 SCK0/P27...

338 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) 17.1 Serial Interface Channel 0 Functions Serial interface channel 0 employs the following four modes. • Operation stop mode • 3-wire serial I/O mode • 2-wire serial I/O mode • I 2 C (Inter IC) bus mode Caution Do not switch the oper...

339 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) (4) I 2 C (Inter IC) bus mode (MSB-first) This mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (SCL) and serial data bus (SDA0 or SDA1). This mode is in compliance with the I 2 C bus form...

340 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) 17.2 Serial Interface Channel 0 Configuration Serial interface channel 0 consists of the following hardware. Table 17-2. Serial Interface Channel 0 Configuration Item Configuration Serial I/O shift register 0 (SIO0) Slave address reg...

341 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) Figure 17-2. Serial Interface Channel 0 Block Diagram CSIE0 COI WUP CSIM 04 CSIM 03 CSIM 02 CSIM 01 CSIM 00 Serial Operating Mode Register 0 Control Circuit Output Control Selector SI0/SB0/ SDA0/P25 PM25 Output Control SO0/SB1/ SDA1/...

345 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) 17.3 Serial Interface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0. • Timer clock select register 3 (TCL3) • Serial operating mode register 0 (CSIM0) • Serial bus in...

346 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) Serial Interface Channel 0 Serial Clock Selection Serial Interface Channel 1 Serial Clock Selection TCL33 TCL32 TCL31 TCL30 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 f XX /2 5 f XX /2 6 f XX /2 7 f XX /2 8 f XX ...

348 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) Figure 17-4. Serial Operating Mode Register 0 Format Notes 1. Bit 6 (COI) is a read-only bit. 2. I 2 C bus mode, the clock frequency becomes 1/16 of that output from TO2. 3. Can be used as P25 (CMOS input/output) when used only for t...

350 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) Figure 17-5. Serial Bus Interface Control Register Format (2/2) Notes 1. Setting should be performed before transfer. 2. If 8-clock wait mode is selected, the acknowledge signal at reception time must be output using ACKT. 3. The bus...

351 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) (4) Interrupt timing specify register (SINT) This register sets the bus release interrupt and address mask functions and displays the SCK0/SCL pin level status. SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET...

352 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) Figure 17-6. Interrupt Timing Specify Register Format (2/2) Notes 1. When using wake-up function in the I 2 C mode, set SIC to 1. 2. When CSIE0 = 0, CLD becomes 0. Remark SVA : Slave address register CSIIF0 : Interrupt request flag c...

353 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) 6 5 4 3 2 1 0 7 Symbol CSIM0 CSIE0 COI WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 FF60H 00H R/W Address After Reset R/W CSIE0 0 Serial Interface Channel 0 Operation Control Operation stopped Operation enabled R/W 1 17.4 Serial Interface ...

357 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) 7 6 Internal Bus 1 0 LSB-first MSB-first Read/Write Gate SI0 Serial I/O Shift Register 0 (SIO0) Read/Write Gate SO0 SCK0 D Q SO0 Latch (4) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to st...

360 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) 6 5 4 3 2 1 0 7 Symbol SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT RELT When RELT = 1, SO0 Iatch is set to 1. After SO0 Iatch setting, automatically cleared to 0. Also cleared to 0 when CSIE0 = 0. R/W FF61H 00H R/W Address After Res...

362 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) RELT CMDT SO0 Latch (3) Other signals Figure 17-12 shows RELT and CMDT operations. Figure 17-12. RELT and CMDT Operations (4) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0...

363 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) 17.4.4 I 2 C bus mode operation The I 2 C bus mode is provided for when communication operations are performed between a single master device and multiple slave devices. This mode configures a serial bus that includes only a single m...

364 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) 1-7 8 9 1-7 8 9 1-7 8 9 Address R/W ACK Data ACK Data ACK SCL Start Condition SDA0(SDA1) Stop Condition (1) I 2 C bus mode functions In the I 2 C bus mode, the following functions are available. (a) Automatic identification of serial...

365 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) 2 3 4 5 6 7 A6 A5 A4 A3 A2 A1 A0 R/W Transfer direction specification SCL 8 1 SDA0(SDA1) 1 2 3 4 5 6 7 A6 A5 A4 A3 A2 A1 A0 R/W Address SCL SDA0(SDA1) H SCL SDA0(SDA1) (a) Start condition When the SDA0 (SDA1) pin level is changed fro...

366 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) H SCL SDA0(SDA1) 1 2 3 4 5 6 7 A6 A5 A4 A3 A2 A1 A0 R/W SCL SDA0 (SDA1) 9 8 ACK (d) Acknowledge signal (ACK) The acknowledge signal indicates that the transferred serial data has definitely been received. This signal is used between ...

367 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) (f) Wait signal (WAIT) The wait signal is output by a slave device to inform the master device that the slave device is in wait state due to preparing for transmitting or receiving data. During the wait state, the slave device contin...

369 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) (b) Serial bus interface control register (SBIC) SBIC is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. R/W RELT Use for stop condition output. When RELT = 1, SO0 latch is set to 1. After SO0 l...

370 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) (c) Interrupt timing specification register (SINT) SINT is set by the 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. R/W WAT1 WAT0 Interrupt Control by Wait Note 2 0 0 Interrupt service request is gener...

371 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) (4) Various signals A list of signals in the I 2 C bus mode is given in Table 17-4. Table 17-4. Signals in I 2 C Bus Mode Signal Name Description Start condition Definition : SDA0 (SDA1) falling edge when SCL is high Note 1 Function ...

372 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) (5) Pin configurations The configurations of the serial clock pin SCL and the serial data bus pins SDA0 (SDA1) are shown below. (a) SCL Pin for serial clock input/output dual-function pin. <1> Master ..... N-ch open-drain outpu...

373 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) (7) Error detection In the I 2 C bus mode, transmission error detection can be performed by the following methods because the serial bus SDA0 (SDA1) status during transmission is also taken into the serial I/O shift register 0 (SIO0)...

374 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) Figure 17-22. Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait) (1/3) (a) Start Condition to Address L L L 1 A5 A4 A3 A2 A1 A0 W ACK A6 2 3 4 5 6 7 8 D7 D6 D5 D4 D3 1 2 3 4 5 9 L L L L L SIO0 ← Addr...

377 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) L L L 1 A0 A1 A2 A3 A4 A5 A6 R ACK 2 3 4 5 6 7 8 D6 D7 D5 D4 D3 2 1 3 4 5 9 L L L SIO0 ← Address Master Device Operation Transfer Line SIO0 ← FFH H L L L L L L L H H Write SIO0 COI ACKD CMDD RELD CLD P27 SCL SDA0 WUP BSYE ACKE CMDT R...

380 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) SCL CLC CMDT CLD SDA0(SDA1) 17.4.5 Cautions on use of I 2 C bus mode (1) Start condition output (master) The SCL pin normally outputs a low-level signal when no serial clock is output. It is necessary to change the SCL pin to high in...

381 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) Writing FFH to SIO0 Setting CSIIF0 SettingACKD Serial Reception 9 a 2 3 A0 R ACK D7 D6 D5 P27 output latch 1 Setting CSIIF0 ACK output Serial Transmission Write data to SIO0 P27 outputlatch 0 Wait release Software Operation Hardware ...

383 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) (4) Reception completion of salve In the reception completion processing of the slave, check the bit 3 (CMDD) of the serial bus interface control register (SBIC) and bit 6 (COI) of the serial operation mode register 0 (CSIM0) (when C...

384 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) • Example of program releasing serial transfer status SET1 P2.5; <1> SET1 PM2.5; <2> SET1 PM2.7; <3> CLR1 CSIE0; <4> SET1 CSIE0; <5> SET1 RELT; <6> CLR1 PM2.7; <7> CLR1 P2.5; <8> CLR1 P...

385 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) 17.4.7 SCK0/SCL/P27 pin output manipulation The SCK0/SCL/P27 pin can execute static output via software, in addition to outputting the normal serial clock. The value of serial clocks can also be arbitrarily set by software (the SI0/S...

386 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD78058FY SUBSERIES) CLC (manipulated by bit manipulation instruction) Wait request signalSerial clock (low while transfer is stopped) SCL Figure 17-29. Logic Circuit of SCL Signal Remarks 1. This figure indicates the relation of the signals and does not...

387 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.1 Serial Interface Channel 1 Functions Serial interface channel 1 employs the following three modes. • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function (1) Operation stop mode This mode is used...

388 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.2 Serial Interface Channel 1 Configuration Serial interface channel 1 consists of the following hardware. Table 18-1. Serial Interface Channel 1 Configuration Item Configuration Register Serial I/O shift register 1 (SIO1) Automatic data transmit/receive a...

389 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-1. Serial Interface Channel 1 Block Diagram RE ARLD ERCE ERR TRF STRB BUSY 1 BUSY 0 Internal Bus Automatic DataTransmit/ReceiveControl Register Serial OperatingMode Register 1 ADTI 7 ADTI 4 ADTI 3 ADTI 2 ADTI 1 ADTI 0 5-Bit Counter Serial I/O Shift...

390 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (1) Serial I/O shift register 1 (SIO1) This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO1 is set with an 8-bit memory manipulation ...

391 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.3 Serial Interface Channel 1 Control Registers The following four types of registers are used to control serial interface channel 1. • Timer clock select register 3 (TCL3) • Serial operating mode register 1 (CSIM1) • Automatic data transmit/receive contro...

392 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Serial Interface Channel 1 Serial Clock Selection TCL37 TCL36 TCL35 TCL34 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 f XX /2 f XX /2 2 f XX /2 3 f XX /2 4 f XX /2 5 f XX /2 6 f XX /2 7 f XX /2 8 Setting prohibited f X /2 2 (1.25 MHz) f X...

393 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (2) Serial operating mode register 1 (CSIM1) This register sets serial interface channel 1 serial clock, operating mode, operation enable/stop and automatic transmit/receive operation enable/stop. CSIM1 is set with a 1-bit or 8-bit memory manipulation instru...

394 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (3) Automatic data transmit/receive control register (ADTC) This register sets automatic receive enable/disable, the operating mode, strobe output enable/disable, busy input enable/disable, error check enable/disable and displays automatic transmit/receive e...

395 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Data Transfer Interval Specification (f XX = 5.0 MHz Operation) ADTI4 ADTI3 ADTI2 ADTI1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Minimum Note 2 18.4 s + 0.5/f SCK 31.2 s +...

396 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Data Transfer Interval Specification (f XX = 5.0 MHz Operation) ADTI4 ADTI3 ADTI2 ADTI1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Minimum Note 223.2 s + 0.5/f SCK 236.0 s +...

399 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Operation enable 6 5 4 3 2 1 0 7 Symbol CSIM1 CSIE1 DIR ATE 0 0 0 CSIM11 CSIM10 SCK1 (Input) CSIE1 0 FF68H 00H R/W Address After Reset R/W CSIM11 P20 PM21 P21 PM22 Note 2 Shift Register 1 Operation Serial Clock Counter Operation Control SI1/P20 Pin Function ...

401 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/ reception is carried out in synchronization with the serial clock. Shift operation of the serial I/O shift register 1 (...

406 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (c) Automatic data transmit/receive interval specify register (ADTI) This register sets the automatic data transmit/receive function data transfer interval. ADTI is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTI to 00H. Note...

410 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (2) Automatic transmit/receive data setting (a) Transmit data setting <1> Write transmit data from the least significant address FAC0H of internal buffer RAM (up to FADFH at maximum). The transmit data should be in the order from high-order address to ...

411 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 SCK1 SO1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 CSIIF1 TRF SI1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Interval (3) Communication operation (a) Basic transmission/reception mode This transmission/reception mode is the same as the 3-wire seri...

412 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-9. Basic Transmission/Reception Mode Flowchart ADTP: Automatic data transmit/receive address pointer ADTI: Automatic data transmit/receive interval specify register SIO1: Serial I/O shift register 1 TRF: Bit 3 of automatic data transmit/receive con...

413 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission/reception (ARLD = 0, RE = 1) in basic transmit/receive mode, internal buffer RAM operates as follows. (i) Before transmission/reception (See Figure 18-10 (a).) After any data has been written to serial I/O shift register 1 (SIO1) (star...

415 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (b) Basic transmission mode In this mode, the specified number of 8-bit unit data are transmitted. Serial transmission is started by writing the desired data to serial I/O shift register 1 (SIO1) when bit 7 (CSIE1) of serial operation mode register 1 (CSIM1)...

416 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-12. Basic Transmission Mode Flowchart ADTP: Automatic data transmit/receive address pointer ADTI: Automatic data transmit/receive interval specify register SIO1: Serial I/O shift register 1 TRF: Bit 3 of automatic data transmit/receive control regi...

417 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) Transmit data 4 (T4) Transmit data 5 (T5) Transmit data 6 (T6) FADFH FAC5H FAC0H SIO1 0 CSIIF1 5 ADTP –1 In 6-byte transmission (ARLD=0, RE=0) in basic transmit mode, internal buffer RAM operates...

419 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (c) Repeat transmission mode In this mode, data stored in the internal buffer RAM is transmitted repeatedly. Serial transmission is started by writing the desired data to serial I/O shift register 1 (SIO1) when bit 7 (CSIE1) of serial operation mode register...

420 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-15. Repeat Transmission Mode Flowchart ADTP: Automatic data transmit/receive address pointer ADTI: Automatic data transmit/receive interval specify register SIO1: Serial I/O shift register 1 Start Write transmit data in internal buffer RAM Set ADTP...

421 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission (ARLD = 1, RE = 0) in repeat transmit mode, internal buffer RAM operates as follows. (i) Before transmission (See Figure 18-16 (a).) After any data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not...

423 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 SCK1 SO1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SI1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Restart CommandCSIE1 = 1, Write to SIO1 Suspend CSIE1 = 0 (Suspended Command) (d) Automatic transmission/reception suspending and restart Automatic t...

424 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (4) Synchronization control Busy control and strobe control are functions for synchronizing sending and receiving between the master device and slave device. By using these functions, it is possible to detect bit slippage during sending and receiving. (a) Bu...

425 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Furthermore, in the case that the busy control option is used, select the internal clock for the serial clock. The busy signal cannot be controlled with an external clock. The operation timing when the busy control option is used is shown in Figure 18-19. Ca...

426 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-20 Busy Signal and Wait Cancel (When BUSY0 = 0) (b) Busy & strobe control option Strobe control is a function for synchronizing the sending and receiving of data between a master device and slave device. When sending or receiving of 8 bit data ...

427 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 SCK1 SO1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 STB BUSY SI1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 TRF Busy Input Valid Busy Input Release CSIIF1 Figure 18-21. Operation Timings When Using Busy & Strobe Control Option (BUSY0 = 0) Cauti...

428 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (c) Bit Slippage Detection Function Through the Busy Signal During an auto send and receive operation, noise occur in the serial clock signal output by the master device and bit slippage may occur in the slave device side serial clock. At this time, if the s...

429 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (5) Automatic transmit/receive interval time When using the automatic transmit/receive function, the read/write operations from/to the internal buffer RAM are performed after transmitting/receiving one byte. Therefore, an interval is inserted before the next...

430 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 f X f CPU SCK1 SO1 SI1 T CPU T SCK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Interval (a) When the automatic transmit/receive function is used by the internal clock If bit 1 (CSIM11) of serial operation mode register 1 (CSIM1) is set at (1), the intern...

433 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.1 Serial Interface Channel 2 Functions Serial interface channel 2 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial transfer is n...

434 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.2 Serial Interface Channel 2 Configuration Serial interface channel 2 consists of the following hardware. Table 19-1. Serial Interface Channel 2 Configuration Item Configuration Register Transmit shift register (TXS) Receive shift register (RXS) Receive b...

435 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Internal Bus Asynchronous Serial Interface Mode Register AsynchronousSerial InterfaceStatus Register Receive Buffer Register (RXB/SIO2) Direction Control Circuit Receive Shift Register (RXS) Reception Control Circuit RxD/SI2/ P70 TxD/SO2/ P71 INTSR/INTCSI2 C...

436 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 TPS3 TPS2 TPS1 TPS0 Internal Bus MDL3 MDL2 MDL1 MDL0 Baud Rate Generator Control Register 4 TXE CSIE2 5-Bit Counter Selector Selector Decoder 1/2 Selector Transmit Clock 1/2 Selector Receive Clock Match Match MDL0 to MDL3 5-Bit Counter RXE Start Bit Detectio...

437 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (1) Transmit shift register (TXS) This register is used to set the transmit data. The data written in TXS is transmitted as serial data. If the data length is specified as 7 bits, bits 0 to 6 of the data written in TXS are transferred as transmit data. Writi...

438 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 6 5 4 3 2 1 0 7 Symbol CSIM2 CSIE2 0 0 0 0 CSIM 22 CSCK 0 FF72H 00H R/W Address After Reset R/W CSCK 0 1 Serial Operating Mode Selection UART mode 3-wire serial I/O mode CSIM22 0 1 First Bit Specification MSB LSB CSIE2 0 1 Operation Control in 3-wire Serial ...

439 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 6 5 4 3 2 1 0 7 Symbol ASIM TXE RXE PS1 PS0 CL SL ISRM SCK FF70H 00H R/W Address After Reset R/W SCK 0 1 Clock Selection in Asynchronous Serial InterfaceMode Input clock from off-chip to ASCK pin Dedicated baud rate generator output Note ISRM 0 1 Control of ...

440 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (2) 3-wire Serial I/O Mode Table 19-2. Serial Interface Channel 2 Operating Mode Settings (1) Operation Stop Mode P72/SCK2/ASCK Pin Functions P71/SO2/TxD Pin Functions P70/SI2/RxD Pin Functions Shift Clock Start Bit TXE RXE SCK CSIE2 CSIM22 CSCK PM70 P70 PM7...

441 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 PE 6 5 4 3 2 1 0 7 Symbol ASIS 0 0 0 0 0 FE OVE FF71H 00H R Address After Reset R/W OVE 0 1 Overrun Error Flag Overrun error not generated Overrun error generated Note 1 (When next receive operation is completed beforedata from receive buffer register is rea...

442 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Baud Rate Generator Input Clock Selection MDL3 MDL2 MDL1 MDL0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 f SCK /16 f SCK /17 f SCK /18 f SCK /19 f SCK /20 f SCK /21 f SCK /2...

444 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin. (a) Generation of baud rate transmit/receive clock by means of main system clock The transmit/rece...

445 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is obtained with ...

446 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.4 Serial Interface Channel 2 Operation Serial interface channel 2 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode 19.4.1 Operation stop mode In the operation stop mode, serial trans...

448 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 6 5 4 3 2 1 0 7 Symbol CSIM2 CSIE2 0 0 0 0 CSIM 22 CSCK 0 CSCK 0 1 Serial Operating Mode Selection UART mode 3-wire serial I/O mode CSIM22 0 1 First Bit Specification MSB LSB CSIE2 0 1 Operation Control in 3-wire Serial I/O Mode Operation stopped Operation e...

450 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 PE 6 5 4 3 2 1 0 7 Symbol ASIS 0 0 0 0 0 FE OVE FF71H 00H R Address After Reset R/W OVE 0 1 Overrun Error Flag Overrun error not generated Overrun error generated Note 1 (When next receive operation is completed beforedata from receive buffer register is rea...

453 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin. (i) Generation of baud rate transmit/receive clock by means of main system clock The transmit/rece...

455 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (2) Communication operation (a) Data format The transmit/receive data format is as shown in Figure 19-7. Figure 19-7. Asynchronous Serial Interface Transmit/Receive Data Format 1 data frame is composed of each of the bits shown below. • Start bits .............

456 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd number) erro...

457 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 D1 D2 D6 D7 Parity D0 TxD (Output) INTST STOP START D1 D2 D6 D7 Parity D0 TxD (Output) INTST STOP START (c) Transmission A transmit operation is started by writing transmit data to the transmit shift register (TXS). The start bit, parity bit and stop bit(s) ...

458 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (d) Reception When bit 6 (RXE) of the asynchronous serial interface mode register (ASIM) is set (1), a receive operation is enabled and sampling of the RxD pin input is performed. RxD pin input sampling is performed using the serial clock specified by ASIM. ...

460 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (3) UART mode cautions (a) If bit 7 (TXE) of the asynchronous serial interface mode register (ASIM) is cleared to (0) during transmission and sending operation is halt, be sure to set the transmit shift register (TXS) to FFH, then set TXE to 1 before executi...

466 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 SI2 SCK2 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO2 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SRIF Transfer Start at the Falling Edge of SCK2 End of Transfer (2) Communication operation In the 3-wire serial I/O mode, data transmission/reception is performed i...

467 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (3) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 19-13 shows the configuration of the transmit shift register (TXS/SIO2) and internal bus. As shown in the figure, MSB/LSB can be rea...

468 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.4.4 Restrictions on using UART mode In the UART mode, a receive completion interrupt request (INTSR) is generated after a certain period of time following the generation and clearing of the receive error interrupt request (INTSER). Thereby, the phenomenon...

469 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 RxD (Input) INTSR INTSER (when Framing orOverrun Error is Generated) INTSER (when Parity Erroris Generated) D0 T1 T2 D1 D2 D6 D7 STOP START Parity Figure 19-15. Period that Reading Receive Buffer Register Is Prohibited T1 : The amount of time for one unit of...

470 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 [Example] INTSER is Generated 7 Clocks (MIN.) of CPU Clock(Time from Interrupt Request to Servicing) Instructions for2205 clocks (MIN.)of CPU clock arerequired. UART Receive Error Interrupt (INTSER) Servicing EI RETI MOV A,RXB Main Processing

471 CHAPTER 20 REAL-TIME OUTPUT PORT 20.1 Real-Time Output Port Functions Data set previously in the real-time output buffer register can be transferred to the output latch by hardware concurrently with timer interrupt request or external interrupt request generation, then output externally. This is...

472 CHAPTER 20 REAL-TIME OUTPUT PORT 20.2 Real-Time Output Port Configuration The real-time output port consists of the following hardware. Table 20-1. Real-time Output Port Configuration Item Configuration Register Real-time output buffer register (RTBL, RTBH) Control register Port mode register 12...

474 CHAPTER 20 REAL-TIME OUTPUT PORT 20.3 Real-Time Output Port Control Registers The following three registers control the real-time output port. • Port mode register 12 (PM12) • Real-time output port mode register (RTPM) • Real-time output port control register (RTPC) (1) Port mode register 12 (PM...

475 CHAPTER 20 REAL-TIME OUTPUT PORT (3) Real-time output port control register (RTPC) This register sets the real-time output port operating mode and output trigger. Table 20-3 shows the relation between the operating mode of the real-time output port and output trigger. RTPC is set with a 1-bit or...

477 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.1 Interrupt Function Types The following three types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally even in the interrupt disabled status. It does not undergo interrupt priority control and is ...

478 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 0 – INTWDT 21.2 Interrupt Sources and Configuration Combining all the factors in interrupts, non-maskable interrupts, maskable interrupts and software interrupts, there are a total of 22 source (see Table 21-1). Table 21-1. Interrupt Source List (1/2) Inte...

482 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.3 Interrupt Function Control Registers The following six types of registers are used to control the interrupt functions. • Interrupt request flag register (IF0L, IF0H, IF1L) • Interrupt mask flag register (MK0L, MK0H, MK1L) • Priority specify flag regis...

483 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 7 PIF6 Symbol IF0L 6 PIF5 5 PIF4 4 PIF3 3 PIF2 2 PIF1 1 PIF0 0 TMIF4 Address FFE0H 00H After Reset R/W R/W × × IF × 0 1 Interrupt Request Flag No interrupt request signal Interrupt request signal is generated; Interrupt request state 7 TMIF01 IF0H 6 TMIF00...

484 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 7 PMK6 Symbol MK0L 6 PMK5 5 PMK4 4 PMK3 3 PMK2 2 PMK 1 PMK 0 TMMK4 Address FFE4H FFH After Reset R/W R/W × × MK × 0 1 Interrupt Servicing Control Interrupt servicing enabled Interrupt servicing disabled 7 TMMK01 MK0H 6 TMMK00 5 TMMK3 4 STMK 3 SRMK 2 SERMK ...

485 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 7 PPR6 Symbol PR0L 6 PPR5 5 PPR4 4 PPR3 3 PPR2 2 PPR1 1 PPR0 0 TMPR4 Address FFE8H FFH After Reset R/W R/W 0 1 Priority Level Selection High priority level Low priority level 7 TMPR01 PR0H 6 TMPR00 5 TMPR3 4 STPR 3 SRPR 2 SERPR 1 CSIPR1 0 CSIPR0 7 1 PR1L 6...

486 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Address FFECH 00H After Reset R/W R/W 0 0 1 1 INTP0 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES11 7 ES31 Symbol INTM0 6 ES30 5 ES21 4 ES20 3 ES11 2 ES10 1 0 0 0 0 1 0 1 ES10 0 0 1 1 INTP1 Valid Edge Sel...

487 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Address FFEDH 00H After Reset R/W R/W 0 0 1 1 INTP3 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES41 7 ES71 Symbol INTM1 6 ES70 5 ES61 4 ES60 3 ES51 2 ES50 1 ES41 0 ES40 0 1 0 1 ES40 0 0 1 1 INTP4 Valid Ed...

489 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (b) When input is equal to or twice the sampling cycle (t SMP ) The noise elimination circuit sets the interrupt request flag (PIF0) at (1) when the sampled INTP0 input level is active twice in succession. Figure 21-8 shows the input/output timing of the n...

490 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (6) Program status word (PSW) The program status word is a register to hold the instruction execution result and the current status for interrupt request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control multiple interrupt p...

491 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4 Interrupt Servicing Operations 21.4.1 Non-maskable interrupt acknowledge operation A non-maskable interrupt request is received without condition even when in the interrupt request reception prohibited state. It does not undergo interrupt priority con...

492 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS WDTM4=1 (with watchdog timer mode selected)? Overflow in WDT? WDTM3=0 (with non-maskable interrupt selected)? Interrupt request generation WDT interrupt servicing? Interrupt control register unaccessed? Interrupt service start Interrupt request held pendin...

493 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-12. Non-Maskable Interrupt Request Acknowledge Operation (a) If a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution (b) If two non-maskable interrupt requests are generated during non-maskab...

494 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4.2 Maskable Interrupt request reception For a maskable interrupt request, the interrupt request flag is set at (1) and if the mask (MK) flag of that interrupt is cleared (0), it is possible for it to be received. A vector interrupt request is received ...

495 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-13. Interrupt Request Acknowledge Processing Algorithm XXIF : Interrupt Request Flag XXMK : Interrupt Mask Flag XXPR : Priority Order Specification Flag IE : Flag which controls reception of maskable interrupt requests (1 = permitted, 0 = prohibi...

497 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4.3 Software interrupt request acknowledge operation A software interrupt request is received by the execution of a BRK command. A software interrupt cannot be prohibited. If a software interrupt request is received, the contents of the program status w...

498 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Table 21-4. Interrupt Request Enabled for Multiple Interrupt During Interrupt Servicing Maskable Interrupt Request PR = 0 PR = 1 IE = 1 IE = 0 IE = 1 IE = 0 Non-maskable interrupt D D D D D ISP=0 E E D D D ISP=1 E E D E D Software interrupt E E D E D Remar...

499 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Main Processing EI INTxx(PR=1) INTyy(PR=0) IE=0 EI RETI INTxxServicing INTzz(PR=0) IE=0 EI RETI INTyyServicing IE=0 RETI INTzzServicing Figure 21-16. Multiple Interrupt Example (1/2) Example 1 Example of multiple interrupt requests being generated twice. D...

500 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Main Processing INTxxServicing INTyyServicing INTxx(PR=0) 1 InstructionExecution IE=0 INTyy(PR=0) IE=0 RETI RETI EI Example 3 Example of a multiple interrupt not being generated because an interrupt was not permitted. In processing of interrupt INTxx, inte...

501 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4.5 Interrupt request reserve Among the commands, there are some for which, even if an interrupt request is generated while they are being executed, reception of the interrupt request is held until execution of the next command is completed. The command...

502 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Internal bus MK IF Test input signal Standbyrelease signal 21.5 Test Functions When a clock timer overflow occurs and when the port 4 falling edge is detected, a corresponding test input flag is set (1) and a standby release signal is generated. Unlike the...

503 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (1) Interrupt request flag register 1L (IF1L) It indicates whether a watch timer overflow is detected or not. It is set by a 1-bit memory manipulation instruction and 8-bit memory manipulation instruction. It is set to 00H by the RESET signal input. Figure...

504 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 7 0 Symbol KRM 6 0 5 0 4 0 3 0 2 0 1 KRMK 0 KRIF Address FFF6H 02H After Reset R/W R/W 0 1 Key Return Signal Not detected Detected (port 4 falling edge detection) KRIF 0 1 Standby Mode Control by Key Return Signal Standby mode release enabled Standby mode ...

505 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 22.1 External Device Expansion Functions The external device expansion functions connect external devices to areas other than the internal ROM, RAM, and SFR. Connection of external devices uses ports 4 to 6. Ports 4 to 6 control address/data, read/wr...

506 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Memory maps when using the external device expansion function are as follows. Figure 22-1. Memory Map When Using External Device Expansion Function (1/2) (a) Memory Map of the µ PD78056F and 78056FY, and of the µ PD78P058F and 78P058FY when the inter...

507 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION FFFFH SFR Internal High-Speed RAM F F 0 0 HF E F F H F B 0 0 HF A F F H FAE0HFADFH FAC0HFABFH F 8 0 0 HF 7 F F H F 4 0 0 HF 3 F F H F 0 0 0 HE F F F H 0 0 0 0 H Reserved Internal Buffer RAM Reserved Internal Expansion RAM Reserved Single-chip Mode FF...

508 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 7 0 Symbol MM 6 0 5 PW1 4 PW0 3 0 2 MM2 1 MM1 0 MM0 Address FFF8H 10H After Reset R/W R/W MM2 MM1 MM0 Single-chip/Memory ExpansionMode Selection P40 to P47, P50 to P57, P64 to P67 Pin state P40 to P47 P50 to P53 P54, P55 P56, P57 P64 to P67 0 0 0 0 0...

509 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION (2) Memory size switching register (IMS) This register specifies the internal memory size. In principle, use IMS in a default status. However, when using the external device expansion function with the µ PD78058F, 78P058F, 78058FY and 78P058FY, set I...

510 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 22.3 External Device Expansion Function Timing Timing control signal output pins in the external memory expansion mode are as follows. (1) RD pin (Alternate function: P64) Read strobe signal output pin. The read strobe signal is output in data access...

511 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION ASTB RD Lower Address Operation Code AD0 to AD7 A8 to A15 Higher Address WAIT ASTB RD AD0 to AD7 A8 to A15 Lower Address Operation Code Higher Address Internal Wait Signal (1-clock wait) ASTB RD AD0 to AD7 A8 to A15 Lower Address Operation Code Highe...

512 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION ASTB RD Lower Address Read Data AD0 to AD7 A8 to A15 Higher Address WAIT ASTB RD AD0 to AD7 A8 to A15 Lower Address Read Data Higher Address Internal Wait Signal (1-clock wait) Higher Address ASTB RD AD0 to AD7 A8 to A15 Lower Address Read Data Figur...

513 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION ASTB WR Higher Address AD0 to AD7 A8 to A15 WAIT Hi-Z Lower Address Write Data ASTB WR AD0 to AD7 A8 to A15 Lower Address Write Data Higher Address Internal Wait Signal (1-clock wait) Hi-Z ASTB WR AD0 to AD7 A8 to A15 Lower Address Write Data Hi-Z Hi...

514 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION ASTB RD WR Higher Address AD0 to AD7 A8 to A15 WAIT Hi-Z Lower Address Write Data Read Data Lower Address Higher Address Internal Wait Signal (1-clock wait) Hi-Z ASTB RD WR AD0 to AD7 A8 to A15 Write Data Read Data ASTB RD WR AD0 to AD7 A8 to A15 Low...

515 CHAPTER 23 STANDBY FUNCTION 23.1 Standby Function and Configuration 23.1.1 Standby function The standby function is designed to decrease power consumption of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. The HALT mode is intended ...

516 CHAPTER 23 STANDBY FUNCTION STOP Mode Clear X1 PinVoltageWaveform V SS a 23.1.2 Standby function control register A wait time after the STOP mode is cleared upon interrupt request till the oscillation stabilizes is controlled with the oscillation stabilization time select register (OSTS). OSTS i...

517 CHAPTER 23 STANDBY FUNCTION 23.2 Standby Function Operations 23.2.1 HALT mode (1) HALT mode set and operating status The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the subsystem clock. The operating status in the HALT mode is described below. ...

518 CHAPTER 23 STANDBY FUNCTION HALTInstruction InterruptRequest Wait StandbyRelease Signal OperatingMode Clock HALT Mode Wait Oscillation Operating Mode (2) HALT mode clear The HALT mode can be cleared with the following four types of sources. (a) Clear upon unmasked interrupt request The HALT mode...

519 CHAPTER 23 STANDBY FUNCTION (d) Clear upon RESET input The HALT mode is cleared upon RESET signal input. As is the case with normal reset operation, a program is executed after branching to the reset vector address. Figure 23-3. HALT Mode Release by RESET Input Remarks 1. f X : main system clock...

520 CHAPTER 23 STANDBY FUNCTION 23.2.2 STOP mode (1) STOP mode set and operating status The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock. Cautions 1. When the STOP mode is set, the X2 pin is internally connected to V DD via a pull-up resistor to m...

521 CHAPTER 23 STANDBY FUNCTION STOPInstruction Wait (Time set by OSTS) Oscillation Stabilization Wait Status OperatingMode Oscillation OperationgMode STOP Mode Oscillation Stop Oscillation StandbyRelease Signal Clock InterruptRequest (2) STOP mode release The STOP mode can be cleared with the follo...

522 CHAPTER 23 STANDBY FUNCTION RESETSignal OperatingMode Clock ResetPeriod STOP Mode Oscillation Stop Oscillation StabilizationWait Status OperatingMode Oscillation Wait (2 17 /f x : 26.2 ms) STOPInstruction Oscillation (c) Release by RESET input The STOP mode is cleared upon RESET input, and after...

523 RESET Count Clock Reset Control Circuit Watchdog Timer Stop Over-flow ResetSignal InterruptFunction CHAPTER 24 RESET FUNCTION 24.1 Reset Function The following two operations are available to generate the reset signal. (1) External reset input with RESET pin (2) Internal reset by watchdog timer ...

524 CHAPTER 24 RESET FUNCTION RESET InternalReset Signal Port Pin Delay Delay Hi-Z X1 Normal Operation Reset Period(Oscillation Stop) OscillationStabilizationTime Wait Normal Operation(Reset Processing) Stop Status(Oscillation Stop) STOP Instruction Execution RESET InternalReset Signal Port Pin Dela...

525 CHAPTER 24 RESET FUNCTION Table 24-1. Hardware Status After Reset (1/2) Hardware Status after Reset Program counter (PC) Note 1 The contents of reset vector tables (0000H and 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) 02H RAM Data memory Undefined Note 2 General regis...

527 Match CORENn CORSTn Program counter (PC) Comparator Correction address register n (CORADn) Internal bus Correction control register Correction branch requestsignal (BR !7FDH) CHAPTER 25 ROM CORRECTION 25.1 ROM Correction Functions The µ PD78058F, 78058FY Subseries can replace part of a program i...

528 CHAPTER 25 ROM CORRECTION FF3AH/FF3BH 0000H Symbol 15 CORAD0 0 Address FF38H/FF39H After Reset 0000H R/W R/W CORAD1 R/W (1) Correction address registers 0 and 1 (CORAD0, CORAD1) These registers set the start address (correction address) of the instruction(s) to be corrected in the mask ROM. The ...

529 CHAPTER 25 ROM CORRECTION 7 0 6 0 5 0 4 0 COREN1 CORST1 COREN0 CORST0 Symbol CORCN Address FF8AH After Reset COREN0 0 1 CORST0 0 1 COREN1 0 1 CORST1 0 1 R/W R/W Note 00H Correction address register 0 and fetch address match detection Not detected Detected Correction address register 0 and fetch ...

530 CHAPTER 25 ROM CORRECTION 25.4 ROM Correction Application (1) Store the correction address and instruction after correction (patch program) to nonvolatile memory (such as EEPROM TM ) outside the microcontroller. When two places should be corrected, store the branch destination judgment program a...

531 CHAPTER 25 ROM CORRECTION No Yes Initialization Load the contents of external nonvolatile memoryinto internal expansion RAMCorrection address register settingROM correction enabled Is ROM correction used ? Note ROM correction Main program (2) Assemble in advance the initialization routine as sho...

533 CHAPTER 25 ROM CORRECTION ADD A, #2 BR !1002H BR !F702H ADD A, #1 MOV B, A 0000H 0080H Program start 1000H 1002H Internal ROM Internal Expansion RAM F400H F702H F7FDH F7FFH (1) (2) (3) EFFFH 25.5 ROM Correction Example The example of ROM correction when the instruction at address 1000H “ADD A, #...

534 CHAPTER 25 ROM CORRECTION Correction Place Internal ROM Internal ROM JUMP FFFFH F7FFH F7FDH xxxxH 0000H (1) (2) (3) BR !JUMP Correction Program 25.6 Program Execution Flow Figures 25-9 and 25-10 show the program transition diagrams when the ROM correction is used. Figure 25-9. Program Transition...

535 CHAPTER 25 ROM CORRECTION Internal ROM Correction Place 1 Internal ROM JUMP Internal ROM (1) (2) (3) (4) (5) (6) (7) (8) FFFFH F7FFH F7FDH yyyyH xxxxH 0000H BR !JUMP Destination judge program Correction program 2 Correction program 1 Correction Place 2 Figure 25-10. Program Transition Diagram (W...

536 CHAPTER 25 ROM CORRECTION 25.7 Cautions on ROM Correction (1) Address values set in correction address registers 0 and 1 (CORAD0 and CORAD1) must be addresses where instruction codes are stored. (2) Correction address registers 0 and 1 (CORAD0 and CORAD1) should be set when the correction enable...

537 CHAPTER 26 µ PD78P058F, 78P058FY The µ PD78P058F and 78P058FY are products which have one time PROM incorporated into them, which it is only possible to write to once. The differences between PROM products ( µ PD78P058F and 78P058FY) and ROM products ( µ PD78056F, 78056FY, 78058F and 78058FY) ar...

538 CHAPTER 26 µ PD78P058F, 78P058FY 26.1 Memory Size Switching Register In the µ PD78P058F and 78P058FY, internal memory can be selected through the memory size select register (IMS). The same memory mapping as that of mask ROM versions that have a different internal memory can be done by setting I...

539 CHAPTER 26 µ PD78P058F, 78P058FY 7 0 Symbol IXS 6 0 5 0 4 0 3 IXRAM3 2 IXRAM2 1 IXRAM1 0 IXRAM0 Address FFF4H 0AH After Reset Internal Extension RAM Capacity Selection IXRAM3 IXRAM2 IXRAM1 1024 bytes 1 0 1 Setting prohibited Other than above IXRAM0 0 R/W W 0 bytes 1 1 0 0 26.2 Internal Expansion...

540 CHAPTER 26 µ PD78P058F, 78P058FY Program inhibit High impedance 26.3 PROM Programming The µ PD78P058F and 78P058FY include on-chip PROM in a 60 Kbyte configuration as program memory. To write a program into the µ PD78P058F or 78P058FY PROM, make the device enter the PROM programming mode by sett...

542 CHAPTER 26 µ PD78P058F, 78P058FY 26.3.2 PROM write procedure Figure 26-3. Page Program Mode Flowchart Start Address = G V DD = 6.5 V, V PP = 12.5 V X = 0 Latch Address = Address + 1 Latch Address = Address + 1 Latch Address = Address + 1 Latch X = X + 1 0.1-ms program pulse Verify 4 Bytes Pass A...

544 CHAPTER 26 µ PD78P058F, 78P058FY Figure 26-5. Byte Program Mode Flowchart Start Address = G V DD = 6.5 V, V PP = 12.5 V X = 0 X = X + 1 0.1-ms program pulse Verify Address = N? V DD = 4.5 to 5.5 V, V PP = V DD All bytes verified? End of write Fail Fail Pass Yes All Pass No Pass Defective product...

545 CHAPTER 26 µ PD78P058F, 78P058FY A0 to A16 D0 to D7 Program Program Verify Data Input Data Output V PP V DD V DD +1.5 V DD V IH V IL V IH V IL V IH V IL V PP V DD CE PGM OE Figure 26-6. Byte Program Mode Timing Cautions 1. Be sure to apply V DD before applying V PP , and remove it after removing...

546 CHAPTER 26 µ PD78P058F, 78P058FY Address Input A0 to A16 CE (Input) OE (Input) D0-D7 Hi-Z Data Output Hi-Z 26.3.3 PROM read procedure PROM contents can be read onto the external data bus (D0 to D7) using the following procedure. (1) Fix the RESET pin low, and supply +5 V to the V PP pin. Unused ...

547 CHAPTER 26 µ PD78P058F, 78P058FY 26.4 Screening of One-Time PROM Versions One-time PROM versions cannot be fully tested by NEC before shipment due to the structure of one-time PROM. Therefore, after users have written data into the PROM, screening should be implemented by user: that is, store de...

549 CHAPTER 27 INSTRUCTION SET This chapter describes each instruction set of the µ PD78058F and 78058FY Subseries as list table. For details of its operation and operation code, refer to the separate document 78K/0 Series USER’S MANUAL—Instructions (U12326E).

550 CHAPTER 27 INSTRUCTION SET 27.1 Legends Used in Operation List 27.1.1 Operand identifiers and description methods Operands are described in “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications ...

551 CHAPTER 27 INSTRUCTION SET 27.1.2 Description of “operation” column A : A register; 8-bit accumulator X : X register B : B register C : C register D : D register E : E register H : H register L : L register AX : AX register pair; 16-bit accumulator BC : BC register pair DE : DE register pair HL ...

552 CHAPTER 27 INSTRUCTION SET 27.2 Operation List Clock Flag Note 1 Note 2 Z AC CY r, #byte 2 4 – r ← byte saddr, #byte 3 6 7 (saddr) ← byte sfr, #byte 3 – 7 sfr ← byte A, r Note 3 1 2 – A ← r r, A Note 3 1 2 – r ← A A, saddr 2 4 5 A ← (saddr) saddr, A 2 4 5 (saddr) ← A A, sfr 2 – 5 A ← sfr sfr, A ...

553 CHAPTER 27 INSTRUCTION SET Clock Flag Note 1 Note 2 Z AC CY rp, #word 3 6 – rp ← word saddrp, #word 4 8 10 (saddrp) ← word sfrp, #word 4 – 10 sfrp ← word AX, saddrp 2 6 8 AX ← (saddrp) saddrp, AX 2 6 8 (saddrp) ← AX MOVW AX, sfrp 2 – 8 AX ← sfrp sfrp, AX 2 – 8 sfrp ← AX AX, rp Note 3 1 4 – AX ← ...

554 CHAPTER 27 INSTRUCTION SET Clock Flag Note 1 Note 2 Z AC CY A, #byte 2 4 – A, CY ← A – byte × × × saddr, #byte 3 6 8 (saddr), CY ← (saddr) – byte × × × A, r Note 3 2 4 – A, CY ← A – r × × × r, A 2 4 – r, CY ← r – A × × × A, saddr 2 4 5 A, CY ← A – (saddr) × × × A, !addr16 3 8 9 + n A, CY ← A – (...

555 CHAPTER 27 INSTRUCTION SET Clock Flag Note 1 Note 2 Z AC CY A, #byte 2 4 – A ← A byte × saddr, #byte 3 6 8 (saddr) ← (saddr) byte × A, r Note 3 2 4 – A ← A r × r, A 2 4 – r ← r A × A, saddr 2 4 5 A ← A (saddr) × A, !addr16 3 8 9 + n A ← A (addr16) × A, [HL] 1 4 5 + n A ← A (HL) × A, [HL + byte] ...

560 CHAPTER 27 INSTRUCTION SET 27.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ

565 APPENDIX A. DIFFERENCES AMONG µ PD78054, 78058F, AND 780058 SUBSERIES The major differences among the µ PD78054, 78058F, and 780058 Subseries are shown in Table A-1. Table A-1. Major Differences Among µ PD78054, 78058F, and 780058 Subseries (1/2) Product Name µ PD78054 Subseries µ PD78058F Subse...

567 APPENDIX B DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the µ PD78058F and 78058FY Subseries. Figure B-1 shows the configuration of the development tools.

570 APPENDIX B DEVELOPMENT TOOLS B.1 Language Processing Software RA78K/0 Program that converts program written in mnemonic into object codes that Assembler package can be executed by microcontroller.In addition, automatic functions to generate symbol table and optimizebranch instructions are also p...

571 APPENDIX B DEVELOPMENT TOOLS B.2 PROM Programming Tool B.2.1 Hardware PG-1500 This is a PROM programmer capable of programming the single-chip microcontroller with on-chip PROM programmer PROM by manipulating from the stand-alone or host machine through connection of the separately available pro...

572 APPENDIX B DEVELOPMENT TOOLS B.3 Debugging Tool B.3.1 Hardware (1/2) (1) When using in-circuit emulator IE-78K0-NS IE-78K0-NS Note The in-circuit emulator serves to debug hardware and software when In-circuit emulator developing application systems using a 78K/0 Series product. It corresponds to...

576 APPENDIX B DEVELOPMENT TOOLS B.4 OS for IBM PC The following OSs for the IBM PC are supported. Table B-1. OS for IBM PC OS Version PC DOS Ver. 5.02 to Ver. 6.3 J6.1/V Note to J6.3/V Note IBM DOS TM J5.02/V Note MS-DOS Ver. 5.0 to Ver. 6.22 5.0/V Note to 6.2/V Note Note Only English mode is suppo...

578 APPENDIX B DEVELOPMENT TOOLS Figure B-3. EV-9200GC-80 Footprints (For Reference Only) F E D G H I J K L C B A 0.026 × 0.748=0.486 0.026 × 0.748=0.486 EV-9200GC-80-P1 I T E M M I L L I M E T E R S I N C H E S A B C D E F G H I J K L 1 9 . 7 1 5 . 0 1 5 . 0 1 9 . 7 6 . 0 ± 0 . 0 5 6 . 0 ± 0 . 0 5 ...

579 APPENDIX B DEVELOPMENT TOOLS Drawing of Conversion Adapter (TGK-080SDW) Figure B-4. TGK-080SDW Drawings (For Reference) (unit: mm) I T E M M I L L I M E T E R S I N C H E S b 0 . 2 5 0 . 0 1 0 c 5 . 3 0 . 2 0 9 a 0.5x19=9.5±0.10 0.020x0.748=0.374±0.004 d 5 . 3 0 . 2 0 9 h 1 . 8 5 ± 0 . 2 0 . 0 7...

581 APPENDIX C EMBEDDED SOFTWARE This chapter describes the embedded software that is available for the µ PD78058F and 78058FY Subseries to allow users to develop and maintain application programs for these subseries.

582 APPENDIX C EMBEDDED SOFTWARE C.1 Real-time OS (1/2) RX78K/0 RX78K/0 is real-time OS conforming to µ ITRON specifications. Real-time OS Tool (configurator) that generates nucleus of RX78K/0 and plural information tables is supplied. Used in combination with an optional assembler package (RA78K/0)...

583 APPENDIX C EMBEDDED SOFTWARE Real-time OS (2/2) MX78K0 µ ITRON-specification subset OS. Nucleus of MX78K0 is supplied. OS This OS performs task management, event management, and time management. It controls the task execution sequence for task management and selects the task to be executed next....

585 APPENDIX D REGISTER INDEX D.1 Register Index (Register Name) [A] A/D conversion result register (ADCR) ............................................................................................................. 264 A/D converter input select register (ADIS) .......................................

586 APPENDIX D REGISTER INDEX Interrupt request flag register 1L (IF1L) ................................................................................................... 483, 503 Interrupt timing specify register (SINT) ........................................................................... 29...

591 APPENDIX E REVISION HISTORY Major revisions by edition and revised chapters are shown below. Edition Major Revisions from Previous Edition Revised Chapters 2nd The following products have already been developed: Throughout µ PD78056GC- ××× -8BT, 78058FGC- ××× -8BT, 78P058FGC-8BT, 78056FYGC- ××× ...

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