Page 3 - support systems or medical equipment for life support, etc.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibitedwithout governmental license, the need for which must be judged by the customer. The export or re-export of this productfrom a country other than Japan may also be prohibited withou...
Page 4 - Major Changes; Chapter 10 has been added.; The mark
Major Changes Page Description All The 44-pin plastic QFP package has been changed from µPD750008GB-xxx-3B4to µPD750008GB-xxx-3BS-MTX. The µPD75P0016 under development has been changed to the already-developedµPD75P0016. The input withstand voltage at ports 4 and 5 during open drain has been changed...
Page 5 - PREFACE; Readers
PREFACE Readers This manual is intended for engineers who want to learn the capabilities of the µPD750004, µPD750006, µPD750008, and µPD75P0016 to develop application systems based on them. Purpose The purpose of this manual is to help users understand the hardware capabilities (shown below) of the ...
Page 6 - Notation
Notation Data bit significance : Higher-order bits on the left side Lower-order bits on the right side Active low : xxx (Pin and signal names are overscored.) Memory map address : Low-order address on the upper side High-order address on the lower side Note : Explanation of an indicated part of text...
Page 7 - Other documents
* Related documents Some documents are preliminary editions, but they are not so specified in the tables below. Documents related to devices Document Name Document Number Japanese English µPD750004, 750006, 750008 Data Sheet U10738J IC-3647 µPD75P0016 Data Sheet U10328J To be prepared µPD750008 User...
Page 9 - CONTENTS; CHAPTER 1
- i - CONTENTS CHAPTER 1 GENERAL ......................................................................................................................... 1 1.1 FUNCTION OVERVIEW ......................................................................................... 2 1.2 ORDERING INFORMATION .......
Page 11 - CHAPTER 7
- iii - 5.3.5 Operation of the Watchdog Timer ............................................................. 102 5.3.6 Other Functions ......................................................................................... 103 5.4 CLOCK TIMER ...........................................................
Page 12 - OPERATING MODES WHEN WRITING TO AND VERIFYING
- iv - CHAPTER 8 RESET FUNCTION ........................................................................................................... 225 CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM) ................................... 229 9.1 OPERATING MODES WHEN WRITING TO AND VERIFYING THE PROGR...
Page 13 - HARDWARE INDEX (ALPHABETICAL ORDER WITH RESPECT TO THE
- v - APPENDIX A FUNCTIONS OF THE µPD75008, µPD750008, AND µPD75P0016 ............................ 299 APPENDIX B DEVELOPMENT TOOLS ................................................................................................ 301 APPENDIX C MASKED ROM ORDERING PROCEDURE .............................
Page 21 - CHAPTER 1 GENERAL; Model; Applications
1 CHAPTER 1 GENERAL CHAPTER 1 GENERAL The µPD750004, µPD750006, µPD750008, and µPD75P0016 are 75XL series 4-bit single-chip microcom- puters. The 75XL series is a successor of the 75X series consisting of many products. These µPD750004, µPD750006, µPD750008, and µPD75P0016 are collectively called th...
Page 22 - FUNCTION OVERVIEW
2 µPD750008 USER'S MANUAL 1.1 FUNCTION OVERVIEW Item Function Instruction execution • 0.95, 1.91, 3.81, 15.3 µs (when the main system clock operates at 4.19 MHz)time • 0.67, 1.33, 2.67, 10.7 µs (when the main system clock operates at 6.0 MHz) • 122 µs (when the subsystem clock operates at 32.768 kHz...
Page 23 - Note Code orders on and after April 1, 1996 can be accepted.
3 CHAPTER 1 GENERAL 1.2 ORDERING INFORMATION Part number Package On-chip ROM µPD750004CU-xxx 42-pin plastic shrink DIP (600 mil) Masked ROM µPD750004GB-xxx-3BS-MTX Note 44-pin plastic QFP (10 x 10 mm) Masked ROM µPD750006CU-xxx 42-pin plastic shrink DIP (600 mil) Masked ROM µPD750006GB-xxx-3BS-MTX N...
Page 24 - DIFFERENCES AMONG SUBSERIES PRODUCTS
4 µPD750008 USER'S MANUAL 1.3 DIFFERENCES AMONG SUBSERIES PRODUCTS Item µPD750004 µPD750006 µPD750008 µPD75P0016 Program counter 12 bits 13 bits 14 bits Program memory (byte) Masked ROM Masked ROM Masked ROM One-time PROM 4096 6144 8192 16384 Data memory (x 4 bits) 512 Mask Pull-up resistors at Inco...
Page 26 - , keeping the wiring as short as possible.
6 µPD750008 USER'S MANUAL 1.5 PIN CONFIGURATION (TOP VIEW) (1) 42-pin plastic shrink DIP (600 mil) µPD750004CU-XXX µPD750006CU-XXX µPD750008CU-XXX µPD75P0016CU Note Connect IC (V PP ) to V DD , keeping the wiring as short as possible. Remark ( ) : µPD75P0016. XT1 XT2 RESET X1 X2 P33 (/MD3) P32 (/MD2...
Page 28 - Pin name
8 µPD750008 USER'S MANUAL Pin name P00-P03 : Port 0 RESET : Reset input P10-P13 : Port 1 TI0 : Timer input 0 P20-P23 : Port 2 PTO0, 1 : Programmable timer output 0, 1 P30-P33 : Port 3 BUZ : Buzzer clock P40-P43 : Port 4 PCL : Programmable clock P50-P53 : Port 5 INT0, 1, 4 : External vectored interru...
Page 29 - CHAPTER 2 PIN FUNCTIONS
9 CHAPTER 2 PIN FUNCTIONS CHAPTER 2 PIN FUNCTIONS 2.1 PIN FUNCTIONS OF THE µPD750008 Table 2-1. Digital I/O Port Pins (1/2) Input/ Also 8 bit Upon I/O Pin used Function circuit output as I/O reset type Note 1 P00 Input INT4 4-bit input port (PORT0). x Input B P01 I/O SCK For P01 to P03, built-in pul...
Page 33 - Output; large-current output. These ports can directly drive the LED.
1 3 CHAPTER 2 PIN FUNCTIONS 2.2.2 P20-P23 (PORT2) : I/O Pins Used Also for PTO0, PTO1, PCL, and BUZ P30-P33 (PORT3) : I/O Pins Used Also for MD0-MD3 Note P40-P43 (PORT4), P50-P53 (PORT5) : N-ch Open-Drain Intermediate Withstand Voltage (13 V) Large-Current Output P60-P63 (PORT6), P70-P73 (PORT7) : T...
Page 36 - This is the positive power supply pin.; This is the ground pin.
1 6 µPD750008 USER'S MANUAL 2.2.14 XT1, XT2 These pins are used for connection to a crystal for subsystem clock oscillation. An external clock can also be applied. (a) Crystal oscillation (b) External clock 2.2.15 RESET This is the pin for active-low reset input. The RESET input is asynchronous. Whe...
Page 38 - Type A; Type D
1 8 µPD750008 USER'S MANUAL Type B-C 2.3 PIN INPUT/OUTPUT CIRCUITS Figure 2-1 shows schematic diagrams of the I/O circuitry of the µPD750008. Figure 2-1. Pin Input/Output Circuits (1/2) Type A Schmitt trigger input with hysteresis IN CMOS input buffer V DD IN P-ch N-ch Push-pull output which can be ...
Page 40 - CONNECTION OF UNUSED PINS
2 0 µPD750008 USER'S MANUAL 2.4 CONNECTION OF UNUSED PINS Table 2-3. Connection of Unused Pins Pin name Recommended connection P00/INT4 To be connected to V SS P01/SCK To be connected to V SS or V DD P02/SO/SB0 P03/SI/SB1 P10/INT0-P12/INT2 To be connected to V SS P13/TI0 P20/PTO0 Input state: To be ...
Page 41 - CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP; DATA MEMORY BANK STRUCTURE AND ADDRESSING MODES
2 1 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP The 75XL series architecture of the µPD750008 has the following features: • Internal RAM of up to 4K words x 4 bits (12-bit address) • Peripheral hardware expansibility To provide these fe...
Page 42 - restoring the MBS with the PUSH or POP instruction.; Examples 1. The MBE is cleared, and a fixed memory bank is used.; MBE
2 2 µPD750008 USER'S MANUAL SET1 MBE CLR1 MBE SET1 MBE MBE = 1 <Main program> <Subroutine> MBE = 0 MEB = 1 CLR1 MBE MBE = 0 RET <Interrupt processing> ; MBE = 0 is to be set in the vector table. MBE = 0 RETI Internal hardwareand static RAMoperations arerepeated. Applicable program ...
Page 54 - GENERAL REGISTER BANK CONFIGURATION; (RB) enabled at instruction execution is determined as; Table 3-2. Register Bank to Be Selected with the RBE and RBS; Normal processing; Bank 0 is always selected.
3 4 µPD750008 USER'S MANUAL 3.2 GENERAL REGISTER BANK CONFIGURATION The µPD750008 contains four register banks, each consisting of eight general registers: X, A, B, C, D, E, H, and L. These registers are mapped to addresses 00H to 1FH in memory bank 0 of the data memory (see Figure 3-5). To specify ...
Page 55 - restoring the RBS with the PUSH or POP instruction.; Example; SEL
3 5 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP Figure 3-4. Example of Register Bank Selection The setting of the RBS can be modified for subroutine processing or interrupt processing by saving or restoring the RBS with the PUSH or POP instruction. The RBE is set using the SET1 or CLR1 ins...
Page 60 - Can also be manipulated as the BS in 8-bit units.
4 0 µPD750008 USER'S MANUAL Figure 3-7. µPD750008 I/O Map (1/5) Notes 1. Can be manipulated separately as the RBS and MBS in 4-bit units. Can also be manipulated as the BS in 8-bit units. Use SEL MBn and SEL RBn instructions to write data to MBS and RBS respectively. 2. WDTM: Watchdog timer enable f...
Page 62 - : Interrupt enable flag; Notes 1. Only bit 3 can be manipulated by an EI/DI instruction.
4 2 µPD750008 USER'S MANUAL Figure 3-7. µPD750008 I/O Map (3/5) Remarks 1. IExxx : Interrupt enable flag 2. IRQxxx : Interrupt request flag Notes 1. Only bit 3 can be manipulated by an EI/DI instruction. 2. Bits 3 and 2 can be manipulated bit by bit by a STOP/HALT instruction. (R/ W) FB0H FB2H FB3H ...
Page 64 - manipulation is performed.
4 4 µPD750008 USER'S MANUAL Figure 3-7. µPD750008 I/O Map (5/5) Notes 1. Bit 1 can be read or written only in serial operation enable mode. It can be read when four-bit manipulation is performed. 2. KR0 to KR7 can be read (R) bit by bit. When inputting 4 bits at a time, specify PORT6 or PORT7. FF0H ...
Page 65 - CHAPTER 4 INTERNAL CPU FUNCTIONS; Mk I MODE/Mk II MODE SWITCH FUNCTIONS; It can be used in the 75XL CPUs having a ROM of up to 16KB.; Table 4-1. Differences between Mk I Mode and Mk II Mode
4 5 CHAPTER 4 INTERNAL CPU FUNCTIONS CHAPTER 4 INTERNAL CPU FUNCTIONS 4.1 Mk I MODE/Mk II MODE SWITCH FUNCTIONS 4.1.1 Differences between Mk I Mode and Mk II Mode The CPU of the µPD750008 subseries has two modes (Mk I mode and Mk II mode) and which mode is used is selectable. Bit 3 of the stack bank...
Page 66 - I mode, initialize the register to 10xxB; at the beginning of the program. To use the CPU in Mk II mode,; Figure 4-1. Stack Bank Selection Register Format
4 6 µPD750008 USER'S MANUAL 4.1.2 Setting of the Stack Bank Selection Register (SBS) The Mk I mode and Mk II mode are switched by stack bank selection register. Figure 4-1 shows the register configuration. The stack bank selection register is set with a 4-bit memory operation instruction. To use the...
Page 67 - to the number of bytes in the instruction.
4 7 CHAPTER 4 INTERNAL CPU FUNCTIONS PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PC13 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PC11 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PC12 4.2 PROGRAM COUNTER (PC): 12 BITS (µPD750004) 13 BITS (µPD750006 AND µPD750008) 14 BITS (µPD75P001...
Page 69 - address with only the 8 low-order bits of the PC changed.
4 9 CHAPTER 4 INTERNAL CPU FUNCTIONS Figure 4-3. Program Memory Map (in µPD750004) Note Can be used only in the MkII mode. Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address with only the 8 low-order bits of the PC changed. * MBE RBE 7 6 0000H MBE ...
Page 70 - Note Can be used only in the MkII mode.
5 0 µPD750008 USER'S MANUAL Figure 4-4. Program Memory Map (in µPD750006) Note Can be used only in the MkII mode. Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address with only the 8 low-order bits of the PC changed. MBE RBE 7 6 0000H MBE RBE 0002H M...
Page 73 - • Memory bank 15 (peripheral hardware area); Note Memory bank 0 or 1 can be selected as the stack area.
5 3 CHAPTER 4 INTERNAL CPU FUNCTIONS 4.4 DATA MEMORY (RAM): 512 WORDS x 4 BITS The data memory consists of a data area and peripheral hardware area as shown in Figure 4-7. The data memory consists of the following memory banks with each bank made of 256 words x 4 bits. • Memory banks 0 and 1 (data a...
Page 74 - Specification of a Data Memory Bank; is addressed by 8-bit immediate data or a register pair.; • Peripheral hardware area : Chapter 5
5 4 µPD750008 USER'S MANUAL 4.4.2 Specification of a Data Memory Bank If the memory bank enable flag (MBE) enables bank specification (MBE = 1), a memory bank is specified with the 4-bit memory bank select register (MBS = 0, 1, 15). If the MBE disables bank specification (MBE = 0), memory bank 0 or ...
Page 76 - GENERAL REGISTER: 8 x 4 BITS x 4 BANKS; be used as data pointers.; Data memory
5 6 µPD750008 USER'S MANUAL 4.5 GENERAL REGISTER: 8 x 4 BITS x 4 BANKS The general registers are mapped to particular addresses in data memory. Four banks of registers are provided, with each bank consisting of eight 4-bit registers (B, C, D, E, H, L, X, and A). The register bank (RB) to be enabled ...
Page 77 - Bit accumulator
5 7 CHAPTER 4 INTERNAL CPU FUNCTIONS Figure 4-9. Register Pair Format 4.6 ACCUMULATOR In the µPD750008, the A register and XA register pair function as accumulators. The A register is mainly used for 4-bit data processing instructions, and the XA register pair is mainly used for 8-bit data processin...
Page 78 - Table 4-2. Stack Area to Be Selected by the SBS; boundaries is enabled only by resetting the SBS.
5 8 µPD750008 USER'S MANUAL 4.7 STACK POINTER (SP) AND STACK BANK SELECT REGISTER (SBS) The µPD750008 uses static RAM as stack memory (LIFO scheme), and the 8-bit register holding the start address of the stack area is the stack pointer (SP). The stack area is located at addresses 000H to 1FFH in me...
Page 80 - PSW bits other than MBE and RBE are not saved or restored.
6 0 µPD750008 USER'S MANUAL PC11 - PC8 MBE SP + 2 PC3 - PC0 PC7 - PC4 SP + 4 IST1 CY SP + 6 SP + 1 SP + 3 SP + 5 Stack RBE PC12 IST0 SK2 MBE SK1 RBE SK0 RETI instruction PSW PC11 - PC8 MBE SP + 2 PC3 - PC0 PC7 - PC4 SP + 4 SP + 1 SP + 3 Stack RBE PC12 RET or RETS instruction Lower bits of pair regis...
Page 83 - MOV
6 3 CHAPTER 4 INTERNAL CPU FUNCTIONS Table 4-4. Carry Flag Manipulation Instructions Instruction (mnemonic) Carry flag operation/processing Instruction dedicated to carry SET1 CY Sets CY to 1. flag manipulation CLR1 CY Clears CY to 0. NOT1 CY Inverts the state of CY. SKT CY Skips if CY is 1. Bit tra...
Page 84 - Table 4-5. Information Indicated by the Interrupt Status Flag; before an interrupt occurs.
6 4 µPD750008 USER'S MANUAL Table 4-5. Information Indicated by the Interrupt Status Flag IST1 IST0 Status of processing Processing and interrupt control being performed 0 0 Status 0 Normal program processing is being performed. Any interrupts are acceptable. 0 1 Status 1 A lower- or higher-priority...
Page 85 - Figure 3-2 shows the range of addressing using MBE and MBS settings.
6 5 CHAPTER 4 INTERNAL CPU FUNCTIONS When the RBE is reset to 0, register bank 0 is always selected as general registers, regardless of the setting of the RBS. A RESET signal automatically initializes the RBE by setting the RBE to the state of bit 6 at program memory address 0. When a vectored inter...
Page 86 - Table 4-6. Register Bank to Be Selected with the RBE and RBS
6 6 µPD750008 USER'S MANUAL Table 4-6. Register Bank to Be Selected with the RBE and RBS Bank 0 is always selected. RBE RBS 3 2 1 0 0 0 0 x x Bank 0 is selected. 0 0 Bank 1 is selected. 1 0 0 0 1 Bank 2 is selected. 1 0 Bank 3 is selected. 1 1 Register bank x: Don’t care Always 0
Page 87 - CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS; Figure 5-1. Data Memory Addresses of Digital Ports
67 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5.1 DIGITAL I/O PORTS The µPD750008 employs the memory mapped I/O method. Thus, all input/output ports are mapped on the data memory space. Figure 5-1. Data Memory Addresses of Digital Ports Remark Some I/O parts can ...
Page 88 - Table 5-1. Types and Features of Digital Ports; is turned off so that these ports are in the input mode.
68 µPD750008 USER'S MANUAL 5.1.1 Types, Features, and Configurations of Digital I/O Ports Table 5-1 lists the types of digital I/O ports. Figures 5-2 to 5-6 show the configurations of the ports. Table 5-1. Types and Features of Digital Ports Port name Function Operation and feature Remarks (symbol) ...
Page 92 - Figure 5-5. Configurations of Ports 4 and 5
72 µPD750008 USER'S MANUAL Figure 5-5. Configurations of Ports 4 and 5 Internal bus Input buffer MPX V DD Pm0 Pm1 Pm2 Pm3 PMm = 0 PMm = 1 PMm Output latch Pull-up resistor N-ch open-drain output buffer Corresponding bits of port mode register group B (m = 4, 5) (Mask option)
Page 99 - output buffers kept off.; (2) Operation when the output mode is set; bits is executed, output latch data is manipulated.
79 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5.1.4 Digital I/O Port Operation When a data memory manipulation instruction is executed for a digital I/O port, the operation of the port and pins depends on the I/O mode setting (Table 5-3). This is because data taken in on the internal bus is the data in...
Page 101 - is connected by software in the format shown in Figure 5-8.
81 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5.1.5 Specification of Bilt-in Pull-Up Resistors A pull-up resistor can be contained at each port pin of the µPD750008 (except for P00). Whether to use the pull-up resistor can be specified by software (for some pins) or a mask option (for the other pins). ...
Page 102 - latch data on the internal bus.
82 µPD750008 USER'S MANUAL Figure 5-8. Pull-Up Resistor Specification Register Format Pull-up resistor specification register group A Pull-up resistor specification register group B 5.1.6 I/O Timing of Digital I/O Ports Figure 5-9 shows the timing of data output to an output latch and the timing of ...
Page 104 - CLOCK GENERATOR; Figure 5-11 shows the configuration of the clock generator.; Figure 5-11. Block Diagram of the Clock Generator; : Main system clock frequency; : Subsystem clock frequency; ) is equal to one machine cycle of an instruction.
84 µPD750008 USER'S MANUAL 5.2 CLOCK GENERATOR The clock generator supplies various clock signals to the CPU and peripheral hardware to control the CPU operation mode. 5.2.1 Clock Generator Configuration Figure 5-11 shows the configuration of the clock generator. Figure 5-11. Block Diagram of the Cl...
Page 107 - CPU operation mode control bits; : Output frequency from the main system clock oscillator; f; : Output frequency from the subsystem clock oscillator
87 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-12. Format of the Processor Clock Control Register Address FB3H 3 2 1 0 PCC3 PCC2 PCC1 PCC0 Symbol PCC CPU clock selection bit(Operation with f X = 6.0 MHz) ( ) is actual frequency at f X = 6.0 MHz CPU clock frequency Φ = f X /64 (93.7 kHz) 1 machi...
Page 108 - Figure 5-13. Format of the System Clock Control Register; is needed to change the system clock. This means
88 µPD750008 USER'S MANUAL (2) System clock control register (SCC) The SCC is a 4-bit register for selecting CPU clock F with the least significant bit and for controlling the termination of main system clock generation with the most significant bit (see Figure 5-13). Bits 0 and 3 of the SCC are loc...
Page 110 - poten tial as that of V; . It must not be grounded to a grounding pattern carry; a resistor must be added to XT2 in series.
90 µPD750008 USER'S MANUAL Any line carrying a high pulsating current must be kept away as far as possible. • The grounding point of the capacitor of the oscillator must have the same poten tial as that of V SS . It must not be grounded to a grounding pattern carry ing a high current. • No signal mu...
Page 112 - (5) Control functions of subsystem clock oscillator; the operating supply voltage is high (V
92 µPD750008 USER'S MANUAL (4) Frequency divider The frequency divider divides the output (f X ) of the main system clock oscillator to generate various clocks. (5) Control functions of subsystem clock oscillator The subsystem clock oscillator of the µPD750008 subseries has two control functions to ...
Page 114 - Setting after switching; machine; machine
94 µPD750008 USER'S MANUAL 5.2.3 System Clock and CPU Clock Setting (1) Time required to change the system clock and CPU clock The system clock and CPU clock can be changed by using the least significant bit of the SCC and the low-order two bits of the PCC. This switching is not performed immediatel...
Page 115 - for stable oscillation.
95 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (2) Procedure for changing the system clock and CPU clock The procedure for changing the system clock and CPU clock is explained using Figure 5-19. Figure 5-19. Changing the System Clock and CPU Clock <1> A RESET signal starts CPU operation at the low...
Page 116 - (1) Configuration of the clock output circuit; Figure 5-20 shows the configuration of the clock output circuit.; (2) Functions of the clock output circuit; or to supply clock pulses to a peripheral LSI device.; Figure 5-20. Configuration of the Clock Output Circuit; or disabling clock output.
96 µPD750008 USER'S MANUAL 5.2.4 Clock Output Circuit (1) Configuration of the clock output circuit Figure 5-20 shows the configuration of the clock output circuit. (2) Functions of the clock output circuit The clock output circuit outputs a clock pulse signal on the P22/PCL pin to output remote con...
Page 117 - is the CPU clock selected by PCC.
97 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (3) Clock output mode register (CLOM) The CLOM is a 4-bit register to control clock output. The CLOM is set by a 4-bit memory manipulation instruction. No read operation is allowed on this register. Example CPU clock F is output on the PCL/P22 pin. SEL MB15...
Page 118 - Figure 5-22. Application to Remote Control Output
98 µPD750008 USER'S MANUAL (4) Application to remote control output The clock output function of the µPD750008 is applicable to remote control output. The frequency of the carrier for remote control output is selected by the clock frequency select bit of the clock output mode register. Pulse output ...
Page 119 - A 4-bit memory manipulation instruction is used to set the BTM.
99 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5.3 BASIC INTERVAL TIMER/WATCHDOG TIMER The µPD750008 contains an 8-bit basic interval timer/watchdog timer, which has the following functions: (a) Interval timer operation which generates a reference timer interrupt (b) Operation as a watchdog timer for de...
Page 120 - Figure 5-24. Format of the Basic Interval Timer Mode Register; Basic interval timer/watchdog timer start control bit
100 µPD750008 USER'S MANUAL When bit 3 is set to 1, the BT is cleared, and the basic interval ltimer/watchdog timer interrupt request flag (IRQBT) is also cleared (to start the basic interval timer/watchdog timer). A RESET signal clears the interval timer to 0, and the longest interrupt request sign...
Page 126 - Figure 5-26 shows the configuration of the clock timer.; Figure 5-26. Block Diagram of the Clock Timer; The values in parentheses are for f
106 µPD750008 USER'S MANUAL 5.4.1 Configuration of the Clock Timer Figure 5-26 shows the configuration of the clock timer. Figure 5-26. Block Diagram of the Clock Timer The values in parentheses are for f X = 4.194304 MHz and f XT = 32.768 kHz. 5.4.2 Clock Mode Register The clock mode register (WM) ...
Page 133 - Timer start indication bit
113 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-31. Timer Counter Mode Register (Channel 1) Format Address FA8H 7 6 TM16 5 TM15 4 TM14 3 TM13 2 TM12 1 0 Symbol TM1 TM13 Timer start indication bit When 1 is written into the bit, the counter and IRQT1 flag are cleared. If bit 2 is set to 1, count...
Page 137 - Table 5-6. Resolution and Longest Setup Time; Mode register
117 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (2) Timer/event counter time setting [Timer setup time] (cycle) is found by dividing [modulo register contents + 1] by [count pulse (CP) frequency] selected by setting the mode register. n+1 T (sec) = = (n + 1) · (resolution) f CP T (sec) : Timer setup tim...
Page 138 - Caution Set a value other than 00H in the modulo register (TMODn).
118 µPD750008 USER'S MANUAL (3) Timer/event counter operation The timer/event counter operates as follows. Figure 5-35 shows the configuration of the timer/event counter. <1> The count pulse (CP) is selected by setting the mode register (TMn) and is input to the count register (Tn). <2> ...
Page 141 - a signal applied to the TI0 pin must have a pulse wider than that.
121 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (3) Error in reading the count register The contents of the count register can be read using an 8-bit data memory manipulation instruction at any time. During operation by such an instruction, all count pulse changes are held not to change the count regist...
Page 142 - (5) Operation after the modulo register is changed; restarted after the contents of the modulo register are changed.
122 µPD750008 USER'S MANUAL (5) Operation after the modulo register is changed The contents of the modulo register are changed when an 8-bit data memory manipulation instruction is executed. If the new value of the modulo register is less than the value of the count register, the count register cont...
Page 143 - The functions of the four modes are outlined below.
123 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5.6 SERIAL INTERFACE 5.6.1 Serial Interface Functions The µPD750008 contains a clock synchronous 8-bit serial interface, which has four modes. The functions of the four modes are outlined below. (1) Operation halt mode This mode is used when serial transfe...
Page 144 - Figure 5-39 shows the block diagram of the serial interface.
124 µPD750008 USER'S MANUAL Figure 5-38. Example of the SBI System Configuration 5.6.2 Configuration of Serial Interface Figure 5-39 shows the block diagram of the serial interface. SCK Master CPU SB0, SB1 SCK SB0, SB1 Slave CPU #1 Address 1 SCK SB0, SB1 Slave IC #N Address N Address Command Data Se...
Page 147 - detect control signals generated in the SBI mode.; P01 output latch; When the RESET signal is entered, this latch is set to 1.
127 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (9) Serial clock control circuit The serial clock control circuit controls the serial clock to be supplied to the shift register, or controls the clock to be output to the SCK pin when the internal system clock is used. (10) Busy/acknowledge output circuit...
Page 148 - Serial interface operation enable/disable specification bit (W); undefined value may result during transfer.
128 µPD750008 USER'S MANUAL Figure 5-40. Format of Serial Operation Mode Register (CSIM) (2/4) Serial interface operation enable/disable specification bit (W) Shift register Serial clock IRQCSI SO/SB0 and operation counter flag SI/SB1 pins CSIE 0 Shift operation Cleared Held Used only for port 0 dis...
Page 150 - Serial transfer dependent on the contents of CSIM is enabled.
130 µPD750008 USER'S MANUAL Figure 5-40. Format of Serial Operation Mode Register (CSIM) (4/4) Remarks 2. The P01/SCK pin assumes any of the following states according to the state of CSIE, CSIM1, and CSIM0: CSIE CSIM1 CSIM0 P01/SCK pin state 0 0 0 Input port 1 0 0 High impedance 0 0 1 High level ou...
Page 151 - of input data from the serial bus. SBIC is used mainly in the SBI mode.
131 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (2) Serial bus interface control register (SBIC) Figure 5-41 shows the format of the serial bus interface control register (SBIC). SBIC is an 8-bit register consisting of bits for controlling the serial bus and flags for indicating the states of input data...
Page 152 - Cautions 1. Never set ACKT before or during serial transfer.
132 µPD750008 USER'S MANUAL Figure 5-41. Format of Serial Bus Interface Control Register (SBIC) (2/3) Busy enable bit (R/W) BSYE 0 <1> The busy signal is automatically disabled. <2> Busy signal output is stopped in phase with the falling edge of SCK immediately after clear instruction ex...
Page 153 - RELD; after serial transfer; RELT; after serial transfer.
133 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-41. Format of Serial Bus Interface Control Register (SBIC) (3/3) Bus release detection flag (R) RELD Condition for being cleared (RELD = 0) Condition for being set (RELD = 1) <1> The transfer start instruction is executed. The bus release si...
Page 154 - Figure 5-42. Peripheral Hardware of Shift Register
134 µPD750008 USER'S MANUAL (3) Shift register (SIO) Figure 5-42 shows the configuration of peripheral hardware of shift register. SIO is an 8-bit register which performs parallel-serial conversion and serial transfer (shift) operation in phase with the serial clock. Serial transfer is started by wr...
Page 155 - operation mode register.
135 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (a) Slave address detection [In the SBI mode] SVA is used when the µPD750008 is connected as a slave device to the serial bus. SVA is an 8- bit register for a slave to set its slave address (number assigned to it). The master outputs a slave address to the...
Page 157 - Communication is performed using three lines:; Remark The μPD750008 can also be used as a slave CPU.; • Serial bus interface control register (SBIC)
137 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5.6.5 Three-Wire Serial I/O Mode Operations The three-wire serial I/O mode is compatible with other modes used in the 75 XL series, 75X series, µPD7500 series, and 87AD series. Communication is performed using three lines: Serial clock (SCK), serial output...
Page 158 - Serial interface operation mode selection bit (W)
138 µPD750008 USER'S MANUAL Serial interface operation enable/disable specification bit (W) Shift register operation Serial clock counter IRQCSI flag SO/SB0 and SI/SB1 pins CSIE 1 Shift operation enabled Count operation Can be set Used in each modeas well as for port 0 Signal from address comparator...
Page 159 - SBIC is manipulated using a bit memory manipulation instruction.; CMDT; in phase with the serial clock.
139 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (b) Serial bus interface control register (SBIC) To use the three-wire serial I/O mode, set SBIC as shown below. (For details on SBIC format, see (2) in Section 5.6.3.) SBIC is manipulated using a bit memory manipulation instruction. When the RESET signal ...
Page 160 - SO pin can be manipulated by setting the RELT bit and CMDT bit.
140 µPD750008 USER'S MANUAL SCK SI IRQCSI 1 SO 2 3 4 5 6 7 8 DI0 DO0 DI1 DO1 DI2 DO2 DI3 DO3 DI4 DO4 DI5 DO5 DI6 DO6 DI7 DO7 Transfer operation is started in phase with falling edge of SCK. Execution of instruction that writes data to SIO (Transfer start request) Completion of transfer Figure 5-44. ...
Page 161 - Figure 5-45 shows operations of RELT and CMDT.; Figure 5-45. Operations of RELT and CMDT; order of SIO is always the same.
141 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (4) Signals Figure 5-45 shows operations of RELT and CMDT. Figure 5-45. Operations of RELT and CMDT (5) Switching between MSB and LSB as the first transfer bit The three-wire serial I/O mode has a function that can switch between the MSB and LSB as the fir...
Page 165 - manipulated bit by bit.
145 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (a) Serial operation mode register (CSIM) To use the two-wire serial I/O mode, set CSIM as shown below. (For details on CSIM format, see (1) in Section 5.6.3.) CSIM is manipulated using an 8-bit manipulation instruction. Bits 7, 6, and 5 of CSIM can be man...
Page 166 - SBIC is manipulated using a bit manipulation instruction.
146 µPD750008 USER'S MANUAL Serial interface operation mode selection bit (W) CSIM4 CSIM3 CSIM2 Shift register sequence SO pin function SI pin function 0 1 1 SIO 7-0 <—> XA SB0/P02 (N-ch P03 input (Transfer starting with MSB) open-drain I/O) 1 P02 input SB1/P03 (N-chopen-drain I/O) Serial cloc...
Page 168 - Figure 5-49. Operations of RELT and CMDT; conditions are satisfied:; written to SIO beforehand.
148 µPD750008 USER'S MANUAL (3) Serial clock selection To select the serial clock, manipulate bits 0 and 1 of serial operation mode register (CSIM). The serial clock can be selected out of the following four clocks: Table 5-8. Serial Clock Selection and Application (In the Two-Wire Serial I/O Mode) ...
Page 169 - methods described below.; and μPD7225G are connected as slaves.
149 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (6) Error detection In the two-wire serial I/O mode, the state of serial bus SB0 or SB1 being used for communication is loaded into the shift register (SIO) of the transmitting device. So a transmission error can be detected by the methods described below....
Page 170 - Figure 5-50. Example of SBI System Configuration
150 µPD750008 USER'S MANUAL The µPD750008, which is the master microcomputer, outputs a serial clock, and all slave microcomputers operate with an external clock. 5.6.7 SBI Mode Operation The SBI (serial bus interface) is a high-speed serial interface that conforms to the NEC serial bus format. To a...
Page 171 - on a circuit board can be simplified.
151 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Cautions 1. In the SBI mode, the serial data bus pin SB0 (or SB1) is an open-drain output. So the serial data bus line is placed in the wired OR state. A pull-up resistor is required for the serial data bus line. 2. To switch between the master and slave, ...
Page 172 - Serial data forms one frame as shown below.; Address transfer
152 µPD750008 USER'S MANUAL (2) SBI definition The format of serial data and signal used in the SBI mode are described below. Serial data to be transferred in the SBI mode is classified into three types: Address, command, and data. Serial data forms one frame as shown below. Figure 5-51 is a timing ...
Page 173 - detect the bus release signal.
153 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (a) Bus release signal (REL) When the SCK line is high (the serial clock is not output), the SB0 (or SB1) line changes from low to high. This signal is called the bus release signal, and is output by the master. Figure 5-52. Bus Release Signal This signal ...
Page 174 - Figure 5-55. Slave Selection Using an Address; data to or from the slave.
154 µPD750008 USER'S MANUAL Figure 5-55. Slave Selection Using an Address (d) Command and data The master sends commands to the slave selected by sending an address. The master also transfers data to or from the slave. Figure 5-56. Command Figure 5-57. Data The 8-bit data following the command signa...
Page 175 - [When output in phase with the 11th clock of SCK]
155 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-58. Acknowledge Signal [When output in phase with the 11th clock of SCK] [When output in phase with the 9th clock of SCK] The acknowledge signal is a one-shot pulse output in phase with the falling edge of SCK after 8-bit data transfer. This signa...
Page 177 - undefined value may be read during transfer.
157 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Serial interface operation enable/disable specification bit (W) Shift register operation Serial clock counter IRQCSI flag SO/SB0 and SI/SB1 pins CSIE 1 Shift operation enabled Count operation Can be set Used in each modeas well as for port 0 Signal from ad...
Page 178 - Remark The value at 4.19 MHz is indicated in parentheses.
158 µPD750008 USER'S MANUAL Serial clock selection bit (W) CSIM1 CSIM0 Serial clock SCK pin mode 0 0 External clock applied to SCK pin Input 0 1 Timer/event counter output (TOUT0) Output 1 0 f X /2 4 (262 kHz) 1 1 f X /2 3 (524 kHz) Remark The value at 4.19 MHz is indicated in parentheses. (b) Seria...
Page 180 - clock can be selected out of the following four clocks:
160 µPD750008 USER'S MANUAL Bus release trigger bit (W) RELT Control bit for bus release signal (REL) trigger output.By setting RELT = 1, the SO latch is set to 1. Then the RELT bit automatically cleared to 0. Caution Never clear SB0 (or SB1) during serial transfer. Be sure to clear SB0 (or SB1) bef...
Page 186 - Notes
166 µPD750008 USER'S MANUAL Table 5-10. Various Signals Used in the SBI Mode (2/2) Synchronous clock for outputting address / command/data, ACK signal, synchronous BUSY signal, and so on. Address/command/data is output during first 8 clock cycles. 8-bit data transferred in phase with SCK after REL s...
Page 187 - the master and a slave.
167 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (6) Pin configuration The configurations of serial clock pin SCK and serial data bus pin (SB0 or SB1) are as follows: (a) SCK: Pin for serial clock I/O <1> Master : CMOS, push-pull output <2> Slave : Schmitt input (b) SB0, SB1: Pin for serial d...
Page 188 - occurrence of a transmission error is assumed.
168 µPD750008 USER'S MANUAL (7) Address match detection method In the SBI mode, communication starts when the master selects a particular slave device by outputting an address. An address match is detected by hardware. The slave address register (SVA) is available. In the wake- up state (WUP = 1), I...
Page 193 - written to SIO beforehand for reception.; Exchanges transmit data with receive data and startstransfer; Notes on the SBI mode
173 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS (10) Transfer start Serial transfer is started by writing transfer data in shift register (SIO), provided that the following two conditions are satisfied: • The serial interface operation enable/disable bit (CSIE) is set to 1. • The internal serial clock i...
Page 194 - SBI mode; The master can be switched to another CPU with a command.; Figure 5-71. Example of Serial Bus Configuration
174 µPD750008 USER'S MANUAL (12) SBI mode This section describes an example of application which performs serial data communication in the SBI mode. In the example, the µPD750008 can be used as either the master CPU or a slave CPU on the serial bus. The master can be switched to another CPU with a c...
Page 196 - The master sends ACK to the slave each time it receives one byte.; Figure 5-73. Transfer Format of the WRITE and END Commands; Figure 5-74. Transfer Format of the STOP Command; S: Output by the slave
176 µPD750008 USER'S MANUAL When the slave receives a transmission data count, if it has data enough for transmitting the specified number of bytes of data, the slave returns ACK. If the slave does not have enough data for transmission, an error occurs; ACK is not returned in this case. The master s...
Page 197 - The STATUS command reads the status of the current slave.; Figure 5-75. Transfer Format of the STATUS Command; The slave returns the status in the format shown in Figure 5-78.
177 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS <3> STATUS command The STATUS command reads the status of the current slave. Figure 5-75. Transfer Format of the STATUS Command Remark M: Output by the master S: Output by the slave The slave returns the status in the format shown in Figure 5-78. Fig...
Page 198 - Figure 5-78. Transfer Format of the CHGMST Command
178 µPD750008 USER'S MANUAL <4> RESET command The RESET command changes the currently selected slave to a non-selected slave. When a RESET command is transmitted, any slave can be placed in the non-selected state. Figure 5-77. Transfer Format of the RESET Command Remark M: Output by the master...
Page 200 - Example To output one SCK/P01 pin clock cycle by software; before the instruction is executed.; Not allowed
180 µPD750008 USER'S MANUAL P01/SCK P01 output latch SCK To internal circuit Address FF0H.1 SCK pin output mode From the serial clock control circuit Example To output one SCK/P01 pin clock cycle by software SEL MB15 ; or CLR1 MBE MOV XA,#10000011B ; SCK (f X /2 3 ), output mode MOV CSIM,XA CLR1 0FF...
Page 201 - the buffer is useful in processing long data bit by bit.; Figure 5-81. Format of the Bit Sequential Buffer; specifying BSB0 or BSB2.
181 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5.7 BIT SEQUENTIAL BUFFER: 16-BIT The bit sequential buffer (BSB) is special data memory for bit manipulations. In particular, the buffer allows bit manipulations to be performed very easily by sequentially changing address and bit specifications. So the b...
Page 203 - CHAPTER 6 INTERRUPT AND TEST FUNCTIONS; interrupt processing.; CONFIGURATION OF THE INTERRUPT CONTROL CIRCUIT
183 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS CHAPTER 6 INTERRUPT AND TEST FUNCTIONS The µPD750008 has seven vectored interrupt sources and two test inputs, allowing a wide range of applications. In addition, the interrupt control circuitry of the µPD750008 has the following features for very high-spee...
Page 205 - s i m u l t a n e o u s l y g e n e r a t e d .
185 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS 6.2 TYPES OF INTERRUPT SOURCES AND VECTOR TABLES Table 6-1 lists the types of interrupt sources, and Figure 6-2 shows vector tables. Table 6-1. Interrupt Sources Interrupt source signal In/out Interrupt Vectored interrupt request priority Note (vector table...
Page 208 - DI; Caution Disable interrupts before setting the IPS.
188 µPD750008 USER'S MANUAL Table 6-2. Set Signals for Interrupt Request Flags Interrupt Set signals for interrupt request flags Interrupt request flag enable flag IRQBT Set by a reference time interval signal from the basic interval timer/watchdog IEBT timer. IRQ4 Set by a detected rising or fallin...
Page 209 - High-order interrupt selection
189 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS Figure 6-3. Interrupt Priority Specification Register IPS0 IPS1 IPS2 IPS3 0 1 2 3 IPS Symbol FB2H Address 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 1 High-order interrupt selection All low-order interrupt VRQ1 (INTBT/INT4) VRQ2 (INT0) VRQ3 (INT1) VR...
Page 210 - The edge to be detected can be selected.; The INT0 pin is supplied with sampling clock; Note When the frequency of a sampling clock is; , these cycles are equal to 2t; frequency of a sampling clock is f
190 µPD750008 USER'S MANUAL (3) Configurations of the INT0, INT1, and INT4 circuits (a) As shown in Figure 6-4 (a), the INT0 circuit accepts an external interrupt at its rising or falling edge. The edge to be detected can be selected. The INT0 circuit has a noise elimination function (see Figure 6-5...
Page 212 - Remark t
192 µPD750008 USER'S MANUAL Figure 6-5. I/O Timing of a Noise Eliminator Remark t SMP = t CY or 64/f X INT0 Shaped output INT0 INT0 INT0 Shaped output Shaped output Shaped output <1> Shorter than sampling cycle (t SMP ) <2> 1 to 2 times <3> Longer than 2 times (a) (b) t SMP t SMP t...
Page 214 - Table 6-3. Interrupt Processing Statuses of IST0 and IST1
194 µPD750008 USER'S MANUAL (4) Interrupt status flags The interrupt status flags (IST0 and IST1), which are contained in the PSW, indicate the status of processing currently executed by the CPU. By using the content of these flags, the interrupt priority control circuit controls multiple interrupts...
Page 215 - start of interrupt are stored in each vector table.
195 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS 6.4 INTERRUPT SEQUENCE When an interrupt occurs, it is processed using the procedure shown in Figure 6-7. Figure 6-7. Interrupt Sequence Notes 1. IST0 and IST1 are the interrupt status flags (bits 3 and 2 of the PSW). (See Table 6-3.) 2. An interrupt servic...
Page 216 - MULTIPLE INTERRUPT PROCESSING CONTROL; double interrupt processing.
196 µPD750008 USER'S MANUAL 6.5 MULTIPLE INTERRUPT PROCESSING CONTROL The µPD750008 can handle multiple interrupts by either of the following methods. (1) Multiple interrupt processing by a high-order interrupt In this method, the µPD750008 selects an interrupt source among multiple interrupt source...
Page 217 - processing is enabled.
197 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS (2) Multiple interrupt processing by changing the interrupt status flags Changing the interrupt status flags with the program causes multiple interrupts to be enabled. That is, when the interrupt processing program changes both IST1 and IST0 to 0 (status 0)...
Page 218 - PROCESSING OF INTERRUPTS SHARING A VECTOR ADDRESS; processing is started by the remaining interrupt request.; Table 6-4. Identifying Interrupt Sharing Vector Table Address; With higher priority
198 µPD750008 USER'S MANUAL 6.6 PROCESSING OF INTERRUPTS SHARING A VECTOR ADDRESS Interrupt sources INTBT and INT4 share a vector table, so an interrupt source is selected as described below. (1) Using only one interrupt The interrupt enable flag for desired one of the two interrupt sources sharing ...
Page 220 - MACHINE CYCLES FOR STARTING INTERRUPT PROCESSING; service routine after an interrupt request flag (IRQn) is set.; cycles is executed, then the interrupt service routine is started.
200 µPD750008 USER'S MANUAL 6.7 MACHINE CYCLES FOR STARTING INTERRUPT PROCESSING With the µPD750008 series, the following machine cycles are used to start the execution of the interrupt service routine after an interrupt request flag (IRQn) is set. (1) When IRQn is set during execution of an interru...
Page 221 - D: Interrupt service routine is executed.
201 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS (2) When IRQn is set during an instruction other than that described in (1) (a) When IRQn is set at the last machine cycle of the instruction being executed In this case, an instruction preceded by the instruction being executed is executed, and an interrup...
Page 222 - EFFECTIVE USE OF INTERRUPTS; PUSH BS instruction before selecting memory bank 1.; (3) Use of a software interrupt for debugging; To use the interrupt function, a main program must:
202 µPD750008 USER'S MANUAL 6.8 EFFECTIVE USE OF INTERRUPTS The interrupt function can be used more effectively in the ways described below. (1) MBE = 0 is set for the interrupt service routine By allocating addresses 00H to 7FH as data memory used by the interrupt service routine and specifying MBE...
Page 224 - <3> Interrupts are enabled by the EI and EI IExxx instructions.; interrupts are disabled.
204 µPD750008 USER'S MANUAL (2) Example of using INTBT, INT0 (falling edge active), and INTT0 without multiple interrupt processing <1> A RESET signal disables all interrupts, setting status 0. <2> INT0 is set to be falling edge active. <3> Interrupts are enabled by the EI and EI I...
Page 225 - and all the interrupts are disabled.
205 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS (3) Nesting of interrupts with higher priority (INTBT has higher priority and INTT0 and INTCSI have lower priority) <1> INTBT is specified as having the higher priority by setting of IPS, and the interrupt is enabled at the same time. <2> INTT0 ...
Page 227 - start the interrupt service program for INTT0, which has been held.
207 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS (5) Execution of held interrupts – two interrupts with lower priority occur concurrently – <1> When INT0 and INTT0 with the lower priority occur concurrently (during execution of the same instruction), INT0, with a higher priority, is executed first. ...
Page 228 - priority and INTT0 and INTCSI have lower priority) –; the interrupt with the lower priority is kept pending.
208 µPD750008 USER'S MANUAL (6) Executing pending interrupt – interrupt occurs during interrupt processing (INTBT has higher priority and INTT0 and INTCSI have lower priority) – <1> When INTBT with the higher priority and INTT0 with the lower priority occur at the same time, the processing of ...
Page 229 - is set to disable all interrupts.
209 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS (7) Enabling of level-two interrupts (enabling level-two INTT0 and INT0 interrupts with INTCSI and INT4 handled as level-one interrupts) <1> When an INTCSI interrupt not allowed to be a level-two interrupt occurs, the INTCSI service program starts, an...
Page 230 - Table 6-6 shows the signals which set test request flags.; Table 6-6. Signals Setting Test Request Flags
210 µPD750008 USER'S MANUAL 6.10 TEST FUNCTION 6.10.1 Test Sources The µPD750008 has two test sources. INT2 provides two types of edge-detection-test inputs. Table 6-5. Test Source Test source Internal/external INT2 (detection of the rising edge of the signal input to the INT2 pin or that of Externa...
Page 231 - Figure 6-10 shows the configuration of INT2 and KR0 to KR7.; (a) Detection of a rising edge on the INT2 input pin; IRQ2 is set when a rising edge is detected on the INT2 input pin.
211 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS (2) INT2 and key interrupt (KR0 to KR7) hardware Figure 6-10 shows the configuration of INT2 and KR0 to KR7. The IRQ2 set signal is output in either of the following edge detection modes, which is selected with the INT2 edge detection mode register (IM2). (...
Page 232 - Figure 6-10. Block Diagram of the INT2 and KR0 to KR7 Circuits
212 µPD750008 USER'S MANUAL Figure 6-10. Block Diagram of the INT2 and KR0 to KR7 Circuits INT2/P12 KR7/P73 KR6/P72 KR5/P71 KR4/P70 KR3/P63 KR2/P62 KR1/P61 KR0/P60 IM2 4 Input buffer Internal bus Selector Rising edge detection circuit Falling edge detection circuit INT2 (IRQ2 set signal) IM20, IM21
Page 235 - CHAPTER 7 STANDBY FUNCTION; function is available in the two modes: the STOP mode and HALT mode.; the power consumption of the entire system.
215 CHAPTER 7 STANDBY FUNCTION CHAPTER 7 STANDBY FUNCTION The µPD750008 provides a standby function to reduce the power consumption by the system. The standby function is available in the two modes: the STOP mode and HALT mode. Differences between these two modes are as follows: (1) STOP mode In the...
Page 236 - as required to change the CPU clock pulse have elapsed.; Caution; STOP mode cannot be used with a system that uses an external clock.
216 µPD750008 USER'S MANUAL 7.1 SETTING OF STANDBY MODES AND OPERATION STATUS Table 7-1. Operation Statuses in the Standby Mode Notes 1. Operation is possible only when the main system clock operates. 2. Operation is possible only when the noise eliminator is not selected by bit 2 of the edge detect...
Page 238 - BTM is to be set before the STOP mode is set.
218 µPD750008 USER'S MANUAL Figure 7-1. Standby Mode Release Operation (2/2) (c) Release of the HALT mode by RESET signal (d) Release of the HALT mode by the occurrence of an interrupt Note The following two wait times can be selected by a mask option: 2 17 /f X (21.8 ms at 6.00 MHz, 31.3 ms at 4.19...
Page 239 - instruction used to set the standby mode.; Wait time; Other than above
219 CHAPTER 7 STANDBY FUNCTION Table 7-2. Selection of a Wait Time with BTM Note This time does not include the time from the release of the STOP mode to the start of oscillation. Caution The wait times used when the STOP mode is released do not include the time (a in Figure7- 2) required before clo...
Page 242 -
222 µPD750008 USER'S MANUAL (2) Application of the HALT mode (at f X = 4.19 MHz) <Intermittent operation under the following conditions> • The main system clock is switched to the subsystem clock on the falling edge of INT4. • The oscillation of the main system clock is stopped, and HALT mode ...
Page 245 - CHAPTER 8 RESET FUNCTION; -1 shows the configuration of the reset circuit.; Figure 8-1. Configuration of Reset Functions; the reset operation timing.; Figure 8-2. Reset Operation by Generation of RESET Signal
225 CHAPTER 8 RESET FUNCTION CHAPTER 8 RESET FUNCTION The µPD750008 is reset with the external reset signal (RESET) or the reset signal received from the basic interval timer/watchdog timer. When either reset signal is input, the internal reset signal is generated. Figure 8-1 shows the configuration...
Page 249 - CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM); ultraviolet radiation cannot be performed.
229 CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM) CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM) The program memory in the µPD75P0016 consists of a one-time PROM (16384 x 8 bits). Writing to and verifying the contents of the one-time PROM is accomplished by using the pins shown ...
Page 250 - Remark X indicates L or H.
230 µPD75008 USER'S MANUAL 9.1 OPERATING MODES WHEN WRITING TO AND VERIFYING THE PROGRAM MEMORY If +6 V is applied to the V DD pin and +12.5 V is applied to the V PP pin, the µPD75P0016 enters program memory write/verify mode. The specific operating mode is then selected by the setting of the MD0 th...
Page 252 - READING THE PROGRAM MEMORY; by means of resistors. Bring X1 to low level.
232 µPD75008 USER'S MANUAL 9.3 READING THE PROGRAM MEMORY The procedure for reading the contents of program memory is described below. The read is performed in the verify mode. (1) Pull low all unused pins to V SS by means of resistors. Bring X1 to low level. (2) Apply 5 V to V DD and V PP . (3) Wai...
Page 253 - Storage Temperature
233 CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM) 9.4 SCREENING OF ONE-TIME PROM Because of its structure, it is difficult for NEC to completely test the one-time PROM product before shipment. It is therefore recommended that screening be performed to verify the PROM contents after the ne...
Page 255 - CHAPTER 10 MASK OPTION; The pins of the μPD750008 have the following mask options:; Table 10-1. Selecting Mask Option of Pin; Pin; The mask option can be specified in 1-bit units.; MASK OPTION OF STANDBY FUNCTION; The following two wait times can be selected:
235 CHAPTER 10 MASK OPTION CHAPTER 10 MASK OPTION 10.1 PIN The pins of the µPD750008 have the following mask options: Table 10-1. Selecting Mask Option of Pin Pin Mask Option P40-P43 Pull-up resistor can be connected in 1-bit units. P50-P53 P40 through P43 (port 4) or P50 through P53 (port 5) can be...
Page 256 - MASK OPTION FOR FEEDBACK RESISTOR OF SUBSYSTEM CLOCK
236 µPD750008 USER'S MANUAL 10.3 MASK OPTION FOR FEEDBACK RESISTOR OF SUBSYSTEM CLOCK For the subsystem clock of the µPD750008, whether to enable the feedback resistor is selected by the mask option. <1> Enable the feedback resistor (switches on or off by software). <2> Disable the feedb...
Page 257 - CHAPTER 11 INSTRUCTION SET; (4) GETI instruction for reducing program sizes; UNIQUE INSTRUCTIONS; (a) Subroutine call instruction for the entire space
237 CHAPTER 11 INSTRUCTION SET CHAPTER 11 INSTRUCTION SET The instruction set of the µPD750008 is an improved and extended version of the 75X series instruction set. This instruction set takes over the instruction set of the 75X series, having the following features: (1) Bit manipulation instruction...
Page 259 - An overflow is set in the carry flag.; Example An accumulator is added to memory data in decimal.; subtraction to number system m.
239 CHAPTER 11 INSTRUCTION SET 11.1.4 Number System Conversion Instructions An application may need to convert the result of a 4-bit data addition or subtraction (performed in binary) to a decimal number. A time-related application may require sexagesimal conversion. For this reason, the instruction...
Page 261 - For immediate data, a proper numeric value or label must be coded.
241 CHAPTER 11 INSTRUCTION SET 11.2 INSTRUCTION SET AND OPERATION (1) Operand identifier and description The operand field of an instruction must contain an operand coded according to the description rule for the operand identifier of the instruction. (Refer to RA75X Assembler Package User’s Manual:...
Page 263 - 0 indicates an addressable area.
243 CHAPTER 11 INSTRUCTION SET (3) Explanation of symbols used for the addressing area column Remarks 1. MB represents an accessible memory bank. 2. For * 2, MB = 0 regardless of the setting of MBE and MBS. 3. For * 4 and * 5, MB = 15 regardless of the setting of MBE and MBS. 4. Each of * 6 to * 10 ...
Page 264 - (4) Explanation of the machine cycle column; a skip operation. S assumes one of the following values:; Caution The GETI instruction is skipped in one machine cycle.; One machine cycle is equal to one cycle (t
244 µPD750008 USER'S MANUAL (4) Explanation of the machine cycle column S represents the number of machine cycles required when a skip instruction with the skip function performs a skip operation. S assumes one of the following values: • When no skip operation is performed: S = 0 • When a 1-byte ins...
Page 265 - Transfer
245 CHAPTER 11 INSTRUCTION SET In Mne- Number Machine Address- struc- monic Operation of cycle Operation ing Skip condition tion bytes area MOV A,#n4 1 1 A <– n4 String-effect A reg1,#n4 2 2 reg1 <– n4 XA,#n8 2 2 XA <– n8 String-effect A HL,#n8 2 2 HL <– n8 String-effect B rp2,#n8 2 2 rp...
Page 266 - MOVT; ADDS; Table reference
246 µPD750008 USER'S MANUAL In- Mne- Number Machine Address- struc- monic Operand of cycle Operation ing Skip condition tion bytes area MOVT XA,@PCDE 1 3 • µPD750004XA <– (PC 11-8 +DE) ROM • µPD750006, µPD750008XA <– (PC 12-8 +DE) ROM • µPD75P0016XA <– (PC 13-8 +DE) ROM XA,@PCXA 1 3 • µPD75...
Page 267 - Comparison; Carry flag
247 CHAPTER 11 INSTRUCTION SET In- Mne- Number Machine Address- struc- monic Operand of cycle Operation ing Skip condition tion bytes area AND A,#n4 2 2 A <– A n4 A,@HL 1 1 A <– A (HL) *1 XA,rp’ 2 2 XA <– XA rp’ rp’1,XA 2 2 rp’1 <– rp’1 XA OR A,#n4 2 2 A <– A n4 A,@HL 1 1 A <– A (H...
Page 268 - Memory bit manipulation
248 µPD750008 USER'S MANUAL In Mne- Number Machine Address- struc- monic Operand of cycle Operation ing Skip condition tion bytes area SET1 mem.bit 2 2 (mem.bit) <– 1 * 3 fmem.bit 2 2 (fmem.bit) <– 1 * 4 pmem.@L 2 2 (pmem 7-2 +L 3-2 .bit(L 1-0 )) <– 1 * 5 @H+mem.bit 2 2 (H+mem 3-0 .bit) <...
Page 269 - Branch; BR; Note The shaded portion is supported in Mk II mode only.
249 CHAPTER 11 INSTRUCTION SET Branch In Mne- Number Machine Address- struc- monic Operand of cycle Operation ing Skip condition tion bytes area BR addr — — • µPD750004 *6 PC 11-0 <– addr The assembler selects the mostadequate instruction frominstructions below.• BR !addr• BR $addr• BRCB !caddr •...
Page 271 - CALLA; Note 1. The shaded portion is supported in Mk II mode only.
251 CHAPTER 11 INSTRUCTION SET In Mne- Number Machine Address- struc- monic Operand of cycle Operation ing Skip condition tion bytes area BR BCXA 2 3 • µPD750004 *11 PC 11-0 <– BCXA Note 1 • µPD750006, µPD750008PC 12-0 <– BCXA Note 2 • µPD75P0016PC 13-0 <– BCXA Note 3 BRA Note 1 !addr1 3 3 ...
Page 272 - CALL; CALLF; Subroutine stack control
252 µPD750008 USER'S MANUAL In Mne- Number Machine Address- struc- monic Operand of cycle Operation ing Skip condition tion bytes area CALL Note !addr 3 3 • µPD750004 *6 (SP–3) <– MBE,RBE, 0, 0(SP–4)(SP–1)(SP–2) <– PC 11-0 PC 11-0 <– addr, SP <– SP–4 • µPD750006, µPD750008(SP–3) <– MB...
Page 273 - RET
253 CHAPTER 11 INSTRUCTION SET In Mne- Number Machine Address- struc- monic Operand of cycle Operation ing Skip condition tion bytes area CALLF Note !faddr 2 3 • µPD750004 *9 (SP–2) –> x, x, MBE,RBE(SP–6)(SP–3)(SP–4) <– PC 11-0 (SP–5) <– 0, 0, 0, 0PC 11-0 <– 0+faddr, SP <– SP–6 • µPD7...
Page 274 - RETS; RETI
254 µPD750008 USER'S MANUAL Subroutine stack control In Mne- Number Machine Address- struc- monic Operand of cycle Operation ing Skip condition tion bytes area RETS Note 1 3+S • µPD750004 Unconditionally MBE, RBE, 0, 0 <– (SP+1)PC 11-0 <– (SP)(SP+3)(SP+2) SP <– SP+4Then skip unconditionally...
Page 275 - supported in Mk I mode only.
255 CHAPTER 11 INSTRUCTION SET In Mne- Number Machine Address- struc- monic Operand of cycle Operation ing Skip condition tion bytes area RETI Note 1 1 3 • µPD7500040, 0, 0, 0 <– (SP+1)PC 11-0 <– (SP)(SP+3)(SP+2) PSW <– (SP+4)(SP+5), SP <– SP+6 • µPD750006, µPD7500080, 0, 0, PC 12 <– ...
Page 276 - Special
256 µPD750008 USER'S MANUAL In Mne- Number Machine Address- struc- monic Operand of cycle Operation ing Skip condition tion bytes area SEL RBn 2 2 RBS <– n (n=0 - 3) MBn 2 2 MBS <– n (n=0, 1, 15) GETI Note taddr 1 3 • µPD750004 *10 When the TBR instruction is usedPC 11-0 <– (taddr) 3-0 +(ta...
Page 277 - GETI
257 CHAPTER 11 INSTRUCTION SET Special In Mne- Number Machine Address- struc- monic Operand of cycle Operation ing Skip condition tion bytes area GETI Notes1, 2 taddr 1 3 • µPD750004 *10 When the TBR instruction is usedPC 11-0 <– (taddr) 3-0 +(taddr+1) 4 When the TCALL instruction is used(SP–6)(S...
Page 278 - : Immediate data for n4 or n8
258 µPD750008 USER'S MANUAL 11.3 INSTRUCTION CODES OF EACH INSTRUCTION (1) Explanations of the symbols for the instruction codes I n : Immediate data for n4 or n8 D n : Immediate data for mem B n : Immediate data for bit N n : Immediate data for n or IExxx T n : Immediate data for taddr x 1/2 A n : ...
Page 279 - The table below lists the second byte
259 CHAPTER 11 INSTRUCTION SET (2) Bit manipulation addressing instruction codes * 1 in the operand field indicates that there are three types of bit manipulation addressing, fmem.bit, pmem.@L, and @H+mem.bit. The table below lists the second byte * 2 of an instruction code corresponding to the abov...
Page 284 - FUNCTIONS AND APPLICATIONS OF THE INSTRUCTIONS; in Mk II mode. Read the following explanation.; How to read; II; Examples 1. The data 0BH is set in the accumulator.; Data to be output to port 3 is selected from 0 to 2.
264 µPD750008 USER'S MANUAL 11.4 FUNCTIONS AND APPLICATIONS OF THE INSTRUCTIONS This section explains functions and applications of the instructions. For the µPD750004, µPD750006, µPD750008, and µPD75P0016, usable instructions and their functions in Mk I mode are different from those in Mk II mode. ...
Page 285 - are processed as NOP instructions.
265 CHAPTER 11 INSTRUCTION SET MOV reg1,#n4 Function: reg1 <– n4 n4 = I 3-0 : 0-FH Transfers the 4-bit immediate data n4 to A register reg1 (X, H, L, D, E, B, C). MOV XA,#n8 Function: XA <– n8 n8 = I 7-0 : 00H-FFH Transfers the 8-bit immediate data n8 to register pair XA. The string effect can...
Page 287 - and transfers the data at the next address to the X register.
267 CHAPTER 11 INSTRUCTION SET MOV XA,mem Function: A <– (mem), X <– (mem+1) mem = D 7-0 : 00H-FEH Transfers the data at the data memory location addressed by the 8-bit immediate data mem to the A register, and transfers the data at the next address to the X register. An even address can be sp...
Page 289 - bit immediate data mem.
269 CHAPTER 11 INSTRUCTION SET XCH XA,@HL Function: A <–> (HL), X <–> (HL+1) Exchanges the contents of the A register with the data at the data memory location addressed by the HL register pair, and exchanges the contents of the X register with the data at the next memory address. Howeve...
Page 290 - ) exchanged with the contents of the DE register pair.
270 µPD750008 USER'S MANUAL 11.4.2 Table Reference Instructions MOVT XA,@PCDE Function: For the µPD750006 and µPD750008 XA <– ROM (PC 12-8 +DE) Transfers the low-order four bits of the table data in program memory to the A register, and the high-order four bits to the X register. The table data i...
Page 294 - Example The register pair is left-shifted.
274 µPD750008 USER'S MANUAL ADDS XA,#n8 Function: XA <– XA+n8 ; Skip if carry. n8 = I 7-0 : 00H-FFH Adds the 8-bit immediate data n8 to the contents of the XA register pair in binary, then skips the next instruction if the addition generates a carry. The carry flag is not affected. ADDS A,@HL Fun...
Page 295 - instruction is skipped.; Example Data memory is compared with register pair rp’.
275 CHAPTER 11 INSTRUCTION SET ADDC XA,rp’ Function: XA, CY <– XA+rp’+CY Adds the contents of register pair rp’ (XA, HL, DE, BC, XA’, HL’, DE’, BC’) together with the carry flag to the contents of the XA register pair in binary. If the addition generates a carry, the carry flag is set. If no carr...
Page 296 - Example The high-order two bits of an accumulator are set to 0.
276 µPD750008 USER'S MANUAL SUBS rp’1,XA Function: rp’1 <– rp’1+XA ; Skip if borrow Subtracts the contents of the XA register pair from the contents of register pair rp’1 (HL, DE, BC, XA’, HL’, DE’, BC’), then sets the result in register pair rp’1. If the subtraction generates a borrow, the immed...
Page 297 - Example The low-order three bits of an accumulator are set to 1.; pair, then sets the result in the A register.
277 CHAPTER 11 INSTRUCTION SET AND A,@HL Function: A <– A (HL) ANDs the contents of the A register with the data at the data memory location addressed by the HL register pair, then sets the result in the A register. AND XA,rp’ Function: XA <– XA rp’ ANDs the contents of the XA register pair wi...
Page 298 - pair, then sets the result in register pair rp’1.; Example The high-order four bits of an accumulator is inverted.; HL register pair, then sets the result in the A register.
278 µPD750008 USER'S MANUAL OR rp’1,XA Function: rp’1 <– rp’ XA ORs the contents of register pair rp’1 (HL, DE, BC, XA’, HL’, DE’, BC’) with the contents of the XA register pair, then sets the result in register pair rp’1. XOR A,#n4 Function: A <– A n4 n4 = I 3-0 : 0-FH Exclusive-ORs the conte...
Page 300 - register pair match the 4-bit immediate data n4.
280 µPD750008 USER'S MANUAL INCS mem Function: (mem) <– (mem)+1 ; Skip if (mem) = 0, mem = D 7-0 : 00H-FFH Increments the data at the data memory location addressed by the 8-bit immediate data mem. If the result of increment produces data that is 0, the immediately following instruction is skippe...
Page 301 - Clears the carry flag.; SKT CY
281 CHAPTER 11 INSTRUCTION SET SKE XA,@HL Function: Skip if A = (HL) and X = (HL+1) Skips the immediately following instruction if the contents of the A register match the data at the data memory location addressed by the HL register pair, and the contents of the X register match the data at the nex...
Page 303 - specified by the 8-bit immediate data mem is 1.
283 CHAPTER 11 INSTRUCTION SET Skips the immediately following instruction if the bit specified by the 2-bit immediate data bit at the address specified by the 8-bit immediate data mem is 1. SKT fmem.bit SKT pmem.@L SKT @H+mem.bit Function: Skip if (bit specified in operand) = 1 Skips the immediatel...
Page 304 - BR addr; Branches to the address specified by the immediate data addr.
284 µPD750008 USER'S MANUAL AND1 CY, fmem.bit AND1 CY, pmem.@L AND1 CY, @H+mem.bit Function: CY <– CY ^ (bit specified in operand) ANDs the content of the carry flag with the bit in data memory specified by bit manipulation addressing (fmem.bit, pmem.@L, @H+mem.bit), then sets the result in the c...
Page 305 - Branches to the address specified by the immediate data addr1.
285 CHAPTER 11 INSTRUCTION SET BR addr1 Function: For the µPD750008 PC 12-0 <– addr1 addr1 = 0000H-1FFFH Branches to the address specified by the immediate data addr1. This instruction is an assembler pseudo instruction, and the assembler automatically replaces this instruction with the BRA !addr...
Page 306 - block 1 instead of block 0 occurs.
286 µPD750008 USER'S MANUAL Remark "Function" in this section is applicable to the µPD750008 whose program counter consists of 13 bits (addr = 0000H to 1FFFH). However, this is also applicable to the µPD750004 whose program counter consists of 12 bits (addr = 0000H to 0FFFH), the µPD750006 w...
Page 307 - a branch to the next page instead of that page occurs.
287 CHAPTER 11 INSTRUCTION SET BR PCDE Function: For the µPD750008 PC 12-0 <– PC 12-8 + DE PC 7- 4 <– D, PC 3-0 <– E Branches to the address specified by the program counter whose low-order 8 bits (PC 7-0 ) have been replaced with the contents of the DE register pair. The high-order bits of...
Page 308 - BR BCDE; BR BCXA; of the B; TBR addr
288 µPD750008 USER'S MANUAL B C 3 0 0 D 3 0 E 3 0 11 8 7 4 3 0 12 PC BR BCDE Function: For the µPD750008 PC 12-0 <– BCDE Branches to the address specified by the program counter whose bits have been replaced with the contents of the B 0 , C, D, and E registers. BR BCXA Function: For the µPD750008...
Page 313 - The low-order part of a register pair (rp
293 CHAPTER 11 INSTRUCTION SET PUSH BS Function: (SP–1) <– MBS, (SP–2) <– RBS, SP <– SP–2 Saves the contents of the memory bank select register (MBS) and the register bank select register (RBS) to the data memory location (stack) addressed by the stack pointer (SP), then decrements SP. POP ...
Page 314 - DI IExxx; contents of the next port to the X register.; A number from 2 to 8 can be specified as n.
294 µPD750008 USER'S MANUAL DI IExxx Function: IExxx <– 0 xxx = N 5 , N 2-0 Resets an interrupt enable flag (IExxx) to 0 to disable an interrupt. (xxx = BT, CSI, T0, T1, W, 0, 1, 2, 4) 11.4.13 I/O Instructions IN A,PORTn Function: A <– PORTn n = N 3-0 : 0–8 Transfers the contents of the port s...
Page 320 - SOS register
300 µPD750008 USER'S MANUAL Item (2/2) SOS register Serial interface Feedback resistor cutflag (SOS.0) Sub-oscillator current cutflag (SOS.1) Register bank selection register(RBS) Standby release with INT0 Number of vectored interrupts Processor clock control register Power supply voltage Operating ...
Page 321 - APPENDIX B DEVELOPMENT TOOLS
301 APPENDIX B DEVELOPMENT TOOLS The following development tools are provided for the development of a system which employs the µPD750008. In the 75XL series, use the common relocatable assembler together with a device file of each model. Note These software products cannot use the task swap functio...
Page 322 - PROM programming tools
302 µPD750008 USER'S MANUAL PROM programming tools Note These software products cannot use the task swap function, which is available in MS-DOS Ver. 5.00 or later. Remark Operation of the PG-1500 controller is guaranteed only on the above host machines and OSs. Hardware Software Distribution media 3...
Page 323 - Debugging Tools; The following system is shown below.; Notes 1. Maintenance service only; Hardware; OS
303 Debugging Tools The in-circuit emulators (IE-75000-R and IE-75001-R) are provided to debug programs used for the µPD750008. The following system is shown below. Notes 1. Maintenance service only 2. To be ordered. 3. These software products cannot use the task swap function, which is available in...
Page 324 - OS for IBM PC; The following IBM PC OSs are supported.; O S; IBM DOS; Only English version is supported.
304 µPD750008 USER'S MANUAL OS for IBM PC The following IBM PC OSs are supported. O S Version PC DOS Ver. 3.1 to Ver. 6.3 J6.1/V Note to J6.3/V Note MS-DOS Ver. 5.0 to Ver. 6.22 5.0/V Note to J6.2/V Note IBM DOS TM J5.02/V Note Note Only English version is supported. Caution These software products ...
Page 325 - Development Tool Configuration
305 APPENDIX B DEVELOPMENT TOOLS Target sysytem Note 2 Emulation probe EP-75008CU-R EP-75008GB-R In-circuit emulator IE-75000-R or IE-75001-R Emulation board IE-75300-R-EM Note 1 Product containing PROM µPD75P0016CU PROM programmer PG-1500 + Programmer adapter PA-75P008CU RS-232-C Centronics interfa...
Page 329 - APPENDIX C MASKED ROM ORDERING PROCEDURE; <1> Advance notice of an order for masked ROM
309 APPENDIX C MASKED ROM ORDERING PROCEDURE After program development is completed, the masked ROM is ordered by the following procedure: <1> Advance notice of an order for masked ROM Give advance notice of masked ROM ordering to a special agent or NEC’s Sales Department, otherwise the ordere...
Page 331 - APPENDIX D INSTRUCTION INDEX
311 APPENDIX D INSTRUCTION INDEX D.1 INSTRUCTION INDEX (BY FUNCTION) [Transfer instructions] MOV A,#n4 ... 245, 264 MOV reg1,#n4 ... 245, 265 MOV XA,#n8 ... 245, 265 MOV HL,#n8 ... 245, 265 MOV rp2,#n8 ... 245, 265 MOV A,@HL ... 245, 265 MOV A,@HL+ ... 245, 265 MOV A,@HL– ... 245, 265 MOV A,@rpa1 .....
Page 337 - APPENDIX E HARDWARE INDEX; Pull-up resistor specification register
317 APPENDIX E HARDWARE INDEX E.1 HARDWARE INDEX (ALPHABETICAL ORDER WITH RESPECT TO THE HARDWARE NAME) [A] Acknowledge detection flag ... 132 Acknowledge enable bit ... 132 Acknowledge trigger bit ... 132 [B] Bank select register ... 65 Basic interval timer ... 99 Basic interval timer mode register...
Page 341 - APPENDIX F REVISION HISTORY
321 APPENDIX F REVISION HISTORY Major revisions in this edition are shown below. The revised chapters refer to this edition. Edition Major revisions from previous edition Revised chapters Second The 44-pin plastic QFP package was changed from All µPD750008GB-xxx-3B4 to µPD750008GB-xxx-3BS-MTX. The µ...
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