Intel PXA250 and PXA210 - Manuals

1-2 PXA250 and PXA210 Applications Processors Design Guide Introduction s The PXA250 applications processor package is: 256 pin, 17x17 mBGA – 32-bit functionality. The PXA210 applications processor package is: 225 pin, 13x13 MMAP – 16-bit functionality, a subset of the PXA250 applications processor ...

1-4 PXA250 and PXA210 Applications Processors Design Guide Introduction • I 2 C Controller pins • PWM pins • 2 dedicated GPIOs pins • Integrated JTAG support 1.2.2 Signal Pin Descriptions Table 1-3 defines the signal descriptions for the applications processor. Table 1-3. Signal Pin Descriptions (Sh...

PXA250 and PXA210 Applications Processors Design Guide 1-11 Introduction Figure 1-2. PXA250 Applications Processor

PXA250 and PXA210 Applications Processors Design Guide 1-15 Introduction Figure 1-3. PXA210 Applications Processor φ

PXA250 and PXA210 Applications Processors Design Guide 2-1 System Memory Interface 2 This section is the design guidelines for the system memory interface. 2.1 Overview The external memory bus interface for the applications processor supports: • 100 MHz SDRAM at 3.3 V • 100 MHz SDRAM at 2.5 V • Sync...

2-2 PXA250 and PXA210 Applications Processors Design Guide System Memory Interface Figure 2-1. General Memory Interface Configuration PXA250 Memory Controller Interface SDRAM Partition 0 SDRAM Partition 1 SDRAM Partition 2 SDRAM Partition 3 nSDCS<0> nSDCS<1> nSDCS<2> nSDCS<3>...

PXA250 and PXA210 Applications Processors Design Guide 2-3 System Memory Interface 2.2 SDRAM Interface The applications processor supports an SDRAM interface at a maximum frequency of 100 MHz. The SDRAM Interface supports four 16-bit or 32-bit wide partitions of SDRAM. Each partition is allocated 64...

PXA250 and PXA210 Applications Processors Design Guide 2-5 System Memory Interface 2.4 SDRAM Support Table 2-2 shows the SDRAM memory types and densities that are supported by the applications processor. . Table 2-2. SDRAM Memory Types Supported by the Applications Processor Partition Size (Mbyte/Pa...

2-6 PXA250 and PXA210 Applications Processors Design Guide System Memory Interface 2.5 SDRAM Address Mapping SDRAM Address Mapping is shown in Table 2-3 and Table 2-4 . Table 2-3. Normal Mode Memory Address Mapping SDRAM # Bits Bank x Row x Col The applications processor pin mapping to SDRAM devices...

PXA250 and PXA210 Applications Processors Design Guide 2-7 System Memory Interface 2.6 Static Memory 2.6.1 Overview The applications processor external memory bus interface supports the following static memory types: • Synchronous and asynchronous Burst mode and Page mode Flash • Synchronous Mask RO...

2-8 PXA250 and PXA210 Applications Processors Design Guide System Memory Interface Memory types are programmable through the memory interface configuration registers. Six chip selects control the static memory interface, nCS<5:0>. All are configurable for nonburst ROM or Flash memory, burst RO...

PXA250 and PXA210 Applications Processors Design Guide 2-9 System Memory Interface 2.6.3 SRAM / ROM / Flash / Synchronous Fast Flash Memory Options Table 2-7 contains the AC specification for SRAM / ROM / Flash / Synchronous Fast Flash. 2.6.4 Variable Latency I/O Interface Overview Both reads and wr...

PXA250 and PXA210 Applications Processors Design Guide 2-11 System Memory Interface 2.6.5 External Logic for PCMCIA Implementation The PXA250 applications processor requires external glue logic to complete the PCMCIA socket interface. Figure 2-4, “Expansion Card External Logic for a Two-Socket Confi...

2-12 PXA250 and PXA210 Applications Processors Design Guide System Memory Interface Figure 2-4. Expansion Card External Logic for a Two-Socket Configuration A8863-02 D(15:0) GPIO(w) GPIO(x) GPIO(y) GPIO(z) PSKTSEL MA(25:0) nPREG nPWAIT nPIOIS16 nPCE(1:2) nPOE, nPWE nPIOW, nPIOR PXA250 Applications P...

2-14 PXA250 and PXA210 Applications Processors Design Guide System Memory Interface 2.6.6 DMA / Companion Chip Interface Connect a companion chip to the applications processor via: • Alternate Bus Master Mode • Variable Latency I/O • Flow through DMA These connections are illustrated in Figure 2-6 a...

PXA250 and PXA210 Applications Processors Design Guide 2-15 System Memory Interface Figure 2-6. Alternate Bus Master Mode PXA250 Memory Controller Companion Chip External PXA250 EXTERNAL SYSTEM PXA250 GPIO Block M BREQ MB G N T GPIO<13> (MBGNT) GPIO<14> (MBREQ) SDRAM Bank 0 nSDCS(0) nWE ...

2-16 PXA250 and PXA210 Applications Processors Design Guide System Memory Interface Figure 2-7. Variable Latency I/O Companion Chip PXA250 EXTERNAL SYSTEM nCS(0,1,2,3,4,5) nPWE nOE RDY MD<31:0> MA<25:0> DQM<3:0> PXA250Memory Controller

PXA250 and PXA210 Applications Processors Design Guide 2-17 System Memory Interface 2.7 System Memory Layout Guidelines 2.7.1 System Memory Topologies (Min and Max Simulated Loading) Figure 2-8 , Figure 2-9 , Figure 2-10 , and Figure 2-11 are the topologies that where simulated to develop the trace ...

2-18 PXA250 and PXA210 Applications Processors Design Guide System Memory Interface 2.7.2 System Memory Recommended Trace Lengths Table 2-10 details the minimum and maximum trace lengths that were simulated for the applications processor. These trace lengths are not the absolute trace lengths that w...

PXA250 and PXA210 Applications Processor Design Guide 3-1 LCD Display Controller 3 This chapter describes sample hardware connections from the PXA250 applications processor to various types of LCD controllers. Active (TFT) as well as passive (DSTN) displays are discussed as well as single and dual p...

3-2 PXA250 and PXA210 Applications Processor Design Guide LCD Display Controller For passive displays, the pins described in Table 3-2 are required connections between the PXA250 applications processor and your LCD panel. 3.2.1 Typical Connections for Passive Panel Displays The following diagrams ar...

PXA250 and PXA210 Applications Processor Design Guide 3-3 LCD Display Controller 3.2.1.2 Passive Monochrome Single Panel Displays, Double-Pixel Data Figure 3-2 shows typical connections for a single-panel-monochrome passive display using double-pixel data mode. 3.2.1.3 Passive Monochrome Dual Panel ...

3-4 PXA250 and PXA210 Applications Processor Design Guide LCD Display Controller 3.2.1.4 Passive Color Single Panel Displays Figure 3-4 is a typical single-panel-color passive display connection. 3.2.1.5 Passive Color Dual Panel Displays Figure 3-5 is a typical dual-panel-color passive display conne...

PXA250 and PXA210 Applications Processor Design Guide 3-5 LCD Display Controller 3.3 Active (TFT) Displays Because data is sent to the panel as raw 16-bit pixel data, active displays require16 data pins in order to transfer the pixel data from the controller. All 16 data lines are also required to d...

3-6 PXA250 and PXA210 Applications Processor Design Guide LCD Display Controller 3.3.1 Typical connections for Active Panel Displays Figure 3-6, “Active Color Display Typical Connection” on page 7 shows a typical connection for an active panel display and should serve as a guide for designing system...

PXA250 and PXA210 Applications Processor Design Guide 3-7 LCD Display Controller Note: This example shows 6 red, 6 green and 6 blue bits on the LCD panel. However, different active display panels might have more or different data lines. Consult the LCD panel manufacturer’s datasheet for the actual d...

3-8 PXA250 and PXA210 Applications Processor Design Guide LCD Display Controller 3.5 Additional Design Considerations 3.5.1 Contrast Voltage Many displays, both active and passive, include a pin for adjusting the display contrast voltage. This is a variable analog voltage that is supplied to the pan...

PXA250 and PXA210 Applications Processor Design Guide 3-9 LCD Display Controller However, typical transfer rates are considerably less than 83 Mhz. For example, an 800x600 color active display running at 75 Hz requires a transfer rate of approximately 36 MHz. To determined this, calculate the number...

PXA250 and PXA210 Applications Processors Design Guide 4-1 USB Interface 4 4.1 Self Powered Device Figure 4-1 shows the USB interface connection for a self-powered device. The 0 ohm resistors are optional, and if not used, then connect USB UDC+ directly to the device UDC+ and connect USB UDC- direct...

4-2 PXA250 and PXA210 Applications Processors Design Guide USB Interface detected. When an interrupt occurs, software must read the GPIOn pin to determine if the cable is connected or not. GPIOn is 1 if the cable is connected or 0 if the cable is disconnected. If a USB connect is detected, then soft...

PXA250 and PXA210 Applications Processors Design Guide 5-1 MultiMediaCard (MMC) 5 The MultiMediaCard (MMC) is a low cost data storage and communication media. The MMC supports the translation protocol from a standard MMC or Serial Peripheral Interface (SPI) bus to an application bus. The MMC control...

5-2 PXA250 and PXA210 Applications Processors Design Guide MultiMediaCard (MMC) 5.1.2 How to Wire Notice in the example schematic ( Figure 5-1, “Applications Processor MMC and SDCard Signal Connections” on page 5-3 ) an SDCard socket is used. The signals on the socket are defined in Table 5-2 . As s...

5-4 PXA250 and PXA210 Applications Processors Design Guide MultiMediaCard (MMC) Three other signals shown on the connector are COMM and the mechanical switches write protect (WP) and card detect (CD). WP and CD are both connected to COMM via a mechanical switch inside the socket when a device is ins...

PXA250 and PXA210 Applications Processors Design Guide 5-5 MultiMediaCard (MMC) Warning: Connecting VSS2 to something other than the power supply ground violates The MultiMediaCard System Specification, Version 2.1. Because the MMC specification does not state that VSS1 and VSS2 must be connected in...

5-6 PXA250 and PXA210 Applications Processors Design Guide MultiMediaCard (MMC) 5.1.4 Pull-up and Pull-down Table 5-4 and Table 5-5 show the pull-up and pull-down resistors required for SDCard and MMC devices according to their respective specifications. 5.2 Utilized Features The applications proces...

PXA250 and PXA210 Applications Processors Design Guide 6-1 AC97 6 The AC97 controller unit (ACUNIT) connects audio chips and codecs to the applications processor. It uses a six-wire interface to transmit and receive data from AC97 2.0 compliant codecs. The AC97 port is a bidirectional, serial PCM di...

6-2 PXA250 and PXA210 Applications Processors Design Guide AC97 6.2 Layout Because of the analog/digital nature of the codecs, it is important that proper mixed-signal layout procedures be followed. Intel recommends you follow the layout recommendations given in your Codec datasheet. Some general re...

PXA250 and PXA210 Applications Processors Design Guide 7-1 I 2 C 7 The Inter-Integrated Circuit (I 2 C) bus interface unit lets the applications processor serve as a master and slave device residing on the I 2 C bus. The I 2 C bus is a serial bus developed by Philips Corporation consisting of a two-...

7-2 PXA250 and PXA210 Applications Processors Design Guide I2C 7.1.2 Digital-to-Analog Converter (DAC) Figure 7-1 shows the schematic for connecting the I 2 C interface to a Linear Technology micropower DAC. The DAC output is connected to the buck converter feedback path and is controlled by the I 2...

PXA250 and PXA210 Applications Processors Design Guide 7-3 I2C . 7.1.4 Pull-Ups and Pull-Downs The I 2 C Bus Specification, available from Philips Corporation, states: The external pull-up devices connected to the bus lines must be adapted to accommodate the shorter maximum permissible rise time for...

7-4 PXA250 and PXA210 Applications Processors Design Guide I2C The actual value of the pull-up is system dependant and a guide is presented in the I 2 C Bus Specification on determining the maximum and minimum resistors to use when the system is intended for standard or fast-mode I 2 C bus devices. ...

PXA250 and PXA210 Applications Processors Design Guide 8-1 Power and Clocking 8 8.1 Operating Conditions Table 8-1 shows voltage, frequency, and temperature specifications for the applications processor for four different ranges. The temperature specification for each range is constant; the frequenc...

8-2 PXA250 and PXA210 Applications Processors Design Guide Power and Clocking 8.2 Electrical Specifications Table 8-2 provides the Absolute Maximum ratings for the applications processor. These parameters may not be exceeded or the part may be permanently damaged. Operation at Absolute Maximum Ratin...

8-4 PXA250 and PXA210 Applications Processors Design Guide Power and Clocking 8.4 Oscillator Electrical Specifications The applications processor contains two oscillators – 32.768 kHz and 3.6864 MHz; each chosen for a specific crystal. When choosing a crystal, match the crystal parameters as closely...

PXA250 and PXA210 Applications Processors Design Guide 8-5 Power and Clocking To drive the 32.768 kHz crystal pins from an external source: • Drive the TEXTAL pin with a digital signal that has a low level near 0 V and a high level near VCC. Do not exceed VCC or go below VSS by more than 100 mV. The...

8-6 PXA250 and PXA210 Applications Processors Design Guide Power and Clocking • Drive the PEXTAL pin with a digital signal that has a low level near 0 V and a high level near VCC. Do not exceed VCC or go below VSS by more than 100 mV. The minimum slew rate is 1 V per 100 ns. The maximum current draw...

PXA250 and PXA210 Applications Processors Design Guide 8-11 Power and Clocking 8.5.2 Power On Timing The External Voltage Regulator and other power-on devices must provide the applications processor with a specific sequence of power and resets to ensure proper operation. This sequence is shown in Fi...

8-12 PXA250 and PXA210 Applications Processors Design Guide Power and Clocking Note: If Hardware Reset is entered during Sleep Mode, the proper power-supply stabilization times and nRESET timing requirements indicated in Table 8-7, “Power-On Timing Specifications” on page 8-12 must be observed. Figu...

PXA250 and PXA210 Applications Processors Design Guide 8-13 Power and Clocking 8.5.4 Watchdog Reset Timing Watchdog Reset is an internally generated reset and therefore has no external pin dependencies. The nRESET_OUT pin is the only indicator of Watchdog Reset, and it stays asserted for t DHW_OUT ....

8-14 PXA250 and PXA210 Applications Processors Design Guide Power and Clocking 8.5.6 Sleep Mode Timing Sleep Mode is internally asserted, and asserts the nRESET_OUT and PWR_EN signals. The sequence indicated in Figure 8-4 “Sleep Mode Timing” and detailed in Table 8-10, “Sleep Mode Timing Specificati...

PXA250 and PXA210 Applications Processors Design Guide 8-15 Power and Clocking 8.6 Memory Bus and PCMCIA AC Specifications This section gives the timing information for the following types of memory: • SRAM / ROM / Flash / Synchronous Fast Flash Asynchronous writes ( Table 8-11 ) • Variable Latency ...

8-20 PXA250 and PXA210 Applications Processors Design Guide Power and Clocking 8.7 Example Form Factor Reference Design Power Delivery Example 8.7.1 Power System Features of the example form factor reference design power system (example in Figure 8-5, “Example Form Factor Reference Design Power Syst...

PXA250 and PXA210 Applications Processors Design Guide 8-21 Power and Clocking • Provide power gating switches for the CF, LCD, backlight, RS-232, MMC, Radio, and audio amplifier subsystems • Provide a high-efficiency 5.5 V supply rail for LCD and other devices • Provide a high-efficiency 3.3 V supp...

8-22 PXA250 and PXA210 Applications Processors Design Guide Power and Clocking 8.7.2 CORE Power The example form factor reference design has a variable 0.8 V – 1.3 V core power supply for the applications processor. This voltage varies depending on the performance required by the application. A Line...

PXA250 and PXA210 Applications Processors Design Guide 8-23 Power and Clocking 8.7.4 I/O 3.3 V Power A simple LDO linear regulator supplies the 3.3V rail. The Analog Devices ADP3335 is chosen for its very low drop-out – 200 mV at 500 mA and 110 mV at 200 mA. So typically, the input cut-off voltage f...

PXA250 and PXA210 Applications Processors Design Guide 9-1 JTAG/Debug Port 9 9.1 Description The JTAG/Debug port is essentially several shift registers, with the destination controlled by the TMS pin and data I/O with TDI/TDO. nTRST provides initialization of the test logic. JTAG is testable via the...

A-2 PXA250 and PXA210 Applications Processors Design Guide SA-1110/Applications Processor Migration — Intel® XScale™ microarchitecture — Debugging - Cache attributes - Other Features - Conclusion A.1 SA-1110 Hardware Migration Issues A.1.1 Hardware Compatibility The majority of the features provided...

PXA250 and PXA210 Applications Processors Design Guide A-3 SA-1110/Applications Processor Migration The power fault (VDD_FAULT) and battery fault (BATT_FAULT) pins that drive the SA-1110 sleep mode are negated with respect to the PXA250 applications processor. You must invert these signals or change...

A-4 PXA250 and PXA210 Applications Processors Design Guide SA-1110/Applications Processor Migration A.1.3 Power Delivery Although both products are tolerant to 3.3 V inputs and outputs, there is a difference in the supply voltage that drives the transistors of the microprocessor megacell. The PXA250...

A-6 PXA250 and PXA210 Applications Processors Design Guide SA-1110/Applications Processor Migration A.2.1 Software Compatibility Because the PXA250 applications processor uses Intel® XScale™ microarchitecture, the PXA250 applications processor has a different pipeline length relative to the SA-1110....

PXA250 and PXA210 Applications Processors Design Guide A-7 SA-1110/Applications Processor Migration You must choose memory clocks, LCD clock rates, audio clocks and interfaces, which GPIOs are actually connected to hardware, and many more. There are no easy solutions here, the device space of the PX...

A-8 PXA250 and PXA210 Applications Processors Design Guide SA-1110/Applications Processor Migration A.3.1 Intel® XScale™ Microarchitecture The PXA250 applications processor is a system on a chip that includes Intel’s new microprocessor megacell. This includes Intel ® Superpipelined Technology and a ...

PXA250 and PXA210 Applications Processors Design Guide A-9 SA-1110/Applications Processor Migration Additional software is required to access these benefits. A similar story is true for AC’97, I2C, GPIOs, MMC and others. The benefits are substantial, but new hardware and software will be necessary t...

PXA250 and PXA210 Applications Processors Design Guide B-1 Example Form Factor Reference Design Schematic Diagrams B B.1 Notes The example form factor reference design schematics in this appendix have known issues and assumptions that need to be assessed for each board design. This appendix document...

PXA250 and PXA210 Applications Processors Design Guide C-1 BBPXA2xx Development Baseboard Schematic Diagram C C.1 Schematic Diagram The BBPXA2xx schematic is on the following pages.

BBPXA2xx Table of Contents Page Function Page Function Page Function 2 Top level block diagram 3 Processor Card Connector 4 Data Buffers/Transceivers 5 Data Buffers/Transceivers 6 Address BUFFERS/TRANSCEIVERS 7 SPX ADDRESS BUFFERS 8 CONTROL BUFFERS/TRANSCEIVERS 9 X ADDRESS BUFFERS 10 BFR ADDRESS BUF...

C-40 PXA250 and PXA210 Applications Processors Design Guide BBPXA2xx Development Baseboard Schematic Diagram

PXA250 and PXA210 Applications Processors Design Guide D-1 PXA250 Processor Card Schematic Diagram D D.1 Schematic Diagram The DCPXA250 processor card schematic is on the following pages.

DCPXA250 Processor Card 32-bit version 9-11 Bus Terminators 8 Visibility 7 VOLTAGE REGULATOR CONTROL CPLD AND I/O EXPANDER 6 JTAG CONNECTOR & PLL and CORE VOLTAGE REGULATORS 5 CLOCKS 4 CONNECTOR (MEMORY and I/O SIGNALS) 3 SDRAM 2 PROCESSOR --- PXA250 32-BIT PAGE FUNCTION TABLE OF CONTENTS

PXA250 and PXA210 Applications Processors Design Guide E-1 PXA210 Processor Card Schematic Diagram E E.1 Schematic Diagram The DCPXA210 processor card schematic is on the following pages.

DCPXA210 Processor Card 16-bit version TABLE OF CONTENTS PAGE FUNCTION 2 PROCESSOR --- PXA210 16-BIT 3 SDRAM 4 CONNECTOR (MEMORY and I/O SIGNALS) 5 CLOCKS 6 JTAG CONNECTOR & PLL and CORE VOLTAGE REGULATORS 7 VOLTAGE REGULATOR CONTROL CPLD AND I/O EXPANDER 8 Visibility 9-13 Bus Terminators and Si...

PXA250 and PXA210 Applications Processors Design Guide E-3 PXA210 Processor Card Schematic Diagram