Intel EP80579 - Manual

Intel EP80579

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Table of Contents:

  • Page 3 – Contents; Intel
  • Page 5 – Figures
  • Page 6 – Revision History
  • Page 7 – Introduction; What’s New in this Chapter
  • Page 8 – Related Information; For convenience, in this document; Reference Documents; Glossary; Table 3; Related Documents and Sample Code
  • Page 10 – Features Supported in this Release; Cryptographic API. For more details, see
  • Page 11 – Part 1: Architectural Overview; This section contains the following chapters:
  • Page 12 – Silicon Overview; Figure 1
  • Page 14 – Software Overview; Section 3.4, “Development View” on page 17
  • Page 15 – them accordingly. See; Logical View; illustrated in; Acceleration Firmware Layer; acceleration firmware.; Software for Intel
  • Page 16 – Figure 3; Infrastructure; Acceleration Access Layer and Acceleration APIs
  • Page 17 – Chapter 7.0, “ASD Module Architecture Overview”; Shim Layers; Development View; Table 4
  • Page 18 – Process View; and tasklet. They also document whether they are thread-safe.; Deployment View; Table 5
  • Page 20 – No updates in this release.; Feature List; The Intel; Symmetric Operations; Cipher; data is 16 byte blocks.; Partial Packets for Cipher and Hash/Authentication Commands
  • Page 21 – Authenticated-Encryption Commands
  • Page 22 – Key Generation; Random Number; RSA; Refer to
  • Page 23 – Lookaside Security Algorithms High Level Overview; recommended to reference the relevant RFC.; Lookaside Symmetric Overview; mode of operation is used.; E n c ry p tio n
  • Page 24 – Counter mode turns a block cipher into a stream cipher, as shown in; Figure 6; Counter Mode
  • Page 25 – A stream cipher operates on individual digits each one at a time.; passed into the algorithm.; CCM
  • Page 26 – GCM; excerpt from the GCM specification which can be accessed at:; TLS key negotiation and generation applications.; Lookaside PKE Overview; Diffie-Hellman Key Exchange; symmetric key cipher.
  • Page 27 – RSA Cryptographic Standard; provides security against adaptive chosen-ciphertext attacks.; Digital Signature Algorithm; in the verification process.; Prime Number Testing
  • Page 28 – Large Number; Lookaside Random Overview
  • Page 29 – QAT Access Layer Architecture Overview; Overview; shutdown afterwards also by the ASD.
  • Page 30 – Debug Component Architecture Overview; • No updates in this release.; Each of these features is described in more detail below.; Version Information; This version information consists of the following:; Liveness Detection
  • Page 31 – Data Structure Dump; Many of the software components in the Intel
  • Page 32 – ASD Module Architecture Overview; Configuration; Table 6
  • Page 33 – Cryptographic System Resource Variables
  • Page 34 – Boot Time Configuration Instructions; Example 1. Sample Configuration File
  • Page 35 – ASD Hardware Services; Interrupt Management Services; Table 8
  • Page 36 – The sequence diagram in; QAT-AL ISR Primitives
  • Page 37 – ISR Sequence Diagram
  • Page 38 – NCDRAM/CDRAM Interface; Development Board Environment; Table 9; Memory Region Definitions
  • Page 39 – IMCH; che
  • Page 40 – ACPI; which provides the equivalent to the EFI variables as outlined in; PCI L; MENCBASE; NCDRAM; ACPI Shared RAM Methods
  • Page 41 – Part 2: Using the API; “Related Documents and Sample Code” on page 8
  • Page 42 – Introduction to Use Cases; Lookaside Acceleration Model; QuickAssist Technology Cryptographic API”; for a
  • Page 43 – Programming Model; QuickAssist Technology API Conventions” on page 43; Memory Allocation and Ownership
  • Page 44 – Data Buffer Models; “Scatter Gather Lists” on page 44; Flat Buffers; Synchronous and Asynchronous Support; Asynchronous Operation
  • Page 45 – Other API Conventions; Asynchronous API and Function Completion Callbacks
  • Page 46 – Section; Callbacks” on page 45; Callback Data Structures; Completion Callbacks” on page 45
  • Page 47 – Return Codes; QuickAssist; Error Values for Other APIs
  • Page 48 – Debugging Applications; Management Interface Layer (MIL) Introduction; messages or debug messages may be lost.; Management Interface Layer Architecture Decomposition; User Space
  • Page 49 – Loading the MIL Application; MIL User Command Details
  • Page 50 – help; The help command lists all the user space commands available.; DebugEnable; command is invoked. Specifically, DebugEnable does the following:; Sequence Diagram for DebugEnable Command
  • Page 51 – DebugDisable; than DebugEnable from the user side.; Sequence Diagram for DebugDisable Command
  • Page 52 – VersionDumpAll; logged to the syslog file as specified in; Sequence Diagram for VersionDumpAll Command
  • Page 53 – and set it appropriately.; Sequence Diagram for setHC Command
  • Page 54 – SystemHealthCheck; and displays this information in the syslog file as shown in; Sequence Diagram for SystemHealthCheck Command
  • Page 55 – DataDump; Sequence Diagram for DataDump Command
  • Page 56 – APIs; Sequence Diagram for SetFileName Command; User; DCC
  • Page 58 – Using the Intel
  • Page 59 – random number generation.
  • Page 60 – Modes of Operation; Asynchronous mode is preferred for optimal performance.; Interrupt Operation; the interrupt and inform the Cryptographic API Library.
  • Page 61 – Interrupt Coalescing; Variables” on page 33; Engine and Priority Support; Symmetric Cryptographic API Data Flow
  • Page 62 – The asynchronous part is hidden from the user by means of a queue.; Symmetric Asynchronous Intel; Application or
  • Page 63 – operation and understands the message format to send to the SSU.; Symmetric Synchronous Intel
  • Page 64 – Data Format
  • Page 65 – Buffer List; A Buffer List is defined by the type CpaBufferList, defined in cpa.h.; Memory Management; Flat Buffer Diagram; Buffer; Buffer List Diagram
  • Page 66 – Endianness and Alignment; Cryptographic API Initialization and Shutdown; Initialization
  • Page 67 – Stop; Completion of an Operation; Session Initialization
  • Page 68 – Session Removal
  • Page 69 – Algorithm Chaining and Authenticated-Encryption
  • Page 70 – parameter mapping to the Cryptographic API.; Setting CpaCyKeyGenTlsOpData Structure Fields
  • Page 71 – Generate Random Data; for the callback parameter.; Asymmetric Operations; Test Prime Number; Sample code is provided for Prime-Test operation see
  • Page 72 – Diffie-Hellman Phase 1 Key and Phase 2 Private Key Generation
  • Page 73 – DSA Signature Verification
  • Page 74 – Using a Cryptographic Framework
  • Page 75 – Openswan and OpenSSL software suites.; Error Handling; shows; Cryptographic API Status Values
  • Page 76 – Appendix A NPF Copyright Notice; Section 10.0, “Programming Model” on page 43; NPF Copyright Notice; Implementation Agreements.
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Order Number: 320183-004US

Intel

®

EP80579 Software for

Security Applications on Intel

®

QuickAssist Technology

Programmer’s Guide

August 2009

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Summary

Page 3 - Contents; Intel

Intel ® EP80579 Software for Security Applications on Intel ® QuickAssist Technology August 2009 PG Order Number: 320183-004US 3 Contents—Security Software Contents 1.0 Introduction .............................................................................................................. 71.1 Wh...

Page 5 - Figures

Intel ® EP80579 Software for Security Applications on Intel ® QuickAssist Technology August 2009 PG Order Number: 320183-004US 5 Contents—Security Software 12.4 Data Format ..................................................................................................... 64 12.4.1 Flat Buffers .....

Page 6 - Revision History

Security Software—Revision History Intel ® EP80579 Software for Security Applications on Intel ® QuickAssist Technology PG August 2009 6 Order Number: 320183-004US 12 Debug APIs .............................................................................................................5613 Cryptogr...

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