Intel PXA250 and PXA210 - Manual

Intel PXA250 and PXA210

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Table of Contents:

  • Page 3 – Contents
  • Page 6 – Figures
  • Page 9 – PXA250 and PXA210 Applications Processors Design Guide; Introduction; Appendix B, “Example Form; Functional Overview; is a block diagram of the applications processor.; Revision History
  • Page 10 – Package Information; Package Introduction; Package features of the PXA250 applications processor are:; Figure 1-1. Applications Processor Block Diagram
  • Page 12 – Signal Pin Descriptions; defines the signal descriptions for the applications processor.
  • Page 19 – Figure 1-2. PXA250 Applications Processor
  • Page 23 – Figure 1-3. PXA210 Applications Processor
  • Page 27 – System Memory Interface; Overview; Figure 1-1, “Applications Processor Block Diagram” on page 1-2
  • Page 28 – Figure 2-1. General Memory Interface Configuration
  • Page 29 – SDRAM Interface; is a wiring diagram example that
  • Page 31 – SDRAM Support
  • Page 32 – SDRAM Address Mapping; SDRAM Address Mapping is shown in; Table 2-3. Normal Mode Memory Address Mapping
  • Page 33 – Static Memory; Synchronous and asynchronous Burst mode and Page mode Flash
  • Page 34 – Boot Time Defaults; shows valid booting configurations; Table 2-5. Valid Booting Configurations Based on Package Type
  • Page 35 – Variable Latency I/O Interface Overview
  • Page 37 – External Logic for PCMCIA Implementation; and; and V; PCMCIA is only implemented on the PXA250 applications processor.
  • Page 38 – Applications
  • Page 40 – DMA / Companion Chip Interface; Connect a companion chip to the applications processor via:
  • Page 41 – EXTERNAL SYSTEM
  • Page 42 – Companion
  • Page 43 – System Memory Layout Guidelines; are the topologies that where simulated to; MD
  • Page 44 – System Memory Recommended Trace Lengths; are measured from the applications; Table 2-10. Minimum and Maximum Trace Lengths for the SDRAM Signals
  • Page 45 – PXA250 and PXA210 Applications Processor Design Guide; LCD Display Controller; LCD Display Overview; well as which LCD data pins are used for which panel (upper or lower).
  • Page 46 – Typical Connections for Passive Panel Displays; Passive Monochrome Single Panel Displays; is a typical single-panel-monochrome passive display connection.
  • Page 47 – Passive Monochrome Single Panel Displays, Double-Pixel Data; is a typical dual-panel-monochrome passive display connection.; Connection; LCD Display
  • Page 48 – Passive Color Single Panel Displays
  • Page 49 – Figure 3-5. Passive Color Dual Panel Displays Typical Connection
  • Page 50 – Typical connections for Active Panel Displays; Figure 3-6, “Active Color Display Typical Connection” on page 7; the
  • Page 51 – Pinout; Figure 3-6. Active Color Display Typical Connection; LCD Panel; LCD Controller Ball Positions (Sheet 1 of 2)
  • Page 52 – Additional Design Considerations; Contrast Voltage; Use a shielded backlight inverter; Signal Routing and Buffering; LCD Controller Ball Positions (Sheet 2 of 2)
  • Page 53 – Panel Connector
  • Page 55 – USB Interface; Self Powered Device; Operation if GPIOn and GPIOx are Different Pins; USB GND
  • Page 56 – Operation if GPIOn and GPIOx are the Same Pin; Bus Powered Device
  • Page 57 – Schematics; Signal Description; MMC controller signal functions are described in
  • Page 58 – How to Wire; Notice in the example schematic (; Table 5-3. MMC Controller Supported Sockets and Devices
  • Page 60 – SDCard Socket; and CD has a pull-down resistor. This causes a rising edge on CD when a; MMC Socket; When using
  • Page 61 – Simplified Schematic
  • Page 62 – Utilized Features
  • Page 63 – The schematics for an AC97 connection are shown in
  • Page 64 – Layout
  • Page 65 – C Signal Description
  • Page 66 – Other Uses of I; C Interface
  • Page 67 – Figure 7-2. Using an Analog Switch to Allow a Second CF Card
  • Page 68 – The applications processor I
  • Page 69 – Power and Clocking; Operating Conditions
  • Page 70 – Electrical Specifications; Consumption Specifications” on page 8-3
  • Page 72 – Oscillator Electrical Specifications; kHz Oscillator Specifications
  • Page 73 – MHz Oscillator Specifications; To drive the 3.6864 MHz crystal pins from an external source:
  • Page 74 – Reset and Power AC Timing Specifications; Power On; Power Supply Connectivity
  • Page 79 – Power On Timing; and detailed in
  • Page 80 – Hardware Reset Timing; The timing sequences shown in; VCC; VCCN
  • Page 81 – Watchdog Reset Timing; for more information.; GPIO Reset Timing; Figure; Table 8-8. Hardware Reset Timing Specifications; nRESET
  • Page 82 – Sleep Mode Timing; Figure 8-4 “Sleep Mode Timing”; Table 8-9. GPIO Reset Timing Specifications
  • Page 83 – Memory Bus and PCMCIA AC Specifications; Synchronous Memories (
  • Page 88 – Power System; Battery voltage monitoring
  • Page 89 – Power System Configuration; . Note that there are
  • Page 90 – CORE Power
  • Page 91 – Peripheral 5.5 V Power
  • Page 93 – Description
  • Page 96 – SA-1110 Hardware Migration Issues; Hardware Compatibility; ROM select pin that selects a 16 or 32-bit interface
  • Page 97 – nWE
  • Page 98 – Power Delivery
  • Page 100 – Software Compatibility
  • Page 101 – DMA; Features
  • Page 102 – Intel® XScaleTM Microarchitecture
  • Page 103 – Conclusion
  • Page 105 – Notes; Page 10: U26 allows the CF card to access the I; Schematic Diagrams
  • Page 123 – Schematic Diagram; The BBPXA2xx schematic is on the following pages.
  • Page 124 – BBPXA2xx; Table of Contents; Page Function
  • Page 162 – BBPXA2xx Development Baseboard Schematic Diagram
  • Page 163 – The DCPXA250 processor card schematic is on the following pages.
  • Page 164 – DCPXA250 Processor Card; TABLE OF CONTENTS
  • Page 175 – The DCPXA210 processor card schematic is on the following pages.
  • Page 176 – DCPXA210 Processor Card
  • Page 189 – PXA210 Processor Card Schematic Diagram
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Intel

®

PXA250 and PXA210

Applications Processors

Design Guide

February, 2002

Order Number:

278523-001

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Summary

Page 3 - Contents

PXA250 and PXA210 Applications Processors Design Guide iii Contents Contents 1 Introduction................................................................................................................................. 1-1 1.1 Functional Overview ......................................................

Page 6 - Figures

vi PXA250 and PXA210 Applications Processors Design Guide Contents Figures 1-1 Applications Processor Block Diagram ...................................................................................... 1-21-2 PXA250 Applications Processor ...............................................................

Page 9 - PXA250 and PXA210 Applications Processors Design Guide; Introduction; Appendix B, “Example Form; Functional Overview; is a block diagram of the applications processor.; Revision History

PXA250 and PXA210 Applications Processors Design Guide 1-1 Introduction 1 This document presents design recommendations, board schematics, and debug recommendations for the Intel® PXA250 and PXA210 applications processors. The PXA250 applications processor is the 32-bit version of the device and the...

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