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Manual Intel IQ80321
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2 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS...
Board Manual 3 Intel ® IQ80321 I/O Processor Evaluation Platform Contents Contents 1 Introduction .................................................................................................................................. 13 1.1 Document Purpose and Scope ........................................
8 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Contents Figures 1 Intel ® 80321 I/O Processor Block Diagram ................................................................................ 16 2 Serial-UART Communication .................................................................
Board Manual 9 Intel ® IQ80321 I/O Processor Evaluation Platform Contents Tables 1 Intel ® 80321 I/O Processor Related Documentation List............................................................ 13 2 Electronic Information .............................................................................
Board Manual 11 Intel ® IQ80321 I/O Processor Evaluation Platform Contents Revision History Date Revision Description April 2003 008 Changed name and references of Tester1LED to Tester321LED. March 2003 007 Revised Appendix B, “Getting Started and Debugger” . Added Appendix C, “Getting Started and D...
12 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Contents This page intentionally left blank.
Board Manual 13 Introduction 1 1.1 Document Purpose and Scope This document describes the Intel ® IQ80321 Evaluation Platform Board. This platform is targeted for the Intel ® 80321 I/O processor (80321). The board serves as both an evaluation platform for developers using 80321 as well as a Customer...
14 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Introduction 1.3 Electronic Information 1.4 Component References Table 3 provides additional information on the major components of IQ80321. Table 2. Electronic Information Support Type Location/Contact The Intel World-Wide Web (WWW) ...
Board Manual 15 Intel ® IQ80321 I/O Processor Evaluation Platform Introduction 1.5 Terms and Definitions Table 4. Terms and Definitions Acronym/Term Definition ARM Refers to both the microprocessor architecture and the company that licenses it. CRB Customer Reference Board ICE In-Circuit Emulator – ...
18 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Introduction 1.7 Intel ® IQ80321 Evaluation Platform Board Features Table 5. Summary of Features Feature Definition Battery Backup Unit: Battery back up circuit for SDRAM – 64 MB for 72 hours. Ethernet Port: Gigabit Ethernet Debugging...
Board Manual 19 Getting Started 2 The IQ80321 is a software development environment for Intel ® 80321 I/O processor. 2.1 Kit Content The IQ80321 Kit contains the following items: • Intel ® IQ80321 Evaluation Platform Board • Code|Lab* Development Environment from Accelerated Technology Incorporated*...
20 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Getting Started 2.3 Factory Settings Make sure that the switch/jumper settings are set to proper positions as explained in Section 3.10, “Switches and Jumpers” on page 52 . 2.4 Development Strategy 2.4.1 Supported Tool Buckets For dev...
Board Manual 21 Intel ® IQ80321 I/O Processor Evaluation Platform Getting Started 2.5 Target Monitors 2.5.1 Redhat Redboot RedBoot* is an acronym for “Red Hat Embedded Debug and Bootstrap”, and is the standard embedded system debug/bootstrap environment from Red Hat, replacing the previous generatio...
22 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Getting Started 2.5.2 ARM Firmware Suite The ARM Firmware Suite is a package of low-level routines and libraries that have been designed to help developers rapidly bring up applications and operating systems on Intel ® XScale™ microar...
Board Manual 23 Intel ® IQ80321 I/O Processor Evaluation Platform Getting Started 2.5.2.1 ARM Angel Angel is one of the debug monitor programs for 80321. It is provided in source and binary form with the ARM Software Development Toolkit. It features: • Debug capability, including memory inspection, ...
24 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Getting Started 2.6 Host Communications Examples How to communicate to the host. 2.6.1 Serial-UART Communication Using a serial connection: 2.6.2 Ethernet-Network Communication Using a network connection: Figure 2. Serial-UART Communi...
Board Manual 25 Intel ® IQ80321 I/O Processor Evaluation Platform Getting Started 2.6.3 JTAG Debug Communication Using a JTAG Emulator: Figure 4. JTAG Debug Communication A9649-01 PCI/PCI-X Platform Server/Desktop/Backplane Intel ® 80321 I/O Processor Running a Debug Monitor SW Debugger Intel ® IQ80...
26 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Getting Started 2.6.4 GNUPro GDB/Insight 2.6.4.1 Communicating with Redboot Hardware Setup: • Host with UNIX/Linux or Win32 installed • Intel ® IQ80321 Evaluation Platform Board with serial cable • Redhat Redboot monitor Flashed to th...
28 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Getting Started 2.6.4.2 Connecting with GDB Below are the GDB commands entered from the command prompt. Be sure system path is set to access “xscale-elf-gdb.exe”. File name in example “hello”. Bold type represents input by user: >x...
Board Manual 29 Intel ® IQ80321 I/O Processor Evaluation Platform Getting Started 2.6.5 ARM Extended Debugger For further information on the AXD Debugger, refer to the content of the ARM ADS. This setup assumes that Angel is Flashed on the board: Description: Terminal emulator runs on host and commu...
Board Manual 31 Hardware Reference Section 3 3.1 Functional Diagram Figure 5 shows the functional block for the IQ80321. Figure 5. Functional Block Diagram A9517-01 Intel ® 80321 I/O Processor Intel ® 82544 Giga Ethernet Logic AnalyzerInterface Secondary PCI-X Expansion PC1600 DDR Memory Memory Batt...
32 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.2 Board Form-Factor/Connectivity Table 6 summarizes the form-factor and connectivity features for the IQ80321. Table 6. Form-Factor/Connectivity Features Description The Intel ® IQ80321 Evaluation Platform...
Board Manual 33 Intel ® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.3 Power The IQ80321 draws power from the PCI-X bus. The power requirements for the IQ80321 are shown in Table 7 below. The numbers do not include the power required by a PCI-X card mounted on the expansion...
34 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.4 Memory Subsystem Memory subsystem consists of the SDRAM as well as the Flash memory subsystems. 3.4.1 DDR SDRAM The DDR SDRAM interface consists of a 64-bit wide data path to support 1.6 GB/sec throughpu...
Board Manual 35 Intel ® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.4.2 Flash Memory Requirements Total Flash memory size is 8 MB. Table 10. Flash Memory Requirements Description Intel ® IQ80321 Evaluation Platform Board Total Flash size is 8 MB IQ80321 Flash technology is...
Board Manual 37 Intel ® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.6 Interrupt Routing The IQ80321 Interrupt routing. Figure 7. External Interrupt Routing to Intel ® 80321 I/O Processor A9450-02 XINT0 Intel ® 80321 I/O Processor INTA# Gigabit Ethernet UART Interrupt INTA#...
38 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.7 Intel ® IQ80321 Evaluation Platform Board Peripheral Bus The IQ80321 populates the peripheral bus as depicted by Figure 8 . The devices on the bus include Flash ROM, UART, HEX display, and rotary switch....
Board Manual 39 Intel ® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.7.1 Flash ROM Table 12. Flash ROM Features Description Flash is an Intel ® StrataFlash ® technology – Part number: 28F640 Flash size is 8 MB The connection to the peripheral bus is depicted by Figure 9 Fig...
40 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.7.2 UART Table 13. UART Features Description UART on the peripheral bus is part of the 16C550 family. The connection to the peripheral bus is depicted by Figure 10 . Figure 10. UART Connection on the Perip...
Board Manual 41 Intel ® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.7.3 HEX Display Table 14. HEX Display on the Peripheral Bus Description The Intel ® IQ80321 Evaluation Platform Board includes a HEX Display unit on the peripheral bus. The HEX display contains two digits ...
42 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.7.4 Rotary Switch The IQ80321 provides a Rotary Switch for the user to select from different boot-up flavors. Table 15. Rotary Switch Requirements Description Rotary switch has a 4-bit resolution (16 posit...
Board Manual 43 Intel ® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.7.5 Battery Status Table 16. Battery Status Buffer Requirements Description The Intel ® IQ80321 Evaluation Platform Board provides the following status for the battery: • Battery-Present status-bit on PB d...
44 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.8 Debug Interface 3.8.1 Console Serial Port The platform has one serial port for debug purposes as described in Section 3.7, “Intel ® IQ80321 Evaluation Platform Board Peripheral Bus” on page 38 . 3.8.2 Et...
Board Manual 45 Intel ® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.8.3 JTAG Debug The IQ80321 has a 20-pin JTAG connector that is in compliant with ARM Multi-ICE guidelines. 3.8.3.1 JTAG Port 3.8.4 Logic-Analyzer Connectors Warning: Be sure to fully understand the pin ass...
46 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.8.5 Mictor J3F2 Warning: Be sure to fully understand the pin assignments of the particular logic analyzer being used before connecting to the Intel ® IQ80310 Evaluation Platform Board. When voltage is appl...
Board Manual 47 Intel ® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.8.6 Mictor J2F1 Warning: Be sure to fully understand the pin assignments of the particular logic analyzer being used before connecting to the Intel ® IQ80310 Evaluation Platform Board. When voltage is appl...
48 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.8.7 Mictor J1C1 Warning: Be sure to fully understand the pin assignments of the particular logic analyzer being used before connecting to the Intel ® IQ80310 Evaluation Platform Board. When voltage is appl...
Board Manual 49 Intel ® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.8.8 Mictor J3C1 Warning: Be sure to fully understand the pin assignments of the particular logic analyzer being used before connecting to the Intel ® IQ80310 Evaluation Platform Board. When voltage is appl...
50 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.8.9 Mictor J2C1 Warning: Be sure to fully understand the pin assignments of the particular logic analyzer being used before connecting to the Intel ® IQ80310 Evaluation Platform Board. When voltage is appl...
Board Manual 51 Intel ® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.9 Board Reset Scheme Figure 15 depicts the reset scheme for the IQ80321. Table 23 list the reset schemes for the IQ80321. Table 23. Reset Requirements/Schemes Description Primary PCI reset, resets all devi...
52 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.10 Switches and Jumpers 3.10.1 Switch Summary Table 24. Switch Summary Switch Association Description Factory Default S7E1-1 - Spare Off S7E1-2 IOP RST_MODE: Sets IOP Reset-Mode operation Off S7E1-3 IOP RE...
Board Manual 53 Intel ® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.10.2 PCIX Initialization Summary Figure 16 shows a routing guidance on how PCI-X mode is determined/implemented on the secondary side of the PCI-X bridge. The Intel ® 80321 I/O processor (80321), GbE devic...
54 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.10.3 Default Switch Settings - Visual Table 25. Switch S7E1 Off Off Off a a. Use opposite settings when using an 80300-BP Backplane from Cyclone Micro Systems or most other PCI-X backplanes(switches S7E1-3...
Board Manual 55 Intel ® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.10.4 Jumper Summary 3.10.5 Connector Summary 3.10.6 General Purpose Input/Output Header The board has three programmable general-purpose I/O pins (GPIO 0-3 on the 80321). These pins are connected to a 6-pi...
Board Manual 57 Intel ® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.10.9 Detail Descriptions of Switches/Jumpers 3.10.9.1 Switch S7E1- 2/3 3.10.9.1.1 S7E1-2: RST_MODE RESET MODE is latched at the de-asserting edge of P_RST# and it determines when the 80321 is held in reset...
58 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.10.9.2 Switch S7E1- 4/5 3.10.9.2.1 Switch S7E1 - 4 This allows 80321 to hide the device in PCI-X Slot 1under GPIO control. 3.10.9.2.2 Switch S7E1 - 5 This allows 80321 to hide the GbE NIC under GPIO contro...
Board Manual 59 Intel ® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.10.9.4 Switch S7E1- 8 Table 45. Switch S7E1 - 8: Descriptions Switch Association Description Factory Default S7E1-8 SPCI-X Clock Enables SPCI-X clock circuit enable. Off Table 46. Switch S7E1 - 8: Settings...
60 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.10.9.5 Switch S8E1- 2 Turn On to enable on-board Gigabit Ethernet, otherwise Off for better PCI-X loading/performance. 3.10.9.6 Switch S8E1- 3 Close to enable bridge to be the arbiter. 3.10.9.7 Switch S8E1...
Board Manual 61 Intel ® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.10.9.8 Switch S8E1- 5 When this input is pulled high (off), the bridge changes the output impedance of the drivers to the opposite state than was assumed by default, as shown in Table 54 below: 3.10.9.9 Sw...
62 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.10.9.10 Switch S8E1- 7 Used to enable the IDSEL reroute function at reset or power-up. The reset value of the secondary bus private device mask register is modified according to the tie value of the IDSEL_...
Board Manual 63 Intel ® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.10.9.12 Switch S8E2 - 1/2 This feature forces the PCI-X Capability pins for the expansion slot to force a configuration on the Secondary PCI-X bus. 3.10.9.13 Switch S8E2 - 4 Table 62. Switch S8E2 - 1/2: De...
64 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.10.9.14 Switch S9E1 - 1:3 3.10.9.15 Switch S9E1 - 4 Table 66. Switch S9E1 - (1:3) Descriptions Switch Association Description Factory Default S9E1-1:3 PCI-X Bridge PCIXCAP: Set Primary PCI-X capability for...
Board Manual 67 Intel ® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.10.9.22 Jumper J9E1 Base Address Register Enable: Used to enable the base address register at reset or power-up. The 64-bit register located at offsets x'10' and x'14' is used to claim a 1 MB memory region...
Board Manual 69 External RAID Section 4 The IQ80321 provides the capability for the user to develop RAID applications. There is a requirement to provide the ability of making the secondary PCI-X devices private and the ability to route the interrupt lines. The following requirements describe this ca...
70 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform External RAID Section 4.2 Interrupt Routing The interrupt lines for devices on the SPCI-X bus (Expansion Slot and Intel ® 82544 Gigabit Ethernet Controllerr) are routed based on requirements. Table 87. Interrupt Routing for Secondary ...
Board Manual 71 Software Reference 5 5.1 DRAM For DDR SDRAM Sizes and Configurations, see section 7.2.2.1, table 139 of theIntel ® 80321 I/O Processor Developer ’s Manual. Table 89 provides DDR SDRAM Address Register Definitions, while this sections also contains multiple examples of Address Registe...
72 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Software Reference 5.2.1 Flash ROM The Flash ROM is an 8 MB Intel ® StrataFlash ® (part# 38F640) that sits on the Peripheral Bus and is accessed using PCE0. Under normal operation, the very first instruction access by the Intel ® XSca...
Board Manual 73 Intel ® IQ80321 I/O Processor Evaluation Platform Software Reference 5.2.2 UART The UART is a TL16C550C. It sits on the Peripheral Bus and is accessed using PCE1 and XINT1# as shown in Figure 20 : See datasheet at the following link for more information and a pin layout of this devic...
74 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Software Reference 5.2.4 HEX Display The HEX Display is an Agilent* HDSP-G211, which allows for monitoring of two digits. It sits on the Peripheral Bus and is accessed using PCE2 and PCE3 as shown here: Redboot* uses address range 0xF...
76 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Software Reference 5.3 Ethernet The 82544EI utilizes a 32/64-bit, 33/66 MHz direct-interface to the PCI bus. The controller interfaces with the 80321 through on-chip command/status registers and using a shared memory area. The intende...
Board Manual 77 Intel ® IQ80321 I/O Processor Evaluation Platform Software Reference 5.4 Board Support Package (BSP) Examples Examples provided in this section are based on the Red Hat* Redboot software running on the IQ80321 board. 5.4.1 Intel ® 80321 I/O Processor Memory Map Figure 25 depicts the ...
Board Manual 79 Intel ® IQ80321 I/O Processor Evaluation Platform Software Reference 5.4.3 Redboot Intel ® IQ80321 Physical Memory Map - Visual Figure 26. Redboot Intel ® IQ80310 Physical Memory Map ATU Outbound Translation Window ATU Outbound Direct Addressing Window Battery Status (R) Rotary Switc...
Board Manual 81 Intel ® IQ80321 I/O Processor Evaluation Platform Software Reference 5.4.5 Redboot Intel ® IQ80321 Files Attached in the kit, find a copy of the Red Hat eCos for Intel ® 80321 I/O processorr CD. Once the CD is installed, you may find: • • The Redboot initialization code source files ...
82 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Software Reference 5.4.6 Redboot Intel ® IQ80321 DDR Memory Initialization Sequence In order to set the correct ECC bits, a DDR memory system (DIMM or discrete components) must be written to with a known value. This process requires 6...
Board Manual 83 Intel ® IQ80321 I/O Processor Evaluation Platform Software Reference 5.4.7 Redboot Switching • S8E1-2 ON: Enable GbE on the SPCI-X Bus. • S8E1-7 OFF: PCI-X Bridge hides devices using Private Space Address lines. • S4D1 ON-OFF-ON-OFF: GbE and Expansion Slot Private Space. All other sw...
Board Manual 85 IQ80310 and IQ80321 Comparisons A This appendix provides a brief description for differences between IQ80321 and IQ80310. Please also refer to application note: Migrating from the Intel ® 80310 I/O Processor Chipset to the Intel ® 80321 I/O Processor Application Note 273562. Table 90...
Board Manual 87 Getting Started and Debugger B B.1 Introduction This appendix pertains to Code|Lab version 2.2 and earlier, which uses the Microsoft Visual Studio 6.0. For Code|Lab version 2.3 and later, refer to Appendix C, “Getting Started and Debugger” . B.1.1 Purpose The purpose of this appendix...
88 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger B.1.4 Related Web Sites • Macraigor: http://www.ocdemon.net/ • http://developer.intel.com/design/intelxscale/dev_tools/020523/index.htm • http://developer.intel.com/design/iio/80321.htm • http://developer....
Board Manual 89 Intel ® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger B.2 Setup B.2.1 Hardware Setup Use Figure 28 and the rest of the Intel ® IQ80321 Evaluation Platform Board Manual, to set up the hardware. • Connect the Raven to the host via the parallel port and to the e...
90 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger B.2.2 Software Setup ATI Code|Lab is a plug-in to Microsoft Visual Studio 6.0; therefore, Microsoft Visual Studio 6.0 must be installed on the host system before installing ATI Code|Lab. To load ATI Code|L...
Board Manual 91 Intel ® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger B.3 New Project Setup B.3.1 Creating a New Project 1. Launch Code|Lab EDE and select “Tools/Customize/Add-ins/Macro Files”. a. Check “Code|Lab EDE” and click Close. 2. Select “File/New…/Project”, then “Cod...
92 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger B.3.2 Configuration On the tool bar, click on the icon that looks like a file folder with the letters “EDE” on it. When the mouse arrow is placed on it, a text box displays “Project Settings”. Note: There ...
Board Manual 93 Intel ® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger B.4 Flashing with JTAG B.4.1 Overview Code|Lab and the Raven are capable of reading from, writing to, and erasing the contents of the Flash on the evaluation board. The board comes with RedBoot loaded in t...
94 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger B.4.2 Using Flash Programmer Note: The parallel port must be set to EPP mode or the Macraigor Raven will not work properly. Download the RedBoot executable files from the following location: http://develop...
Board Manual 95 Intel ® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger B.5 Debugging Out of Flash JTAG debuggers can be used on two levels; with or without the source code. When the Flash is programmed, the debugger can monitor the executable code, halt it, step through it, a...
96 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger B.7 Running the Code|Lab Debugger This section is provided to get the system up and running in the Code|Lab Debug environment, but it is not intended as a full-functional tutorial. Please refer to the ATI ...
Board Manual 97 Intel ® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger B.7.2 Manually Loading and Executing an Application Program 1. Launch the Code|Lab Debug Environment from the desktop icon. 2. Ensure “File…/Program Load Options/Load Executable and Symbols” is checked. 3....
98 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger B.7.4 Using Breakpoints Note the small gray circles on the sidebar beside each line of source code. Single-click any of these gray circles and a red dot appears. The red dot represents a break point. Singl...
Board Manual 99 Intel ® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger B.7.5 Stepping Through the Code The “led.c” file contains a function that is called from code in “blink.c”. Tis exercise steps through the code and utilizes a few of the most common step tools. 1. Launch t...
100 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger B.8 Exploring the Code|Lab Debug Windows This section discusses some basics of the debug environment. Some of these windows and concepts have been dealt with during previous exercises in this manual. Howe...
Board Manual 101 Intel ® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger B.8.6 Registers Window Close all the active windows, then bring up the Registers window. Resize the this window and its columns to get a good view of all the registers. Notice that there is a Flags tab at...
102 Board Manual Intel ® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger B.9 Debugging Basics B.9.1 Overview Debuggers allow developers to interrogate application code by allowing program flow control, data observation, and data manipulation. The flow control functions include...
Board Manual 113 Intel ® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger C.5 Debugging Out of Flash JTAG debuggers can be used on two levels; with or without the source code. When the Flash is programmed, the debugger can monitor the executable code, halt it, step through it, ...
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