Page 3 - Contents; Intel
D15343-003 3 Contents Contents 1.0 Introduction .................................................................................................................................... 111.1 Overview ...........................................................................................................
Page 7 - Figures; Tables
D15343-003 7 Contents Figures 1 Intel® 854 Chipset system block diagram (Native Graphic mode) ............................................. 16 2 Configuration Address Register .................................................................................................. 45 3 Configuration Data R...
Page 9 - Revision History
D15343-003 9 Contents Revision History § § Date Revision Description March 2005 1.0 Initial release of this document. June 2005 2.0 Add support for Genuine Intel® Processor at 1.2 GHz and Genuine Intel® Processor at 1.5 GHz technology.
Page 11 - Introduction; Overview; Figure 1; Processor/Host Bus Support
Introduction D15343-003 11 1.0 Introduction This document is the datasheet for the Intel ® 82854 Graphics Memory Controller Hub (GMCH). 1.1 Overview The Intel ® 854 chipset is a combination of the Intel ® 82854 Graphics Memory Controller Hub (GMCH) (Graphics Memory Controller Hub) and ICH4-M (I/O Co...
Page 12 - System Interrupts
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 12 D15343-003 System Interrupts • Supports Intel 8259 and front side bus interrupt delivery mechanism • Supports interrupts signaled as upstream memory writes from PCI and Hub interface • MSI sent to the CPU through the system bus • IOxAPIC in ICH4...
Page 13 - Display
Introduction D15343-003 13 Display • Analog display support — 350-MHz integrated 24-bit RAMDAC that can drive a standard progressive scan analog monitor with pixel resolution up to 1600x1200 at 85 Hz and up to 2048x1536 at 75 Hz • Dual independent pipe support — Concurrent: different images and disp...
Page 15 - Hub Interface to ICH4-M
Introduction D15343-003 15 — Dithering — Line and full-scene anti-aliasing — 16- and 24-bit Z buffering — 16- and 24-bit W buffering — 8-bit Stencil buffering — Double and triple render buffer support — 16- and 32-bit color — Destination alpha — Vertex cache — Optimal 3D resolution supported — Fast ...
Page 16 - Package; Intel® 854 Chipset system block diagram (Native Graphic mode)
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 16 D15343-003 Package 732-pin Micro-FCBGA (37.5 x 37.5 mm) Figure 1. Intel® 854 Chipset system block diagram (Native Graphic mode) Intel ® Celeron ® M Processor SIO PS/2 Serial FWH Intel ® 82801DBM (ICH4-M) Audio Codec AC Link LPC PCI Slots LANPHY ...
Page 17 - Terminology; Terms and Descriptions
Introduction D15343-003 17 1.2 Terminology Table 1. Terms and Descriptions Term Description AGTL+ Advanced Gunning Transceiver Logic + (AGTL+) bus BLI Backlight Inverter Core The internal base logic in the Intel ® 82854 GMCH CPU Central Processing Unit CRT Cathode Ray Tube DBI Dynamic Bus inversion ...
Page 19 - Reference Documents
Introduction D15343-003 19 1.3 Reference Documents Table 2. Reference Documents Document Location Intel® Celeron® M Processor Datasheet http://www.intel.com/design/mobile/datashts/300302.htm Ultra Low Voltage Intel(R) Celeron(R) M Processor at 600 MHz Addendum to the Intel(R) Celeron(R) M Processor ...
Page 21 - System Architecture
Intel ® 82854 GMCH Overview D15343-003 21 2.0 Intel ® 82854 GMCH Overview 2.1 System Architecture The Intel ® 82854 GMCH includes a processor interface, DDR SDRAM interface, display interface, and Hub interface. Combined with the ULV Intel® Celeron® M Processor or Genuine Intel® Processor, and an IC...
Page 22 - Processor Host Interface; DDR SDRAM Memory Capacity
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 22 D15343-003 2.2 Processor Host Interface The Intel ® 82854 GMCH supports the Intel Celeron M Processor, and Genuine Intel Processor. Key features of the front side bus (FSB) are: • Support for a 400-MHz system bus frequency. • Source synchronous ...
Page 23 - Graphics Features; GMCH Analog Display Port; Figure 8
Intel ® 82854 GMCH Overview D15343-003 23 The GMCH system memory architecture is optimized to maintain open pages (up to 16-KB page size) across multiple rows. As a result, up to 16 pages across four rows is supported. To complement this, the GMCH will tend to keep pages open within rows, or will on...
Page 24 - Hub Interface
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 24 D15343-003 2.6 Hub Interface A proprietary interconnect connects the GMCH to the ICH4-M. All communication between the GMCH and the ICH4-M occurs over the Hub interface 1.5. The Hub interface runs at 66 MHz (266-MB/s). 2.7 Address Decode Policie...
Page 25 - GMCH Clocking; The GMCH has the following clock input/output pins:
Intel ® 82854 GMCH Overview D15343-003 25 2.8 GMCH Clocking The GMCH has the following clock input/output pins: • 400-MHz, spread spectrum, low voltage differential BCLK, BCLK# for front side bus (FSB) • 66-MHz, 3.3-V GCLKIN for Hub interface buffers • Six pairs of differential output clocks (SCK[5:...
Page 27 - Signal Description; This section describes the Intel
Signal Description D15343-003 27 3.0 Signal Description This section describes the Intel ® 82854 GMCH signals. These signals are arranged in functional groups according to their associated interface. The following notations are used to describe the signal type. The signal description also includes t...
Page 28 - Host Interface Signals; Host Interface Signal Descriptions
Intel ® 854 Graphics Memory Controller Hub (GMCH) 28 D15343-003 3.1 Host Interface Signals Table 5. Host Interface Signal Descriptions Signal Name Type Description ADS# I/O AGTL+ Address Strobe: The system bus owner asserts ADS# to indicate the first of two cycles of a request phase. The GMCH can as...
Page 31 - DDR SDRAM Interface; DDR SDRAM Interface Descriptions
Signal Description D15343-003 31 3.2 DDR SDRAM Interface Table 6. DDR SDRAM Interface Descriptions Signal Name Type Description SCS[3:0]# O SSTL_2 Chip Select: These pins select the particular DDR SDRAM components during the active state. NOTE: There is one SCS# per DDR-SDRAM Physical DDR DIMM devic...
Page 32 - Hub Interface Signals
Intel ® 854 Graphics Memory Controller Hub (GMCH) 32 D15343-003 3.3 Hub Interface Signals Table 7. Hub Interface Signals SMAB[5,4,2,1] O SSTL_2 Memory Address Copies: These signals are identical to SMA[5,4,2,1] and are used to reduce loading for selective CPC(clock-per-command). These copies are not...
Page 33 - Clocks; Clock Signals
Signal Description D15343-003 33 3.4 Clocks Table 8. Clock Signals Signal Name Type Description Host Processor Clocking BCLK BCLK# I CMOS Differential Host Clock In: These pins receive a buffered host clock from the external clock synthesizer. This clock is used by all of the GMCH logic that are in ...
Page 35 - Internal Graphics Display Signals; Digital Video Output B (DVOB) Port Signal Descriptions
Signal Description D15343-003 35 3.5 Internal Graphics Display Signals The IGD has support for DVOB/C interfaces, and an Analog CRT port.Digital Video Output B (DVOB) Port. 3.5.1 Digital Video Output B (DVOB) Port Table 9. Digital Video Output B (DVOB) Port Signal Descriptions Name Type Description ...
Page 36 - Digital Video Output C (DVOC) Port Signal Descriptions
Intel ® 854 Graphics Memory Controller Hub (GMCH) 36 D15343-003 3.5.2 Digital Video Output C (DVOC) Port Table 10. Digital Video Output C (DVOC) Port Signal Descriptions Name Type Description DVOCD[11:0] O DVO [Native Graphic Mode] DVOC Data : This data bus is used to drive 12-bit RGB data on each e...
Page 37 - DVOB and DVOC Port Common Signal Descriptions; Analog CRT Display; Analog CRT Display Signal Descriptions
Signal Description D15343-003 37 Table 11. DVOB and DVOC Port Common Signal Descriptions 3.5.3 Analog CRT Display Table 12. Analog CRT Display Signal Descriptions Name Type Description DVOBCINTR# I DVO DVOBC Interrupt : This pin is used to signal an interrupt, typically used to indicate a hot plug o...
Page 38 - General Purpose Input/Output Signals; GPIO Signal Descriptions
Intel ® 854 Graphics Memory Controller Hub (GMCH) 38 D15343-003 3.5.4 General Purpose Input/Output Signals Table 13. GPIO Signal Descriptions GPIO I/F Total Type Comments RSTIN# I CMOS Reset: Primary Reset, Connected to PCIRST# of ICH4-M. PWROK I CMOS Power OK : Indicates that power to GMCH is stabl...
Page 39 - Voltage References, PLL Power
Signal Description D15343-003 39 3.6 Voltage References, PLL Power Table 14. Voltage References, PLL Power Signal Name Type Description Host Processor HXRCOMP Analog Host RCOMP: Used to calibrate the Host AGTL+ I/O buffers. HYRCOMP Analog Host RCOMP: Used to calibrate the Host AGTL+ I/O buffers. HXS...
Page 41 - Register Description; Function #1: DDR SDRAM Interface Registers; Device Number Assignment
Register Description D15343-003 41 4.0 Register Description 4.1 Conceptual Overview of the Platform Configuration Structure The GMCH and ICH4-M are physically connected by a Hub interface. From a configuration standpoint, the Hub interface is logically PCI bus #0. As a result, all devices internal t...
Page 42 - provides the nomenclature for the access attributes.; Nomenclature for Access Attributes
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 42 D15343-003 4.2 Nomenclature for Access Attributes Table 16 provides the nomenclature for the access attributes. Table 16. Nomenclature for Access Attributes A physical PCI Bus #0 does not exist. The Hub interface and the internal devices in the ...
Page 43 - Standard PCI Bus Configuration Mechanism; PCI Bus #0 Configuration Mechanism
Register Description D15343-003 43 4.3 Standard PCI Bus Configuration Mechanism The PCI Bus defines a slot based “configuration space” that allows each device to contain up to eight functions with each function containing up to 256, 8-bit configuration registers. The PCI Specification defines two bu...
Page 44 - Primary PCI and Downstream Configuration Mechanism; Register Definitions; I/O Mapped into the CPU I/O Space, which control access to PCI; Internal Configuration registers:; residing within the GMCH, they are partitioned into two; Internal Memory Mapped Configuration registers:; reside in the GMCH Device #2 that controls the Integrated Graphics; Reserved Bits
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 44 D15343-003 4.4.2 Primary PCI and Downstream Configuration Mechanism If the Bus Number in the CONFIG_ADDRESS is non-zero, the GMCH will generate a Type 1 Hub interface Configuration Cycle. A[1:0] of the Hub interface request packet for the Type 1...
Page 45 - CONFIG_ADDRESS – Configuration Address Register; Configuration Address Register; Reserved
Register Description D15343-003 45 system initialization software (usually BIOS) to properly determine the DDR SDRAM configurations, operating parameters, and optional system features that are applicable and to program the GMCH registers accordingly. 4.6 I/O Mapped Registers The GMCH contains two re...
Page 47 - CONFIG_DATA – Configuration Data Register; Configuration Data Register; Configuration Data Window
Register Description D15343-003 47 4.6.2 CONFIG_DATA – Configuration Data Register CONFIG_DATA is a 32-bit Read/Write window into Configuration Space. The portion of Configuration Space that is referenced by CONFIG_DATA is determined by the contents of CONFIG_ADDRESS. I/O Address:Default Value:Acces...
Page 48 - VGA I/O Mapped Registers; lists direct CPU Access registers and; VGA I/O Mapped Register List
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 48 D15343-003 4.7 VGA I/O Mapped Registers If Native Graphics mode is strapped, and Device #2 is enabled, and Function #0 within Device #2 is enabled for VGA, and IO_EN is set within Function #0 then GMCH claims a set of I/O registers for legacy VG...
Page 51 - VID – Vendor Identification Register
Register Description D15343-003 51 4.8.1 VID – Vendor Identification Register The VID Register contains the vendor identification number. This 16-bit register, combined with the Device Identification Register, uniquely identifies any PCI device. Writes to this register have no effect. 4.8.2 DID – De...
Page 52 - PCICMD – PCI Command Register
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 52 D15343-003 4.8.3 PCICMD – PCI Command Register Since GMCH Device #0 does not physically reside on PCI_A many of the bits are not implemented. Address Offset:Default Value:Access:Size: 04-05h0006hRead only, Read/Write16 bits Bit Descriptions 15:1...
Page 53 - PCI Status Register
Register Description D15343-003 53 4.8.4 PCI Status Register PCISTS is a 16-bit status register that reports the occurrence of error events on Device #0's PCI Interface. Bit 14 is Read/Write Clear. All other bits are Read Only. Since GMCH Device #0 does not physically reside on PCI_A many of the bit...
Page 54 - RID – Register Identification
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 54 D15343-003 4.8.5 RID – Register Identification This register contains the revision number of the GMCH Device #0. These bits are read only and writes to this register have no effect. 4.8.6 SUBC – Sub Class Code Register This register contains the...
Page 55 - BCC – Base Class Code Register; This value is used to identify the vendor of the subsystem.
Register Description D15343-003 55 4.8.7 BCC – Base Class Code Register This register contains the Base Class code of the GMCH Device #0. This code is 06h indicating a Bridge device. 4.8.8 HDR – Header Type Register This register identifies the header layout of the configuration space. No physical r...
Page 56 - SID – Subsystem Identification Register; This value is used to identify a particular subsystem.; CAPPTR – Capabilities Pointer Register
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 56 D15343-003 4.8.10 SID – Subsystem Identification Register This value is used to identify a particular subsystem. 4.8.11 CAPPTR – Capabilities Pointer Register The CAPPTR provides the offset that is the pointer to the location of the first device...
Page 61 - Attribute Bit Assignment
Register Description D15343-003 61 4.8.17 PAM(6:0) – Programmable Attribute Map Register (Device #0) The GMCH allows programmable DDR SDRAM attributes on 13 Legacy system memory segments of various sizes in the 640 kB -1 MB address range. Seven Programmable Attribute Map (PAM) registers are used to ...
Page 62 - PAM Registers
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 62 D15343-003 As an example, consider a BIOS that is implemented on the Expansion bus. During the initialization process, the BIOS can be shadowed in main system memory to increase the system performance. When BIOS is shadowed in main system memory...
Page 63 - PAM Registers and Associated System Memory Segments; Routing of accesses
Register Description D15343-003 63 Table 21. PAM Registers and Associated System Memory Segments For details on overall system address mapping scheme see the Address Decoding section of this document. DOS Application Area (00000h-9FFFh) The DOS area is 640 kB in size and it is further divided into t...
Page 65 - ESMRAMC – Extended System Management RAM Control (Device #0)
Register Description D15343-003 65 4.8.19 ESMRAMC – Extended System Management RAM Control (Device #0) The Extended SMRAM register controls the configuration of Extended SMRAM Space. The Extended SMRAM (E_SMRAM) Memory provides a Write-Back cacheable SMRAM Memory Space that is above 1 MB. Address Of...
Page 67 - #0 via the PCI Command register
Register Description D15343-003 67 4.8.21 ERRCMD – Error Command Register (Device #0) This register enables various errors to generate a SERR Hub Interface Special cycle. Since the GMCH does not have a SERR# signal, SERR messages are passed from the GMCH to the ICH4-M over Hub interface. The actual ...
Page 70 - SHIC – Secondary Host Interface Control Register (Device #0)
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 70 D15343-003 4.8.24 SHIC – Secondary Host Interface Control Register (Device #0) Address Offset:Default Value:Access:Size: 74-77h00006010hRead Only, Read/Write32 bits Bit Descriptions 31 Reserved 30 BREQ0# Control of FSB Address and Control bus po...
Page 75 - PCISTS – PCI Status Register
Register Description D15343-003 75 4.9.4 PCISTS – PCI Status Register PCISTS is a 16-bit status register that reports the occurrence of error events on Device #0's PCI Interface. Bit 14 is Read/Write Clear. All other bits are Read Only. Since GMCH Device #0 does not physically reside on PCI_A, many ...
Page 76 - RID – Revision Identification Register
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 76 D15343-003 4.9.5 RID – Revision Identification Register This register contains the revision number of the Intel ® 82854 GMCH Device #0. These bits are Read Only and Writes to this register have no effect. 4.9.6 RID – Revision Identification Regi...
Page 77 - HDR – Header Type Register
Register Description D15343-003 77 4.9.8 HDR – Header Type Register This register identifies the header layout of the configuration space. No physical register exists at this location. 4.9.9 SVID – Subsystem Vendor Identification Register This value is used to identify the vendor of the subsystem. 4...
Page 78 - 4h to 4Fh is reserved.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 78 D15343-003 4.9.11 CAPPTR – Capabilities Pointer Register The CAPPTR provides the offset that is the pointer to the location of the first device capability in the capability list. 4.9.12 DRB – DRAM Row (0:3) Boundary Register (Device #0) The DDR ...
Page 79 - Row Attribute Register; defines the page sizes to be used when accessing; DRA; registers describes the page size
Register Description D15343-003 79 4.9.13 DRA – DRAM Row Attribute Register (Device #0) The DDR SDRAM Row Attribute Register defines the page sizes to be used when accessing different pairs of Rows. Each Nibble of information in the DRA registers describes the page size of a pair of Rows: Row 0, 1: ...
Page 93 - DID – Device Identification Register
Register Description D15343-003 93 4.10.2 DID – Device Identification Register This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI device. Writes to this register have no effect. Address Offset:Default Value:Access:Size: 02-03h358ChRead Only16 bits Bit D...
Page 94 - Since the Intel
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 94 D15343-003 4.10.3 PCICMD – PCI Command Register Since the Intel ® 82854 GMCH Device #0 does not physically reside on PCI_A many of the bits are not implemented. Address Offset:Default Value:Access:Size: 04-05h0006hRead Only, Read/Write16 bits Bi...
Page 97 - ID – Subsystem Identification Register
Register Description D15343-003 97 4.10.8 HDR – Header Type Register This register identifies the header layout of the configuration space. No physical register exists at this location. 4.10.9 SVID – Subsystem Vendor Identification Register This value is used to identify the vendor of the subsystem....
Page 100 - “Nomenclature for Access Attributes” on page 42
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 100 D15343-003 4.11 Intel ® 82854 GMCH Integrated Graphics Device Registers (Device #2, Function #0) This section contains the PCI configuration registers listed in order of ascending offset address. Device #2 incorporates Function #0. See “Nomencl...
Page 111 - System Memory Address Ranges; Figure 5; Simplified View of System Address Map
Intel ® 82854 GMCH System Address Map D15343-003 111 5.0 Intel ® 82854 GMCH System Address Map A system based on the GMCH supports 4 GB of addressable system memory space and 64 kB+3B of addressable I/O space. The I/O and system memory spaces are divided by system configuration software into regions...
Page 112 - DOS Compatibility Area; 60 kB - 1 MB system BIOS area; Detailed View of System Address Map
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 112 D15343-003 5.2 DOS Compatibility Area This compatibility region is divided into the following address regions: • 0 - 640 kB DOS Area • 640 - 768 kB Video Buffer Area • 768 - 896 kB in 16-kB sections (total of eight sections) - expansion area • ...
Page 113 - System Memory Segments and Their Attributes; Legacy VGA ranges is accessible when the Intel
Intel ® 82854 GMCH System Address Map D15343-003 113 Table 26. System Memory Segments and Their Attributes DOS Area (000000h-09FFFFh) The DOS area is 640 kB in size and is always mapped to the main system memory controlled by the GMCH. Legacy VGA Ranges (0A0000h-0BFFFFh) Legacy VGA ranges is accessi...
Page 114 - Extended System Memory Area; Main system memory from 1 MB to the top of system memory.
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 114 D15343-003 Monochrome Display Adapter (MDA) Range (0B0000h - 0B7FFFh) Monochrome Display Adapter ranges is accessible when the Intel® 854 Chipset is strapped into Native Graphics mode. Legacy support requires the ability to have a second graphi...
Page 115 - Pre-allocated System Memory
Intel ® 82854 GMCH System Address Map D15343-003 115 5.4 Main System Memory Address Range (0010_0000h to Top of Main Memory) The address range from 1 MB to the top of main system memory is mapped to main DDR SDRAM address range controlled by the GMCH. The GMCH will forward all accesses to addresses ...
Page 116 - Extended SMRAM Address Range (HSEG and TSEG)
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 116 D15343-003 5.4.2.1 Extended SMRAM Address Range (HSEG and TSEG) The HSEG and TSEG SMM transaction address spaces reside in this extended system memory area. 5.4.2.2 HSEG SMM mode CPU accesses to enabled HSEG are remapped to 000A0000h-000BFFFFh....
Page 117 - PCI Memory Address Range (Top of Main System Memory to 4 GB)
Intel ® 82854 GMCH System Address Map D15343-003 117 5.4.2.5 PCI Memory Address Range (Top of Main System Memory to 4 GB) The address range from the top of main DDR SDRAM to 4-GB (top of physical system memory space supported by the GMCH) is normally mapped via the Hub interface to PCI. As an intern...
Page 118 - System Management Mode (SMM) Memory Range; SMM Space Restrictions
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 118 D15343-003 5.4.3 System Management Mode (SMM) Memory Range The GMCH supports the use of main system memory as System Management RAM (SMM RAM) enabling the use of System Management mode. The GMCH supports three SMM options: Compatible SMRAM (C_S...
Page 119 - SMM Space Transaction Handling; System Memory Shadowing
Intel ® 82854 GMCH System Address Map D15343-003 119 Table 28. SMM Space Transaction Handling 5.4.4 System Memory Shadowing Any block of system memory that can be designated as Read-Only or Write-Only can be "shadowed" into GMCH DDR SDRAM. Typically this is done to allow ROM code to execute ...
Page 120 - PCI I/O Address Mapping; The PCICMD1 register can disable the routing of I/O cycles to PCI.; GMCH Decode Rules and Cross-Bridge Address Mapping
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 120 D15343-003 5.4.5.1 PCI I/O Address Mapping The GMCH can be programmed to direct non-memory (I/O) accesses to the PCI bus interface when CPU initiated I/O cycle addresses are within the I/O address range. This range is controlled via the I/O Bas...
Page 121 - Hub Interface Decode Rules; Memory writes to VGA range (Native Graphics Mode only); Hub Interface Accesses to GMCH that Cross Device Boundaries
Intel ® 82854 GMCH System Address Map D15343-003 121 5.4.7 Hub Interface Decode Rules The GMCH accepts accesses from Hub interface to the following address ranges: • All Memory Read and Write accesses to Main DDR SDRAM including PAM region (except SMM space) • Memory writes to VGA range (Native Grap...
Page 122 - Interface Decode Rules
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 122 D15343-003 5.4.7.2 Interface Decode Rules Cycles Initiated Using PCI Protocol The GMCH does not support any PCI access targeting Hub interface. The GMCH will claim PCI initiated memory read and write transactions decoded to the main DDR SDRAM r...
Page 123 - Functional Description; Host Interface Overview; Relation of DBI Bits to Data Bits; System Bus Interrupt Delivery
Functional Description D15343-003 123 6.0 Functional Description 6.1 Host Interface Overview The GMCH front side bus uses source synchronous transfer for the address and data signals. The address signals are double pumped and two addresses can be generated every bus clock. At100-MHz bus frequency, t...
Page 124 - Upstream Interrupt Messages; System Memory Interface; DDR SDRAM Interface Overview; Configuration Mechanism for DDR DIMMs
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 124 D15343-003 MSI is dependent on the address of the interrupt Memory Write. The GMCH forwards inbound Hub interface memory writes to address 0FEEx_xxxxh, to the system bus as Interrupt Message transactions. 6.2.2 Upstream Interrupt Messages The G...
Page 125 - System Memory Register Programming; lists; Data Bytes on DDR DIMM Used for Programming DRAM Registers; provide enough data for programming the GMCH DDR SDRAM registers.; DDR SDRAM Performance Description
Functional Description D15343-003 125 series of I/O cycles to the south bridge. The BIOS needs to determine the size and type of system memory used for each of the rows of system memory in order to properly configure the GMCH system memory interface. For SMBus Configuration and Access of the Serial ...
Page 126 - Integrated Graphics Overview; The Intel; D/2D Instruction Processing; DVOB
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 126 D15343-003 6.4 Integrated Graphics Overview The Intel ® 82854 GMCH provides a highly integrated graphics accelerator and PCI set while allowing a flexible Integrated System Graphics solution. High bandwidth access to data is provided through th...
Page 127 - D Engine; Setup Engine
Functional Description D15343-003 127 6.4.2 3D Engine The 3D engine of the GMCH has been designed with a deeply pipelined architecture, where performance is maximized by allowing each stage of the pipeline to simultaneously operate on different primitives or portions of the same primitive. The GMCH ...
Page 128 - Backface Culling
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 128 D15343-003 The scissor rectangle accelerates the clipping process by allowing the driver to clip to a bigger region than the hardware renders to. The scissor rectangle is pixel accurate, and independent of line and point width. The GMCH support...
Page 129 - Texture Chromakey; The GMCH supports seven types of texture filtering:
Functional Description D15343-003 129 6.4.2.10 Texture Chromakey Chromakey is a method for removing a specific color or range of colors from a texture map before it is applied to an object. For nearest texture filter modes, removing a color simply makes those portions of the object transparent (the ...
Page 130 - Multiple Texture Composition; Raster Engine
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 130 D15343-003 Maps. Trilinear MIP Mapping is used minimize the visibility of LOD transitions across the polygon. • Anisotropic MIP Nearest (Anisotropic filtering): This filter can be used when textured object pixels map back to significantly non-s...
Page 131 - Texture Map Blending
Functional Description D15343-003 131 6.4.3.1 Texture Map Blending Multiple textures can be blended together in an iterative process and applied to a primitive. The GMCH allows up to four distinct or shared texture coordinates and texture maps to be specified onto the same polygon. Also, the GMCH su...
Page 132 - Alpha Blending
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 132 D15343-003 The GMCH supports both types of fog operations, vertex and per pixel. If fog is disabled, the incoming color intensities are passed unchanged to the destination blend unit. If fog is enabled, the incoming pixel color is blended with ...
Page 133 - Stencil Buffer; D Engine; 56-Bit Pattern Fill and BLT Engine; Move rectangular blocks of data between system memory locations
Functional Description D15343-003 133 reasonably accurate depth buffering within inches of the eye point. The selection of depth buffer size is relatively independent of the color buffer. A 16-bit Z/W or 24-bit Z/W buffer can be selected with a 16-bit color buffer. Z buffer is not supported in 8-bit...
Page 134 - Alpha Stretch BLT; Planes and Engines; Dual Display Usage Model (Native Graphic Mode only)
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 134 D15343-003 Data is horizontally and vertically aligned at the destination. If the destination for the BLT overlaps with the source system memory location, the GMCH can specify which area in system memory to begin the BLT transfer. Hardware is i...
Page 135 - Cursor Color Formats; Overlay Plane; Gamma Correction
Functional Description D15343-003 135 6.4.6.1 Cursor Color Formats Color data can be in an indexed format or a true color format. Indexed data uses the entries in the four-entry cursor palette to convert the two-bit index to a true color format before being passed to the blenders. The index can opti...
Page 136 - Color Control
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 136 D15343-003 6.4.7.5 Color Control Color control provides a method of changing the color characteristics of the pixel data. It is applied to the data while in YUV format and uses input parameters such as brightness, saturation, hue (tint) and con...
Page 137 - Video Functionality; MPEG-4: Only supports some features in the simple profile; Hardware Motion Compensation
Functional Description D15343-003 137 6.4.8 Video Functionality The GMCH supports MPEG-2 decoding hardware, sub-picture support and DTV. 6.4.8.1 MPEG-2 Decoding The GMCH MPEG2 Decoding supports Hardware Motion Compensation (HWMC). The GMCH can accelerate video decoding for the following video coding...
Page 138 - Internal Graphic Display Interface; Pipe A Timing Generator Unit
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 138 D15343-003 6.5 Internal Graphic Display Interface The GMCH has three dedicated display ports: an Analog CRT port and two Digital display ports, DVOB and DVOC. When the GMCH is strapped to operate in Native Graphic Mode, the DVOB and DVOC can su...
Page 139 - ARIB Support; H, V timing signals for active and blank timing; Figure 9; ARIB TR-B15 Plane Resolutions
Functional Description D15343-003 139 6.5.1.1 ARIB Support Please refer to the ARIB TR-B15 Operational Guidelines for Digital Satellite Broadcasting (detailed Implementation guideline for receiver) for an exhaustive coverage of this topic ( http://www.arib.or.jp/english/html/overview/ov/tr_b15.html ...
Page 140 - HSYNC/VSYNC Field Timing
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 140 D15343-003 6.5.1.3 HSYNC/VSYNC Field Timing The interlace timing is provided on the timing generator associated with Display Pipe A. When data is being driven out of the device, HSYNC and VSYNC accompanies or frames the data. Interlace timing r...
Page 141 - Blend Function; Interlace support for Plane A graphics; In the Intel
Functional Description D15343-003 141 Following conditions should be met for the sync (HSYNC, VSYNC) and blank (HBLANK, VBLANK) signals: • Start of H(V)SYNC can not coincide with start of H(V)BLANK • H(V)SYNC should always start after H(V)BLANK starts. In interlaced mode, the Vertical Total (VTOTAL_...
Page 143 - Interlace support for Video Overlay Window; DVO Control Data Bits; The Display Pipe A timing registers:
Functional Description D15343-003 143 6.5.4 Interlace support for Video Overlay Window In interlace mode, support for Field1 and Field2 timing generation is supported by the Video Overlay. The Video Overlay makes use of the DPODPfieldID signal generated by the Pipe A timing generator to synchronize ...
Page 144 - Timing Register Switching
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 144 D15343-003 Figure 11 shows how the timing registers switch while the buffer 0 and buffer 1 are scanned out. As shown in the above figure, buffer switching in Multi-display mode occurs on VBLANK. Once VBLANK is detected, horizontal and vertical ...
Page 145 - Analog Display Port Characteristics; Integrated RAMDAC
Functional Description D15343-003 145 6.5.5 Analog Display Port Characteristics The Analog display port provides an RGB signal output along with an HSYNC and VSYNC signal. There is an associated DDC signal pair that is implemented using GPIO pins dedicated to the analog port. The intended target dev...
Page 147 - Power and Thermal Management
Power and Thermal Management D15343-003 147 7.0 Power and Thermal Management The Intel ® 82854 GMCH is intended to be compliant with the following specifications and technologies: • APM Rev 1.2 • PCI Power Management Rev 1.0 • PC'99, Rev 1.0, PC'99A, and PC'01, Rev 1.0 • ACPI 1.0b and 2.0 support • ...
Page 148 - General Description of Supported CPU States
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 148 D15343-003 7.1 General Description of Supported CPU States C0 (Full On) : This is the only state that runs software. All clocks are running, STPCLK is deasserted, and the processor core is active. The processor can service snoops and maintain c...
Page 149 - Internal Thermal Sensor; This section describes the new on-die Thermal sensor capability.; The Thermal sensor functions are provided below:; Catastrophic Trip Point; : This trip point is nominally 14oC below the Catastrophic trip; Hysteresis Operation
Power and Thermal Management D15343-003 149 7.3 Internal Thermal Sensor This section describes the new on-die Thermal sensor capability. 7.3.1 Overview The Thermal sensor functions are provided below: Catastrophic Trip Point : This trip point is programmed through the BIOS during initialization. Thi...
Page 150 - External Thermal Sensor Input; Intel® 854 Chipset Platform Design Guide For Use with; Usage; External sensor(s) used for dynamic temperature feedback control:
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 150 D15343-003 7.4 External Thermal Sensor Input An External Thermal sensor with a serial interface may be placed next to DDR SDRAM DIMM (or any other appropriate platform location), or a remote Thermal Diode may be placed next to the DDR DIMM (or ...
Page 151 - Strapping Configuration; Strapping Signals and Configuration
Intel ® 82854 GMCH Strap Pins D15343-003 151 8.0 Intel ® 82854 GMCH Strap Pins 8.1 Strapping Configuration Table 33. Strapping Signals and Configuration Note: All strap signals are sampled with respect to the leading edge of the Intel ® 82854 GMCH PWROK In signal. Pin Name Strap Description Configur...
Page 153 - Ballout and Package Information
Ballout and Package Information D15343-003 153 9.0 Ballout and Package Information Figure 12. Intel ® 82854 GMCH Ballout Diagram (Top View) 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AJ NC NC VSS VSS VCCSM SMVREF _0 VSS SMVSW I NGL VCCSM VSS SMVSW I NGH VSS VCCSM V...
Page 154 - VCC/VSS Voltage Groups; Voltage Levels and Ball Out for Voltage Groups
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 154 D15343-003 9.1 VCC/VSS Voltage Groups Table 35. Voltage Levels and Ball Out for Voltage Groups Name Voltage Level Ball out VCC 1.5 H14,J15,N14,N16,P13,P15,P17,R14,R16,T13,T15, T17,U14,U16,W21,AA15,AA17,AA19 VCCADAC 1.5 A9,B9 VCCDVO 1.5 E1,E4,E6...
Page 155 - Ballout Table
Ballout and Package Information D15343-003 155 Table 36. Ballout Table Row Column Signal Name Row Column Signal Name Row Column Signal Name E 5 ADDID[0] AA 22 DPWR# G 3 DVOCD[11] F 5 ADDID[1] N 24 DRDY# K 3 DVOCD[2] E 3 ADDID[2] B 7 DREFCLK K 2 DVOCD[3] E 2 ADDID[3] B 17 RSVD J 6 DVOCD[4] G 5 ADDID[...
Page 164 - Package Mechanical Information; through
Intel ® 82854 Graphics Memory Controller Hub (GMCH) 164 D15343-003 9.2 Package Mechanical Information Figure 13 through Figure 15 provide detail on the package information and dimensions of the Intel ® 82854 GMCH. The Intel ® 82854 GMCH comes in a Micro-FCBGA package, which is similar to the mobile ...
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