Intel D15343-003 - Manual

Intel D15343-003

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Table of Contents:

  • Page 3 – Contents; Intel
  • Page 7 – Figures; Tables
  • Page 9 – Revision History
  • Page 11 – Introduction; Overview; Figure 1; Processor/Host Bus Support
  • Page 12 – System Interrupts
  • Page 13 – Display
  • Page 15 – Hub Interface to ICH4-M
  • Page 16 – Package; Intel® 854 Chipset system block diagram (Native Graphic mode)
  • Page 17 – Terminology; Terms and Descriptions
  • Page 19 – Reference Documents
  • Page 21 – System Architecture
  • Page 22 – Processor Host Interface; DDR SDRAM Memory Capacity
  • Page 23 – Graphics Features; GMCH Analog Display Port; Figure 8
  • Page 24 – Hub Interface
  • Page 25 – GMCH Clocking; The GMCH has the following clock input/output pins:
  • Page 27 – Signal Description; This section describes the Intel
  • Page 28 – Host Interface Signals; Host Interface Signal Descriptions
  • Page 31 – DDR SDRAM Interface; DDR SDRAM Interface Descriptions
  • Page 32 – Hub Interface Signals
  • Page 33 – Clocks; Clock Signals
  • Page 35 – Internal Graphics Display Signals; Digital Video Output B (DVOB) Port Signal Descriptions
  • Page 36 – Digital Video Output C (DVOC) Port Signal Descriptions
  • Page 37 – DVOB and DVOC Port Common Signal Descriptions; Analog CRT Display; Analog CRT Display Signal Descriptions
  • Page 38 – General Purpose Input/Output Signals; GPIO Signal Descriptions
  • Page 39 – Voltage References, PLL Power
  • Page 41 – Register Description; Function #1: DDR SDRAM Interface Registers; Device Number Assignment
  • Page 42 – provides the nomenclature for the access attributes.; Nomenclature for Access Attributes
  • Page 43 – Standard PCI Bus Configuration Mechanism; PCI Bus #0 Configuration Mechanism
  • Page 44 – Primary PCI and Downstream Configuration Mechanism; Register Definitions; I/O Mapped into the CPU I/O Space, which control access to PCI; Internal Configuration registers:; residing within the GMCH, they are partitioned into two; Internal Memory Mapped Configuration registers:; reside in the GMCH Device #2 that controls the Integrated Graphics; Reserved Bits
  • Page 45 – CONFIG_ADDRESS – Configuration Address Register; Configuration Address Register; Reserved
  • Page 47 – CONFIG_DATA – Configuration Data Register; Configuration Data Register; Configuration Data Window
  • Page 48 – VGA I/O Mapped Registers; lists direct CPU Access registers and; VGA I/O Mapped Register List
  • Page 51 – VID – Vendor Identification Register
  • Page 52 – PCICMD – PCI Command Register
  • Page 53 – PCI Status Register
  • Page 54 – RID – Register Identification
  • Page 55 – BCC – Base Class Code Register; This value is used to identify the vendor of the subsystem.
  • Page 56 – SID – Subsystem Identification Register; This value is used to identify a particular subsystem.; CAPPTR – Capabilities Pointer Register
  • Page 61 – Attribute Bit Assignment
  • Page 62 – PAM Registers
  • Page 63 – PAM Registers and Associated System Memory Segments; Routing of accesses
  • Page 65 – ESMRAMC – Extended System Management RAM Control (Device #0)
  • Page 67 – #0 via the PCI Command register
  • Page 70 – SHIC – Secondary Host Interface Control Register (Device #0)
  • Page 75 – PCISTS – PCI Status Register
  • Page 76 – RID – Revision Identification Register
  • Page 77 – HDR – Header Type Register
  • Page 78 – 4h to 4Fh is reserved.
  • Page 79 – Row Attribute Register; defines the page sizes to be used when accessing; DRA; registers describes the page size
  • Page 93 – DID – Device Identification Register
  • Page 94 – Since the Intel
  • Page 97 – ID – Subsystem Identification Register
  • Page 100 – “Nomenclature for Access Attributes” on page 42
  • Page 111 – System Memory Address Ranges; Figure 5; Simplified View of System Address Map
  • Page 112 – DOS Compatibility Area; 60 kB - 1 MB system BIOS area; Detailed View of System Address Map
  • Page 113 – System Memory Segments and Their Attributes; Legacy VGA ranges is accessible when the Intel
  • Page 114 – Extended System Memory Area; Main system memory from 1 MB to the top of system memory.
  • Page 115 – Pre-allocated System Memory
  • Page 116 – Extended SMRAM Address Range (HSEG and TSEG)
  • Page 117 – PCI Memory Address Range (Top of Main System Memory to 4 GB)
  • Page 118 – System Management Mode (SMM) Memory Range; SMM Space Restrictions
  • Page 119 – SMM Space Transaction Handling; System Memory Shadowing
  • Page 120 – PCI I/O Address Mapping; The PCICMD1 register can disable the routing of I/O cycles to PCI.; GMCH Decode Rules and Cross-Bridge Address Mapping
  • Page 121 – Hub Interface Decode Rules; Memory writes to VGA range (Native Graphics Mode only); Hub Interface Accesses to GMCH that Cross Device Boundaries
  • Page 122 – Interface Decode Rules
  • Page 123 – Functional Description; Host Interface Overview; Relation of DBI Bits to Data Bits; System Bus Interrupt Delivery
  • Page 124 – Upstream Interrupt Messages; System Memory Interface; DDR SDRAM Interface Overview; Configuration Mechanism for DDR DIMMs
  • Page 125 – System Memory Register Programming; lists; Data Bytes on DDR DIMM Used for Programming DRAM Registers; provide enough data for programming the GMCH DDR SDRAM registers.; DDR SDRAM Performance Description
  • Page 126 – Integrated Graphics Overview; The Intel; D/2D Instruction Processing; DVOB
  • Page 127 – D Engine; Setup Engine
  • Page 128 – Backface Culling
  • Page 129 – Texture Chromakey; The GMCH supports seven types of texture filtering:
  • Page 130 – Multiple Texture Composition; Raster Engine
  • Page 131 – Texture Map Blending
  • Page 132 – Alpha Blending
  • Page 133 – Stencil Buffer; D Engine; 56-Bit Pattern Fill and BLT Engine; Move rectangular blocks of data between system memory locations
  • Page 134 – Alpha Stretch BLT; Planes and Engines; Dual Display Usage Model (Native Graphic Mode only)
  • Page 135 – Cursor Color Formats; Overlay Plane; Gamma Correction
  • Page 136 – Color Control
  • Page 137 – Video Functionality; MPEG-4: Only supports some features in the simple profile; Hardware Motion Compensation
  • Page 138 – Internal Graphic Display Interface; Pipe A Timing Generator Unit
  • Page 139 – ARIB Support; H, V timing signals for active and blank timing; Figure 9; ARIB TR-B15 Plane Resolutions
  • Page 140 – HSYNC/VSYNC Field Timing
  • Page 141 – Blend Function; Interlace support for Plane A graphics; In the Intel
  • Page 143 – Interlace support for Video Overlay Window; DVO Control Data Bits; The Display Pipe A timing registers:
  • Page 144 – Timing Register Switching
  • Page 145 – Analog Display Port Characteristics; Integrated RAMDAC
  • Page 147 – Power and Thermal Management
  • Page 148 – General Description of Supported CPU States
  • Page 149 – Internal Thermal Sensor; This section describes the new on-die Thermal sensor capability.; The Thermal sensor functions are provided below:; Catastrophic Trip Point; : This trip point is nominally 14oC below the Catastrophic trip; Hysteresis Operation
  • Page 150 – External Thermal Sensor Input; Intel® 854 Chipset Platform Design Guide For Use with; Usage; External sensor(s) used for dynamic temperature feedback control:
  • Page 151 – Strapping Configuration; Strapping Signals and Configuration
  • Page 153 – Ballout and Package Information
  • Page 154 – VCC/VSS Voltage Groups; Voltage Levels and Ball Out for Voltage Groups
  • Page 155 – Ballout Table
  • Page 164 – Package Mechanical Information; through
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Intel

®

82854 Graphics Memory

Controller Hub (GMCH)

Datasheet

Revision 2.0

June 2005

Order Number:

D15343-003

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Summary

Page 3 - Contents; Intel

D15343-003 3 Contents Contents 1.0 Introduction .................................................................................................................................... 111.1 Overview ...........................................................................................................

Page 7 - Figures; Tables

D15343-003 7 Contents Figures 1 Intel® 854 Chipset system block diagram (Native Graphic mode) ............................................. 16 2 Configuration Address Register .................................................................................................. 45 3 Configuration Data R...

Page 9 - Revision History

D15343-003 9 Contents Revision History § § Date Revision Description March 2005 1.0 Initial release of this document. June 2005 2.0 Add support for Genuine Intel® Processor at 1.2 GHz and Genuine Intel® Processor at 1.5 GHz technology.

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