Page 3 - Contents
R Intel ® 82845 MCH for SDR Datasheet 3 Contents 1 Introduction ........................................................................................................................ 11 1.1 Terminology and Notations .....................................................................................
Page 7 - Figures
R Intel ® 82845 MCH for SDR Datasheet 7 Figures Figure 1. Intel ® MCH Simplified Block Diagram ................................................................. 20 Figure 2. PAM Register Attributes ..................................................................................... 60 Figure 3. Add...
Page 8 - Revision History
R 8 Intel ® 82845 MCH for SDR Datasheet Revision History Revision Number Description Date -001 Initial Release. September 2001 -002 • Changed the document name to add the term “for SDR”. • DWTC—DRAM Write Thermal Management Control Register was incorrectly placed in Device 0. It should be in Device ...
Page 9 - Note
R Intel ® 82845 MCH for SDR Datasheet 9 Intel ® 82845 MCH Features ! Intel ® Pentium ® 4 Processor (478 pin package) Support Enhanced Mode Scaleable Bus Protocol 2x Address, 4x Data System Bus interrupt delivery 400 MHz system bus System Bus Dynamic Bus Inversion (DBI) 32-bit system bus ...
Page 10 - System Block Diagram
R 10 Intel ® 82845 MCH for SDR Datasheet System Block Diagram In te l ® 8 2 8 0 1 B A I/O C o n tro lle r H u b (IC H 2 ) S y s te m M e m o ry s ys _ b lk P C I B u s In te l ® 8 2 8 4 5 M e m o ry C o n tro lle r H u b (M C H ) 4 x A G P G ra p h ic s C o n tro ll e r H u bIn te rfa c e 4 U S B P ...
Page 11 - Introduction; Terminology and Notations; Table 1. General Terminology
Introduction R Intel ® 82845 MCH for SDR Datasheet 11 1 Introduction The Intel ® 82845 Memory Controller Hub (MCH) is designed for use with the Intel ® Pentium ® 4 processor in the 478-pin package. The Intel ® 845 chipset contains two main components: the 82845 Memory Controller Hub (MCH) for the ho...
Page 12 - Table 2. Data Type Notation
Introduction R 12 Intel ® 82845 MCH for SDR Datasheet Term Description GART Graphics Aperture Re-map Table. This table contains the page re-map information used during AGP aperture address translations. GTLB Graphics Translation Look-aside Buffer. A cache used to store frequently used GART entries. ...
Page 13 - Documents
Introduction R Intel ® 82845 MCH for SDR Datasheet 13 1.2 Reference Documents Document Document Number / Location Intel ® Pentium 4 Processor in a 478 Pin Package and Intel ® 845 Chipset Platform for SDR Design Guide 298354 Intel ® 82801BA I/O Controller Hub (ICH2 ) and Intel ® 82801BAM I/O Controll...
Page 14 - 45 Chipset System Architecture
Introduction R 14 Intel ® 82845 MCH for SDR Datasheet 1.3 Intel ® 845 Chipset System Architecture The MCH provides the processor interface, system memory interface, AGP interface, and hub interface in an 845 chipset desktop platform. The processor interface supports the Pentium 4 processor subset of...
Page 15 - System Bus Interface; System Bus Error Checking
Introduction R Intel ® 82845 MCH for SDR Datasheet 15 1.4.1 System Bus Interface The MCH is optimized for the Pentium 4 processor. The primary enhancements over the Compatible Mode P6 bus protocol are: • Source synchronous double-pumped address • Source synchronous quad-pumped data • System bus inte...
Page 16 - System Memory Interface; Table 4. Memory Capacity; Interface; only
Introduction R 16 Intel ® 82845 MCH for SDR Datasheet 1.4.3 System Memory Interface The MCH directly supports one channel of PC133 SDRAM. The memory interface supports Single Data Rate (SDR) devices with densities of 64 Mb, 128 Mb, 256 Mb, and 512 Mb technology. The memory interface also supports va...
Page 17 - MCH Clock Ratio Table
Introduction R Intel ® 82845 MCH for SDR Datasheet 17 1.4.5 Hub Interface The 8-bit hub interface connects the MCH to the ICH2. All communication between the MCH and the ICH2 occurs over the hub interface. The hub interface runs at 66 MHz / 266 MB/s. In addition to the normal traffic types, the foll...
Page 18 - Interrupts
Introduction R 18 Intel ® 82845 MCH for SDR Datasheet 1.4.7 System Interrupts The MCH supports both Intel 8259 and Pentium 4 processor interrupt delivery mechanisms. The serial APIC interrupt mechanism is not supported. Intel 8259 support consists of flushing inbound hub interface write buffers when...
Page 19 - Signal; AGP
Signal Description R Intel ® 82845 MCH for SDR Datasheet 19 2 Signal Description This chapter provides a detailed description of the MCH signals. The signal descriptions are arranged in functional groups according to their associated interface (see Figure 1). The states of all of the signals during ...
Page 20 - MCH Simplified Block Diagram
Signal Description R 20 Intel ® 82845 MCH for SDR Datasheet Figure 1. Intel ® MCH Simplified Block Diagram b lo c k _ d ia _ 8 4 5 S C S [1 1 :0 ]# S M A [1 2 :0 ] S B S [1 :0 ] S R A S #S C A S # S W E # S D Q [6 3 :0 ] S C B [7 :0 ] S C K E [5 :0 ] R D C L K O R D C L K IN A G P In te rf a c e S B...
Page 21 - System Bus Signals
Signal Description R Intel ® 82845 MCH for SDR Datasheet 21 2.1 System Bus Signals Signal Name Type Description ADS# I/O AGTL+ Address Strobe: The system bus owner asserts ADS# to indicate the first of two cycles of a request phase. BNR# I/O AGTL+ Block Next Request: BNR# is used to block the curren...
Page 23 - SDR SDRAM Interface Signals
Signal Description R Intel ® 82845 MCH for SDR Datasheet 23 2.2 SDR SDRAM Interface Signals Signal Name Type Description SCS[11:0]# O CMOS Chip Select: These signals select the particular SDRAM components during the active state. Note: There are two SCS# signals per SDRAM row. These signals can be t...
Page 24 - AGP Interface Signals; AGP Addressing Signals
Signal Description R 24 Intel ® 82845 MCH for SDR Datasheet 2.4 AGP Interface Signals 2.4.1 AGP Addressing Signals Signal Name Type Description PIPE# I AGP Pipelined Read: This signal is asserted by the AGP master to indicate a full-width address is to be enqueued on by the target using the AD bus. ...
Page 25 - AGP Flow Control Signals
Signal Description R Intel ® 82845 MCH for SDR Datasheet 25 2.4.2 AGP Flow Control Signals Signal Name Type Description RBF# I AGP Read Buffer Full: RBF# indicates if the master is ready to accept previously requested low priority read data. When RBF# is asserted, the MCH is not allowed to initiate ...
Page 26 - AGP Strobes Signals; Signals
Signal Description R 26 Intel ® 82845 MCH for SDR Datasheet 2.4.4 AGP Strobes Signals Signal Name Type Description AD_STB0 I/O (s/t/s) AGP Address/Data Bus Strobe-0: This signal provides timing for 2x and 4x data on AD[15:0] and the C/BE[1:0]# signals. The agent that is providing the data drives thi...
Page 28 - Clocks, Reset, and Miscellaneous Signals
Signal Description R 28 Intel ® 82845 MCH for SDR Datasheet 2.5 Clocks, Reset, and Miscellaneous Signals Signal Name Type Description BCLK BCLK# I CMOS Differential Host Clock In: These pins receive a differential host clock from the external clock synthesizer. This clock is used by all of the MCH l...
Page 29 - Voltage Reference and Power Signals
Signal Description R Intel ® 82845 MCH for SDR Datasheet 29 2.6 Voltage Reference and Power Signals Signal Name Type Description HVREF Ref Host Reference Voltage: Reference voltage input for the data, address, and common clock signals of the host AGTL+ interface. SDREF Ref SDRAM Reference Voltage: R...
Page 30 - Reset States During Reset
Signal Description R 30 Intel ® 82845 MCH for SDR Datasheet 2.7 Reset States During Reset Z Ti-state ISO Isolate inputs in inactive state S Strap input sampled during assertion or on the de-asserting edge of RSTIN# H Driven high L Driven low D Strong drive (to normal value supplied by core logic if ...
Page 31 - Register; Terminology
Register Description R Intel ® 82845 MCH for SDR Datasheet 31 3 Register Description The MCH contains two sets of software accessible registers, accessed via the host processor I/O address space: • Control registers I/O mapped into the processor I/O space, which control access to PCI and AGP configu...
Page 32 - PCI Bus Configuration Space Access; Note that the primary PCI bus; MCH Internal Device Assignments
Register Description R 32 Intel ® 82845 MCH for SDR Datasheet Term Description Reserved Registers In addition to reserved bits within a register, the MCH contains address locations in the configuration space that are marked “Reserved”. When a “Reserved” register location is read, a random value is r...
Page 33 - Standard PCI Bus Configuration Mechanism; PCI Bus 0 Configuration Mechanism
Register Description R Intel ® 82845 MCH for SDR Datasheet 33 3.2.1 Standard PCI Bus Configuration Mechanism The PCI Bus defines a slot based "configuration space" that allows each device to contain up to 8 functions with each function containing up to 256 8-bit configuration registers. The ...
Page 34 - Primary PCI and Downstream Configuration Mechanism; I/O Mapped Registers; CONF_ADDR—Configuration Address Register
Register Description R 34 Intel ® 82845 MCH for SDR Datasheet Primary PCI and Downstream Configuration Mechanism If the Bus Number in the CONF_ADDR is non-zero, and is less than the value in the Host-AGP device’s Secondary Bus Number register, or greater than the value in the Host-AGP device’s Subor...
Page 36 - CONF_DATA—Configuration Data Register; Memory-Mapped Register Space; Table 7. Memory-mapped Register Address Map
Register Description R 36 Intel ® 82845 MCH for SDR Datasheet 3.3.2 CONF_DATA—Configuration Data Register I/O Address: 0CFCh Default Value: 00000000h Access: R/W Size: 32 bits CONF_DATA is a 32 bit read/write window into configuration space. The portion of configuration space that is referenced by C...
Page 37 - DRAMWIDTH—DRAM Width Register
Register Description R Intel ® 82845 MCH for SDR Datasheet 37 3.4.1 DRAMWIDTH—DRAM Width Register Address Offset: 2Ch Default Value: 00h Access: R/W Size: 8 bits This register determines the width of SDRAM devices populated in each row of memory. Bit Descriptions 7:6 Reserved. 5 Row 5 Width. Width o...
Page 39 - CKESTR—Strength Control Register (SCKE Signal Group)
Register Description R Intel ® 82845 MCH for SDR Datasheet 39 3.4.3 CKESTR—Strength Control Register (SCKE Signal Group) Memory Address Offset: 31h Default Value: 00h Access: R/W Size: 8 bits This register controls the drive strength of the I/O buffers for the CKE signal group. This group has two po...
Page 41 - CKSTR—Strength Control Register (Clock Signal Group)
Register Description R Intel ® 82845 MCH for SDR Datasheet 41 3.4.5 CKSTR—Strength Control Register (Clock Signal Group) Memory Address Offset: 33h Default Value: 00h Access: R/W Size: 8 bits This register controls the drive strength of the I/O buffers for the Clock (CK) signal group including both ...
Page 45 - VID—Vendor Identification Register (Device 0); DID—Device Identification Register (Device 0)
Register Description R Intel ® 82845 MCH for SDR Datasheet 45 3.5.1 VID—Vendor Identification Register (Device 0) Address Offset: 00–01h Default Value: 8086h Attribute: RO Size: 16 bits The VID Register contains the vendor identification number. This 16-bit register combined with the DID Register un...
Page 48 - RID—Revision Identification Register (Device 0)
Register Description R 48 Intel ® 82845 MCH for SDR Datasheet 3.5.5 RID—Revision Identification Register (Device 0) Address Offset: 08h Default Value: See table below Access: RO Size: 8 bits This register contains the revision number of the MCH Device 0. These bits are read only and writes to this r...
Page 49 - MLT—Master Latency Timer Register (Device 0)
Register Description R Intel ® 82845 MCH for SDR Datasheet 49 3.5.8 MLT—Master Latency Timer Register (Device 0) Address Offset: 0Dh Default Value: 00h Access: RO Size: 8 bits The hub interface does not comprehend the concept of Master Latency Timer. Therefore, this register is not implemented. Bit ...
Page 50 - APBASE—Aperture Base Configuration Register (Device 0)
Register Description R 50 Intel ® 82845 MCH for SDR Datasheet 3.5.10 APBASE—Aperture Base Configuration Register (Device 0) Offset: 10–13h Default: 0000_0008h Access: R/W , RO Size: 32 bits The APBASE is a standard PCI Base Address register that is used to set the base of the Graphics Aperture. The ...
Page 51 - SVID—Subsystem Vendor Identification (Device 0)
Register Description R Intel ® 82845 MCH for SDR Datasheet 51 3.5.11 SVID—Subsystem Vendor Identification (Device 0) Offset: 2C–2Dh Default: 0000h Access: R/W O Size: 16 bits This value is used to identify the vendor of the subsystem. Bit Description 15:0 Subsystem Vendor ID. (Default = 0000h). This...
Page 53 - DRA—DRAM Row Attribute Registers (Device 0)
Register Description R Intel ® 82845 MCH for SDR Datasheet 53 3.5.16 DRA—DRAM Row Attribute Registers (Device 0) Offset: 70–73h (DRA0–DRA3) Default: 00h Access: R/W Size: 8 bits The DRAM Row Attribute Register defines the page sizes to be used when accessing different pairs of rows. Each nibble of i...
Page 56 - DRC—DRAM Controller Mode Register (Device 0)
Register Description R 56 Intel ® 82845 MCH for SDR Datasheet 3.5.18 DRC—DRAM Controller Mode Register (Device 0) Offset: 7C–7Fh Default: 00000000h Access: R/W , RO Size: 32 bits Bit Description 31:30 Revision Number (REV)—R/W. Reflects the revision number of the format used for SDRAM register defin...
Page 58 - DERRSYN—DRAM Error Syndrome Register (Device 0); EAP—Error Address Pointer Register (Device 0)
Register Description R 58 Intel ® 82845 MCH for SDR Datasheet 3.5.19 DERRSYN—DRAM Error Syndrome Register (Device 0) Address Offset: 86h Default Value: 00h Access: RO Size: 8 bits This register is used to report the ECC syndromes for each quadword of a 32 byte-aligned data quantity read from the sys...
Page 60 - Figure 2. PAM Register Attributes
Register Description R 60 Intel ® 82845 MCH for SDR Datasheet At the time that a hub interface or AGP accesses to the PAM region may occur, the targeted PAM segment must be programmed to be both readable and writeable. As an example, consider BIOS that is implemented on the expansion bus. During the...
Page 61 - Table 9. PAM Register Attributes; Routing of
Register Description R Intel ® 82845 MCH for SDR Datasheet 61 Table 9. PAM Register Attributes PAM Reg Attribute Bits Memory Segment Comments Offset PAM0[3:0] Reserved 90h PAM0[7:4] R R WE RE 0F0000h–0FFFFFh BIOS Area 90h PAM1[3:0] R R WE RE 0C0000h–0C3FFFh ISA Add-on BIOS 91h PAM1[7:4] R R WE RE 0C...
Page 62 - Extended System BIOS Area (E0000h–EFFFFh); FDHC—Fixed DRAM Hole Control Register (Device 0)
Register Description R 62 Intel ® 82845 MCH for SDR Datasheet Extended System BIOS Area (E0000h–EFFFFh) This 64 KB area is divided into four 16 KB segments that can be assigned with different attributes via PAM control register as defined by the table above. System BIOS Area (F0000h–FFFFFh) This are...
Page 65 - ACAPID—AGP Capability Identifier Register (Device 0)
Register Description R Intel ® 82845 MCH for SDR Datasheet 65 3.5.25 ACAPID—AGP Capability Identifier Register (Device 0) Address Offset: A0–A3h Default Value: 0020_0002h Access: RO Size: 32 bits This register provides standard identifier for AGP capability. Bit Description 31:24 Reserved. 23:20 Maj...
Page 73 - TOM—Top of Low Memory Register (Device 0)
Register Description R Intel ® 82845 MCH for SDR Datasheet 73 3.5.33 TOM—Top of Low Memory Register (Device 0) Address Offset: C4–C5h Default Value: 0100h Access: R/W Size: 16 bits This register contains the maximum address below 4 GB that should be treated as a memory access. Note that this registe...
Page 74 - MCHCFG—MCH Configuration Register (Device 0)
Register Description R 74 Intel ® 82845 MCH for SDR Datasheet 3.5.34 MCHCFG—MCH Configuration Register (Device 0) Offset: C6–C7h Default: 0000h Access: R/W , RO Size: 16 bits Bit Description 15:12 Reserved. 11 System Memory Frequency Select. This bit must be programmed prior to memory initialization...
Page 76 - ERRCMD—Error Command Register (Device 0)
Register Description R 76 Intel ® 82845 MCH for SDR Datasheet Bit Description 0 Single-bit DRAM ECC Error Flag (DSERR). 0 = Software must write a 1 to clear this bit and unlock the error logging mechanism. 1 = A memory read data transfer had a single-bit correctable error and the corrected data was ...
Page 79 - SKPD—Scratchpad Data Register (Device 0)
Register Description R Intel ® 82845 MCH for SDR Datasheet 79 3.5.39 SKPD—Scratchpad Data Register (Device 0) Address Offset: DE–DFh Default Value: 0000h Access: R/W Size: 16 bits Bit Description 15:0 Scratchpad [15:0]. These bits are R/W storage bits that have no effect on the MCH functionality. 3....
Page 81 - VID1—Vendor Identification Register (Device 1); DID1—Device Identification Register (Device 1)
Register Description R Intel ® 82845 MCH for SDR Datasheet 81 Address Offset Symbol Name Default Access 58–5Fh DRTC DRAM Read Thermal Management Control 00000000h R/W/L 59–FFh — Reserved — — 3.6.1 VID1—Vendor Identification Register (Device 1) Address Offset: 00–01h Default Value: 8086h Attribute: R...
Page 84 - RID1—Revision Identification Register (Device 1); BCC1—Base Class Code Register (Device 1)
Register Description R 84 Intel ® 82845 MCH for SDR Datasheet 3.6.5 RID1—Revision Identification Register (Device 1) Address Offset: 08h Default Value: See RID1 table below Access: RO Size: 8 bits This register contains the revision number of the MCH device 1. These bits are read only and writes to ...
Page 85 - MLT1—Master Latency Timer Register (Device 1); PBUSN1—Primary Bus Number Register (Device 1)
Register Description R Intel ® 82845 MCH for SDR Datasheet 85 3.6.8 MLT1—Master Latency Timer Register (Device 1) Address Offset: 0Dh Default Value: 00h Access: R/W Size: 8 bits This functionality is not applicable. It is described here since these bits should be implemented as a read/write to preve...
Page 86 - SBUSN1—Secondary Bus Number Register (Device 1); SUBUSN1—Subordinate Bus Number Register (Device 1)
Register Description R 86 Intel ® 82845 MCH for SDR Datasheet 3.6.11 SBUSN1—Secondary Bus Number Register (Device 1) Offset: 19h Default: 00h Access: R/W Size: 8 bits This register identifies the bus number assigned to the second bus side of the “virtual” PCI-PCI bridge i.e. to AGP. This number is p...
Page 90 - MBASE1—Memory Base Address Register (Device 1); MLIMIT1—Memory Limit Address Register (Device 1)
Register Description R 90 Intel ® 82845 MCH for SDR Datasheet 3.6.17 MBASE1—Memory Base Address Register (Device 1) Address Offset: 20–21h Default Value: FFF0h Access: R/W Size: 16 bits This register controls the host to AGP non-prefetchable memory accesses routing based on the following formula: ME...
Page 93 - ERRCMD1—Error Command Register (Device 1)
Register Description R Intel ® 82845 MCH for SDR Datasheet 93 Bit Descriptions 0 Parity Error Response Enable (PER_EN)—R/W. Controls MCH’s response to data phase parity errors on AGP. 0 = Address and data parity errors on AGP are not reported via the MCH hub interface SERR# messaging mechanism. Othe...
Page 97 - System Address Map; Memory Address Ranges; Figure 3. Addressable Memory Space
System Address Map R Intel ® 82845 MCH for SDR Datasheet 97 4 System Address Map A system based on the 845 chipset supports 4 GB of addressable memory space and 64 KB+3 of addressable I/O space. The I/O and memory spaces are divided by system configuration software into regions. The memory ranges ar...
Page 98 - Figure 4. DOS Compatible Area Address Map
System Address Map R 98 Intel ® 82845 MCH for SDR Datasheet Figure 4. DOS Compatible Area Address Map M o n o c h r o m e D is p la y A d a p te r S p a c e U p p e r , L o w e r , E x p a n s io n C a rd B IO S a n d B u ffe r A re a 1 M B s y s _ a d d r_ m a p _ 2 6 4 0 K B 7 0 4 K B 7 3 6 K B 7 ...
Page 99 - VGA and MDA Memory Space
System Address Map R Intel ® 82845 MCH for SDR Datasheet 99 4.1.1 VGA and MDA Memory Space Video cards use these legacy address ranges to map a frame buffer or a character-based video buffer. The address ranges in this memory space are: • VGAA 0_000A_0000 to 0_000A_FFFF • MDA 0_000B_0000 to 0_000B_7...
Page 100 - PAM Memory Spaces; ISA expansion region; ISA Hole Memory Space
System Address Map R 100 Intel ® 82845 MCH for SDR Datasheet 4.1.2 PAM Memory Spaces The address ranges in this memory space are: • PAMC0 0_000C_0000 to 0_000C_3FFF • PAMC4 0_000C_4000 to 0_000C_7FFF • PAMC8 0_000C_8000 to _000C_BFFF • PAMCC 0_000C_C000 to 0_000C_FFFF • PAMD0 0_000D_0000 to 0_000D_3...
Page 101 - TSEG SMM Memory Space
System Address Map R Intel ® 82845 MCH for SDR Datasheet 101 4.1.4 TSEG SMM Memory Space The TSEG SMM space (TOM – TSEG to TOM) allows system management software to partition a region of system memory just below the top of low memory (TOM) that is accessible only by system management software. This ...
Page 102 - AGP Memory and Prefetchable Memory; Hub Interface Subtractive Decode; AGP Memory Address Ranges
System Address Map R 102 Intel ® 82845 MCH for SDR Datasheet 4.1.8 AGP Aperture Space (Device 0 BAR) Processors and AGP devices communicate through a special buffer called the “graphics aperture” (APBASE to APBASE + APSIZE). This aperture acts as a window into main system memory and is defined by th...
Page 103 - AGP DRAM Graphics Aperture; System Management Mode (SMM) Memory Range
System Address Map R Intel ® 82845 MCH for SDR Datasheet 103 4.2.1 AGP DRAM Graphics Aperture Memory-mapped, graphics data structures can reside in a Graphics Aperture to system memory. This aperture is an address range defined by the APBASE and APSIZE registers of the MCH device 0. The APBASE regis...
Page 104 - SMM Space Definition; Table 11. SMM Space Address Ranges; SMM Space Restrictions
System Address Map R 104 Intel ® 82845 MCH for SDR Datasheet 4.3.1 SMM Space Definition Its addressed SMM space and its DRAM SMM space define SMM space. The addressed SMM space is defined as the range of bus addresses used by the processor to access SMM space. System memory SMM space is defined as t...
Page 105 - MCH Decode Rules and Cross-Bridge; Hub Interface Decode Rules
System Address Map R Intel ® 82845 MCH for SDR Datasheet 105 4.4 I/O Address Space The MCH does not support the existence of any other I/O devices beside itself on the system bus. The MCH generates either hub interface or AGP bus cycles for all processor I/O accesses. The MCH contains two internal r...
Page 106 - AGP Interface Decode Rules; Cycles Initiated Using AGP FRAME# Protocol
System Address Map R 106 Intel ® 82845 MCH for SDR Datasheet 4.5.2 AGP Interface Decode Rules Cycles Initiated Using AGP FRAME# Protocol The MCH does not support any AGP FRAME# access targeting the hub interface. The MCH claims AGP-initiated memory read and write transactions decoded to the system m...
Page 107 - Functional; Bus; Dynamic Bus Inversion
Functional Description R Intel ® 82845 MCH for SDR Datasheet 107 5 Functional Description This chapter describes the system bus that connects the MCH to the processor, the system memory interface, the AGP interface, the MCH power and thermal management, the MCH clocking, and the MCH system reset and...
Page 108 - System Bus Interrupt Delivery
Functional Description R 108 Intel ® 82845 MCH for SDR Datasheet 5.1.2 System Bus Interrupt Delivery The Pentium 4 processor supports the system bus interrupt delivery; the APIC serial bus interrupt delivery mechanism is not supported. Interrupt-related messages are encoded on the system bus as “Int...
Page 109 - Single Data Rate (SDR) SDRAM Interface Overview; Table 12. Supported DIMM Configurations
Functional Description R Intel ® 82845 MCH for SDR Datasheet 109 5.2 System Memory Interface The 845 chipset can be configured to support PC133 SDRAM. 5.2.1 Single Data Rate (SDR) SDRAM Interface Overview The MCH integrates a system memory SDRAM controller with a 64-bit wide interface and twelve sys...
Page 110 - Configuration Mechanism For DIMMs; Memory Detection and Initialization; Memory Register Programming; Table 13. Data Bytes on DIMM Used for Programming DRAM Registers
Functional Description R 110 Intel ® 82845 MCH for SDR Datasheet 5.2.2.1 Configuration Mechanism For DIMMs Detection of the type of SDRAM installed on the DIMM is supported via a Serial Presence Detect mechanism as defined in the JEDEC 168-pin DIMM specification. This uses the SCL, SDA and SA[2:0] p...
Page 111 - Memory Address Translation and Decoding; Table 14. Address Translation and Decoding
Functional Description R Intel ® 82845 MCH for SDR Datasheet 111 5.2.3 Memory Address Translation and Decoding The 845 MCH contains address decoders that translate the address received on the system bus or the hub interface. Decoding and translation of these addresses vary with the four SDRAM types....
Page 112 - DRAM Performance Description; AGP Interface Overview; AGP Target Operations
Functional Description R 112 Intel ® 82845 MCH for SDR Datasheet 5.2.4 DRAM Performance Description The overall memory performance is controlled by the DRAM Timing (DRT) Register, pipelining depth used in the MCH, memory speed grade, and the type of SDRAM used in the system. In addition, the exact p...
Page 114 - AGP Transaction Ordering; AGP Signal Levels; x AGP Protocol; Writes
Functional Description R 114 Intel ® 82845 MCH for SDR Datasheet 5.3.2 AGP Transaction Ordering The MCH observes transaction ordering rules as defined by the AGP Interface Specification, Revision 2.0 . 5.3.3 AGP Signal Levels The 4x data transfers use 1.5 V signaling levels as described by the AGP I...
Page 115 - Table 16. Data Rate Control Bits; AGP FRAME# Transactions on AGP; MCH Initiator and Target Operations; Table 17. PCI Commands Supported by the Intel
Functional Description R Intel ® 82845 MCH for SDR Datasheet 115 Table 16. Data Rate Control Bits AGPCNTL .FWCE AGPCMD. FWPE AGPCMD. DRATE [bit 2] AGPCMD. DRATE [bit 1] AGPCMD. DRATE [bit 0] MCH =>AGP Master Write Protocol 0 0 X X X 1x 1 1 0 0 1 1x 1 1 0 1 0 2x strobing 1 1 1 0 0 4x strobing 5.3....
Page 116 - target
Functional Description R 116 Intel ® 82845 MCH for SDR Datasheet C/BE[3:0]# Intel ® MCH PCI Command Encoding Cycle Destination Response as a FRAME# Target Dual Address Cycle 1101 N/A No response Memory Read Line 1110 System Memory Read 1110 Hub interface No response Memory Write and Invalidate 1111 ...
Page 117 - MCH Retry/Disconnect Conditions; Delayed Transaction; Power and Thermal Management; Processor Power State Control
Functional Description R Intel ® 82845 MCH for SDR Datasheet 117 MCH Retry/Disconnect Conditions The MCH generates retry/disconnect according to the AGP Interface Specification, Revision 2.0 rules when being accessed as a target from the AGP FRAME# device. Delayed Transaction When an AGP FRAME#-to-s...
Page 118 - Sleep State Control; MCH Clocking
Functional Description R 118 Intel ® 82845 MCH for SDR Datasheet 5.4.2 Sleep State Control • S0 (Awake): In this state all power planes are active. All of the ACPI software “C” states are embedded in this state. • S1: The recommended implementation of S1 state is the same as C2 state (Stop Grant), w...
Page 119 - Electrical; Absolute Maximum Ratings; Table 18. Absolute Maximum Ratings; Characteristics; Table 19. Power Characteristics
Electrical Characteristics R Intel ® 82845 MCH for SDR Datasheet 119 6 Electrical Characteristics This chapter contains the absolute maximum operating ratings, power characteristics, and DC characteristics for the 82845 MCH. 6.1 Absolute Maximum Ratings Table 18 lists the MCH’s maximum environmental...
Page 120 - Groups
Electrical Characteristics R 120 Intel ® 82845 MCH for SDR Datasheet 6.3 Signal Groups The signal description includes the type of buffer used for the particular signal: AGTL+ Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O Specification for complete details. The MCH integrates most AGTL+ ...
Page 122 - Table 21. DC Characteristics
Electrical Characteristics R 122 Intel ® 82845 MCH for SDR Datasheet 6.4 DC Characteristics Table 21. DC Characteristics Symbol Signal Group Parameter Min Typ Max Unit Notes I/O Buffer Supply Voltage VCCSM (u) PC133 SDRAM I/O Voltage 3.135 3.3 3.465 V VCC1_8 (t) 1.8V I/O Supply Voltage 1.71 1.8 1.89...
Page 125 - Ballout and Package Information
Ballout and Package Information R Intel ® 82845 MCH for SDR Datasheet 125 7 Ballout and Package Information This chapter provides the MCH ballout and package information. The ballout footprint is shown in Figure 6 and Figure 7. These figures represent the ballout organized by ball number. Table 22 p...
Page 126 - 2845 MCH Ballout Diagram (Top View—Left Side)
Ballout and Package Information R 126 Intel ® 82845 MCH for SDR Datasheet Figure 6. Intel ® 82845 MCH Ballout Diagram (Top View—Left Side) 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AJ VSS VCC1_5 VTT VTT VTT VSS VSS AH SBA0 SBA1 G_GNT# VSS VSS VSS HD61# HD57# AG VCC1_5 SBA2 SBA3 ST2 ST0 G_REQ# VTT...
Page 127 - 2845 MCH Ballout Diagram (Top View—Right Side)
Ballout and Package Information R Intel ® 82845 MCH for SDR Datasheet 127 Figure 7. Intel ® 82845 MCH Ballout Diagram (Top View—Right Side) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VSS VSS VSS VSS VSS VSS AJ HD49# HD44# DBI2# HD24# HD31# HD25# HD20# AH HD52# HD48# HD45# HD42# HD43# HD38# HD27# HD28# HD29# H...
Page 128 - 2845 MCH Ballout Listed Alphabetically by Signal Name
Ballout and Package Information R 128 Intel ® 82845 MCH for SDR Datasheet Table 22. Intel ® 82845 MCH Ballout Listed Alphabetically by Signal Name Signal Name Ball # 66IN P22 AD_STB0 R24 AD_STB0# R23 AD_STB1 AC27 AD_STB1# AC28 ADS# V3 AGPREF AA21 BCLK# K8 BCLK J8 BNR# W3 BPRI# Y7 BR0# V7 CPURST# AE1...
Page 134 - Package Mechanical Information
Ballout and Package Information R 134 Intel ® 82845 MCH for SDR Datasheet 7.1 Package Mechanical Information This section provides the MCH package mechanical dimensions. The package is a 593 ball FC-BGA. Figure 8. Intel ® MCH FC-BGA Package Dimensions (Top and Side View) p k g _ o lg a _5 9 3 _ to p...
Page 137 - Testability; Figure 10. XOR Tree Chain; XOR Test Mode Initialization
Testability R Intel ® 82845 MCH for SDR Datasheet 137 8 Testability In the MCH, testability for Automated Test Equipment (ATE) board-level testing has been implemented as an XOR chain. An XOR-tree is a chain of XOR gates, each with one input pin connected to it (see Figure 10). Figure 10. XOR Tree C...
Page 138 - Chains; Table 23. XOR Chain 0
Testability R 138 Intel ® 82845 MCH for SDR Datasheet 8.2 XOR Chains Note: RSTIN#, TESTIN#, and all Rcomp buffers are not part of any XOR chain. Table 23. XOR Chain 0 Chain 0 Ball Element # Signal Name Note Initial Logic Level AE6 1 HDSTBP1# Input 1 AD3 2 HDSTBP0# Input 1 V3 3 ADS# Input 1 U6 4 HREQ...
Page 140 - Table 24. XOR Chain 1
Testability R 140 Intel ® 82845 MCH for SDR Datasheet Table 24. XOR Chain 1 Chain 1 Ball Element # Signal Name Note Initial Logic Level N6 1 HADSTDB1# Input 1 H7 2 SCS6# Input 1 G10 3 SCKE2 Input 1 G5 4 SCK11 Input 1 F4 5 SCKE1 Input 1 F3 6 SCK6 Input 1 C2 7 SCK3 Input 1 B2 8 SDQ31 Input 1 E2 9 SCK2...
Page 141 - Table 25. XOR Chain 2
Testability R Intel ® 82845 MCH for SDR Datasheet 141 Table 25. XOR Chain 2 Chain 2 Ball Element # Signal Name Note Initial Logic Level D10 1 SDQ54 Input 1 C10 2 SDQ21 Input 1 C11 3 SDQ52 Input 1 F9 4 SDQ22 Input 1 B11 5 SDQ19 Input 1 B13 6 SDQ16 Input 1 G11 7 SCKE4 Input 1 C12 8 SDQ18 Input 1 F11 9...
Page 142 - Table 26. XOR Chain 3
Testability R 142 Intel ® 82845 MCH for SDR Datasheet Table 26. XOR Chain 3 Chain 3 Ball Element # Signal Name Note Initial Logic Level G10 1 SCKE0 Input 1 G12 2 SMA12 Input 1 G15 3 SCK4 Input 1 F13 4 SCK0 Input 1 C14 5 SCB3 Input 1 E14 6 SDQ48 Input 1 D14 7 SCB7 Input 1 C15 8 SCB6 Input 1 G17 9 SBC...
Page 143 - Table 27. XOR Chain 4
Testability R Intel ® 82845 MCH for SDR Datasheet 143 Chain 3 Ball Element # Signal Name Note Initial Logic Level B25 35 SDQ6 Input 1 C25 36 SDQ38 Input 1 C27 37 SDQ3 Input 1 D27 38 SDQ35 Input 1 B27 39 SDQ36 Input 1 C26 40 RSVD Input 1 F23 41 SDQ8 Input 1 E24 42 SDQ39 Input 1 E25 43 SDQ5 Input 1 E2...
Page 144 - Table 28. XOR Chain 5
Testability R 144 Intel ® 82845 MCH for SDR Datasheet Chain 4 Ball Element # Signal Name Note Initial Logic Level N27 20 HI_2 Input 1 M26 21 HI_4 Input 1 N25 22 HI_STB Input 1 L27 23 HI_7 Input 1 P25 24 HI_0 Input 1 P23 25 HI_3 Input 1 P24 26 HI_1 Input 1 R27 27 G_ADO Input 1 R28 28 G_AD1 Input 1 U2...
Page 146 - Table 29. XOR Chain 6
Testability R 146 Intel ® 82845 MCH for SDR Datasheet Table 29. XOR Chain 6 Chain 6 Ball Element # Signal Name Note Initial Logic Level AC27 1 AD_STB1 Input 1 AF27 2 SB_STB Input 1 AE17 3 CPURST# Input 1 AD17 4 HD62# Input 1 AE16 5 HD63# Input 1 AH15 6 HD57# Input 1 AG15 7 HD54# Input 1 AF16 8 HD59#...
Page 147 - Table 30. XOR Chain 7
Testability R Intel ® 82845 MCH for SDR Datasheet 147 Chain 6 Ball Element # Signal Name Note Initial Logic Level AC9 35 HD35# Input 1 AD9 36 HD37# Input 1 AH7 37 HD24# Input 1 AH5 38 HD31# Input 1 AG8 39 HD27# Input 1 Y4 40 DEFER# Input 1 W7 41 RS1# Input 1 AE24 42 SBA6 Output N/A Table 30. XOR Cha...
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