Page 2 - Legal
Intel ® 82575EB Gigabit Ethernet Controller — Legal Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 2 January 2011 Legal INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY E...
Page 3 - Revisions
Revisions — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 3 Revisions Revision Date Description .25 2/2006 Initial release (Intel Secret). 1.1 1/2008 • Updated Section 13.4.8....
Page 4 - Content
Intel ® 82575EB Gigabit Ethernet Controller — Content Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 4 January 2011 Content 1.0 Introduction ...............................................................................................
Page 18 - NOTE: This page intentionally left blank.
Intel ® 82575EB Gigabit Ethernet Controller — Content Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 18 January 2011 NOTE: This page intentionally left blank.
Page 19 - Register and Bit References; Byte and Bit Designations
Introduction — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 19 1.0 Introduction This document describes the external architecture (including device operation, register defini...
Page 20 - Memory Alignment Terminology
Intel ® 82575EB Gigabit Ethernet Controller — Memory Alignment Terminology Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 20 January 2011 • PCI Express* Card Electromechanical Specification, Rev 1.1RD, November 2004• PICMG3.1 Etherne...
Page 21 - Architectural Overview; External Architecture
Architectural Overview — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 21 2.0 Architectural Overview This section provides an overview of the 82575 . The following sections gi...
Page 22 - System Interface
Intel ® 82575EB Gigabit Ethernet Controller — Integrated 10/100/1000 Mb/s PHY Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 22 January 2011 Figure 1. 82575 External Interfaces 2.1.1 Integrated 10/100/1000 Mb/s PHY The 82575 contains...
Page 23 - Flash Memory Interface; Software Watchdog
Flash Memory Interface — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 23 2.1.4 Flash Memory Interface The 82575 provides an external serial interface to a FLASH device. Acces...
Page 24 - LEDs; DMA Addressing
Intel ® 82575EB Gigabit Ethernet Controller — LEDs Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 24 January 2011 the four pins is configurable via EEPROM as well as the default value of any pins configured as outputs. To avoid signa...
Page 25 - Ethernet Addressing
Ethernet Addressing — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 25 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e Example 1. Byt...
Page 26 - Interrupt Control and Tuning; Hardware Acceleration Capability
Intel ® 82575EB Gigabit Ethernet Controller — Interrupt Control and Tuning Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 26 January 2011 Table 2. Intel® Architecture Byte Ordering Note: The notation in this manual follows the conven...
Page 27 - Jumbo Frame Support; Buffer and Descriptor Structure
Jumbo Frame Support — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 27 2.5.1 Jumbo Frame Support The 82575 supports jumbo frames to increase performance and decrease CPU utili...
Page 28 - Multiple Transmit Queues
Intel ® 82575EB Gigabit Ethernet Controller — Multiple Transmit Queues Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 28 January 2011 The software gives the hardware ownership of a queue of buffers for receives. These receive buffers...
Page 29 - Power Up State
General Initialization and Reset Operation — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 29 3.0 General Initialization and Reset Operation This section lists all necessary i...
Page 30 - Global Reset and General Configuration; Receive Initialization
Intel ® 82575EB Gigabit Ethernet Controller — Global Reset and General Configuration Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 30 January 2011 After the initialization completes, a typical driver enables the desired interrupts b...
Page 31 - Initialize the Receive Control Register; Transmit Initialization
Initialize the Receive Control Register — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 31 • Enable the queue by setting RXDCTL.ENABLE. In the case of queue zero, the enable b...
Page 32 - Dynamic Queue Enabling and Disabling; Link Setup Mechanisms and Control/Status; PHY Initialization
Intel ® 82575EB Gigabit Ethernet Controller — Dynamic Queue Enabling and Disabling Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 32 January 2011 • Set the length register to the size of the descriptor ring. • Program the TXDCTL regi...
Page 37 - Reset Operation
Reset Operation — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 37 PCS_LCTL.FDV - Should be set by software to the duplex value established via software priority resolution PC...
Page 41 - PHY Behavior During a Manageability Session:
PHY Behavior During a Manageability Session: — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 41 b. IP Address Valid.c. IPv4 Address Tabled. IPv6 Address Tablee. Flexible Filte...
Page 42 - Initialization of Statistics
Intel ® 82575EB Gigabit Ethernet Controller — Initialization of Statistics Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 42 January 2011 The Keep_PHY_Link_Up bit is set by the BMC through a command on the sideband interface. It is c...
Page 43 - EEPROM and Flash Interface; EEPROM Device; Software Accesses
EEPROM and Flash Interface — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 43 4.0 EEPROM and Flash Interface This section describes the EEPROM and Flash interfaces supported b...
Page 44 - Signature and CRC Fields
Intel ® 82575EB Gigabit Ethernet Controller — Signature and CRC Fields Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 44 January 2011 Software can use the EEPROM Read register (EERD) to cause the 82575 to read a word from the EEPROM ...
Page 45 - Protected EEPROM Space; Initial EEPROM Programming
Protected EEPROM Space — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 45 This mechanism uses an SMBus message that the firmware is able to receive in all modes, no matter wha...
Page 46 - Activating the Protection Mechanism; Non Permitted Accesses to Protected Areas in
Intel ® 82575EB Gigabit Ethernet Controller — Activating the Protection Mechanism Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 46 January 2011 sequence, the 82575 reads the hardware initialization words in the EEPROM. If the signat...
Page 49 - Flash Interface Operation
Flash Interface Operation — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 49 /* Poll the ready bit to see if the MDI read completed */ for (i = 0; i < E1000_GEN_POLL_TIMEOU...
Page 50 - Flash Write Control; Shared EEPROM; EEPROM Deadlock Avoidance
Intel ® 82575EB Gigabit Ethernet Controller — Flash Write Control Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 50 January 2011 To directly access the Flash, software needs to: 1. Write a 1b to the Flash Request bit (FLA.FL_REQ)2. R...
Page 51 - EEPROM Map Shared Words; Shared FLASH
EEPROM Map Shared Words — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 51 • Hardware auto read.• Accesses of port 0 LAN driver.• Accesses of port 1 LAN driver.• Firmware acce...
Page 52 - Flash Access Contention; EEPROM Map
Intel ® 82575EB Gigabit Ethernet Controller — Flash Access Contention Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 52 January 2011 4.4.1 Flash Access Contention The 82575 implements internal arbitration between Flash accesses initi...
Page 54 - Hardware Accessed Words
Intel ® 82575EB Gigabit Ethernet Controller — Hardware Accessed Words Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 54 January 2011 4.5.1 Hardware Accessed Words This section describes the EEPROM words that are loaded by the 82575 h...
Page 63 - NC-SI and PCIe* Completion Timeout Configuration
Hardware Accessed Words — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 63 The description of bits 13 and 11 in various combinations are as follows: 4.5.1.11 NC-SI and PCIe* C...
Page 72 - Management Hardware Configuration Control (Word
Intel ® 82575EB Gigabit Ethernet Controller — Hardware Accessed Words Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 72 January 2011 4.5.1.22 Functions Control (Word 21h) 4.5.1.23 LAN Power Consumption (Word 22h) This word is meaning...
Page 74 - End of RO Area (Word 2Ch; Main Setup Options PCI Function 0 (Word 30h)
Intel ® 82575EB Gigabit Ethernet Controller — Hardware Accessed Words Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 74 January 2011 4.5.1.25 End of RO Area (Word 2Ch 4.5.1.26 Start of RO Area (Word 2Dh) 4.5.1.27 Watchdog Configurati...
Page 76 - Configuration Customization Options PCI Function 0 (Word 31h)
Intel ® 82575EB Gigabit Ethernet Controller — Hardware Accessed Words Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 76 January 2011 4.5.1.29.2 Configuration Customization Options PCI Function 0 (Word 31h) Word 31h of the EEPROM cont...
Page 78 - Configuration Customization Options PCI Function 1 (Word 35h); Configuration Customization Options PCI Function 2 (Word 39h); Configuration Customization Options PCI Function 3 (Word 3Bh); iSCSI Boot Configuration Offset (Word 3Dh); iSCSI Module Structure
Intel ® 82575EB Gigabit Ethernet Controller — Hardware Accessed Words Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 78 January 2011 4.5.1.29.6 Configuration Customization Options PCI Function 1 (Word 35h) This word is the same as wo...
Page 81 - Manageability Control Sections; Sideband Configuration Structure
Manageability Control Sections — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 81 4.6 Manageability Control Sections 4.6.1 Sideband Configuration Structure 4.6.1.1 Section Hea...
Page 83 - Flex TCO Filter Configuration Structure
Flex TCO Filter Configuration Structure — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 83 4.6.1.5 SMBus Fail-Over Register (Low Word) - (0ffset 04h) 4.6.1.6 SMBus Fail-Over R...
Page 85 - NC-SI Microcode Download Structure
NC-SI Microcode Download Structure — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 85 4.6.2.2 Flex Filter Length and Control - (0ffset 01h) 4.6.2.3 Flex Filter Enable Mask - (...
Page 86 - NC-SI Configuration Structure
Intel ® 82575EB Gigabit Ethernet Controller — NC-SI Configuration Structure Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 86 January 2011 4.6.4 NC-SI Configuration Structure 4.6.4.1 Section Header - (0ffset 0h) 4.6.4.2 Rx Mode Contr...
Page 87 - Common Firmware Pointer
Common Firmware Pointer — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 87 4.6.4.5 Tx Mode Control2 (RT_CTRL[31:16]) (Offset 04h) 4.6.4.6 MAC Tx Control Reg1 (TxCntrlReg1 (15:...
Page 88 - Manageability Capability/Manageability Enable (Word; Pass Through Pointers; Flex TCO Filter Configuration Pointer (Word 58h)
Intel ® 82575EB Gigabit Ethernet Controller — Pass Through Pointers Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 88 January 2011 4.6.5.1 Manageability Capability/Manageability Enable (Word 54h) 4.6.6 Pass Through Pointers 4.6.6.1 P...
Page 90 - PT LAN Configuration Structure
Intel ® 82575EB Gigabit Ethernet Controller — PT LAN Configuration Structure Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 90 January 2011 4.6.6.4 PT LAN1 Configuration Pointer (Word 59h) 4.6.6.5 NC-SI Microcode Download Pointer (Wo...
Page 92 - LAN0 UDP Flex Filter Ports 0:15 MFUTP Registers
Intel ® 82575EB Gigabit Ethernet Controller — PT LAN Configuration Structure Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 92 January 2011 4.6.7.13 LAN0 UDP Flex Filter Ports 0:15; MFUTP Registers (Offset 15h:24h) 4.6.7.14 LAN0 VLAN...
Page 97 - ARP Response IPv4 Address 0 LSB (Offset 43h)
PT LAN Configuration Structure — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 97 4.6.7.26 ARP Response IPv4 Address 0 LSB (Offset 43h) 4.6.7.27 ARP Response IPv4 Address 0 MS...
Page 98 - Software Owned EEPROM Words
Intel ® 82575EB Gigabit Ethernet Controller — Software Owned EEPROM Words Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 98 January 2011 4.6.7.32 LAN0 IPv6 Address 0 LSB; MIPAF (Offset 49h) 4.6.7.33 LAN0 IPv6 Address 0 MSB; MIPAF (Of...
Page 101 - Transmit Data Flow
Receive and Transmit Description — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 101 5.0 Receive and Transmit Description This section describes the data flows, packet recepti...
Page 102 - Receive Data Flow
Intel ® 82575EB Gigabit Ethernet Controller — Receive Data Flow Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 102 January 2011 5.2 Receive Data Flow Receive Data Flow provides a high level description of all data/control transformat...
Page 103 - Packet Address Filtering; Receive Data Storage
Packet Address Filtering — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 103 5.3.1 Packet Address Filtering Hardware stores incoming packets in host memory subject to the foll...
Page 104 - Legacy Receive Descriptor Format; Length Field
Intel ® 82575EB Gigabit Ethernet Controller — Legacy Receive Descriptor Format Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 104 January 2011 If for any queue SRRCTL[n].BSIZEPACKET equals 0b, the buffer size defined by RCTL.BSIZE is...
Page 105 - Receive Descriptor Status Field
Legacy Receive Descriptor Format — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 105 For packets with a VLAN header, the packet checksum includes the header (if VLAN striping ...
Page 107 - Receive Descriptor Errors Field
Legacy Receive Descriptor Format — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 107 5.3.3.4 Receive Descriptor Errors Field Most error information appears only when the Store...
Page 109 - VLAN Tag Field; Advanced Receive Descriptors; Packet Buffer Address
Advanced Receive Descriptors — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 109 If receive checksum offloading is disabled (RXCSUM.IPOFL & RXCSUM.TUOFL), the IPE and TCPE...
Page 111 - Packet Type
Advanced Receive Descriptors — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 111 5.3.4.3 Packet Type 5.3.4.4 RSS Type The 82575 must identify the packet type and then choose t...
Page 112 - Packet Checksum
Intel ® 82575EB Gigabit Ethernet Controller — Advanced Receive Descriptors Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 112 January 2011 Table 31. Supported Packets Note: The header of the fragmented IPv6 packet is defined until th...
Page 113 - RSS Hash Value
Advanced Receive Descriptors — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 113 This field is mutually exclusive with the RSS Hash Value. It is enabled when the RXCSUM.PCSD b...
Page 114 - Extended Errors
Intel ® 82575EB Gigabit Ethernet Controller — Advanced Receive Descriptors Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 114 January 2011 Note: Unsupported packet types will either have the IXSM bit set, or do not have the IPCS or T...
Page 115 - Packet Buffer (Number of Bytes Exists in the Host
Advanced Receive Descriptors — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 115 5.3.4.10 Packet Buffer (Number of Bytes Exists in the Host Packet Buffer) The length covers th...
Page 116 - Receive UDP Fragmentation Checksum; Receive Descriptor Fetching
Intel ® 82575EB Gigabit Ethernet Controller — Receive UDP Fragmentation Checksum Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 116 January 2011 5.3.4.11 VLAN Tag Field Hardware stores additional information in the receive descriptor...
Page 117 - Receive Descriptor Write-Back; Receive Descriptor Packing; Receive Descriptor Ring Structure
Receive Descriptor Write-Back — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 117 When the number of descriptors in host memory is greater than the available on-chip descripto...
Page 119 - Multiple Receive Queues
Multiple Receive Queues — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 119 These registers hold a value that is an offset from the base and indicates the in-progress descript...
Page 120 - Queuing for Virtual Machine Devices (VMDq); Association Through MAC Address
Intel ® 82575EB Gigabit Ethernet Controller — Queuing for Virtual Machine Devices (VMDq) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 120 January 2011 When receiving an incoming packet, its header is analyzed, according to the prot...
Page 121 - Association Through MAC Address + RSS; Association through VLAN tag ID
Queuing for Virtual Machine Devices (VMDq) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 121 Software can program different values to the MAC filters (any bits in RAH or RAL...
Page 122 - Multiple Receive Queues & Receive-Side Scaling; RSS Hash Function
Intel ® 82575EB Gigabit Ethernet Controller — Multiple Receive Queues & Receive-Side Scaling (RSS) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 122 January 2011 5.4.2 Multiple Receive Queues & Receive-Side Scaling (RSS) The...
Page 124 - Hash for IPv4 with TCP
Intel ® 82575EB Gigabit Ethernet Controller — Multiple Receive Queues & Receive-Side Scaling (RSS) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 124 January 2011 The 32-bit result of the hash computation is written into the pack...
Page 125 - Hash for IPv4 with UDP; Indirection Table
Multiple Receive Queues & Receive-Side Scaling (RSS) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 125 5.4.2.1.2 Hash for IPv4 with UDP Concatenate SourceAddress, Destin...
Page 126 - Support for Multiple Processors; RSS Verification Suite
Intel ® 82575EB Gigabit Ethernet Controller — RSS Verification Suite Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 126 January 2011 5.4.2.3 Support for Multiple Processors It is assumed that each queue is associated with a specific ...
Page 127 - Header Splitting and Replication
Header Splitting and Replication — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 127 5.5 Header Splitting and Replication This feature consists of splitting or replicating a p...
Page 130 - Receive Packet Checksum Offloading
Intel ® 82575EB Gigabit Ethernet Controller — Receive Packet Checksum Offloading Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 130 January 2011 5.5.1 Receive Packet Checksum Offloading The 82575 supports the offloading of three rece...
Page 131 - MAC Address Filter
Receive Packet Checksum Offloading — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 131 Table 34 lists the general details about what packets are processed. In more detail, the...
Page 132 - IPv6 Extension Headers
Intel ® 82575EB Gigabit Ethernet Controller — Receive Packet Checksum Offloading Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 132 January 2011 5.5.1.5 IPv6 Extension Headers IPv4 and TCP provide header lengths that allow hardware t...
Page 133 - Packet Transmission
Packet Transmission — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 133 Table 35. Next Header Type Encodings Note: The 82575 hardware acceleration does not support all IPv6 Ex...
Page 134 - Transmit Data Storage
Intel ® 82575EB Gigabit Ethernet Controller — Transmit Data Storage Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 134 January 2011 Output packets are made up of pointer–length pairs constituting a descriptor chain (so called descrip...
Page 135 - Transmit Descriptors; Legacy Transmit Descriptor Format
Transmit Descriptors — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 135 Each context defines information about the packet sent including the total size of the MAC header (TDE...
Page 136 - Transmit Descriptor Write Back Format; Length
Intel ® 82575EB Gigabit Ethernet Controller — Transmit Descriptor Write Back Format Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 136 January 2011 Table 36. Transmit Descriptor (TDESC) Layout – Legacy Mode 5.6.5 Transmit Descriptor ...
Page 139 - Transmit Descriptor Status Field Format; Transmit Descriptor Special Field Format
Transmit Descriptor Special Field Format — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 139 5.6.5.4 Transmit Descriptor Status Field Format Table 38. Transmit Status Layout 5...
Page 140 - Advanced Transmit Context Descriptor
Intel ® 82575EB Gigabit Ethernet Controller — Advanced Transmit Context Descriptor Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 140 January 2011 Table 39. Special Field (TDESC.SPECIAL) Layout 5.6.7 Advanced Transmit Context Descrip...
Page 142 - Advanced Transmit Data Descriptor
Intel ® 82575EB Gigabit Ethernet Controller — Advanced Transmit Data Descriptor Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 142 January 2011 Table 42. Advanced Transmit Context Descriptor Required Valid Fields 5.6.8 Advanced Trans...
Page 143 - DCMD
Advanced Transmit Data Descriptor — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 143 5.6.8.4 DCMD DCMD Layout Field Description TSE TCP Segmentation Enable Indicates a TCP se...
Page 144 - STA; IDX; PAYLEN; Transmit Descriptor Ring Structure
Intel ® 82575EB Gigabit Ethernet Controller — Transmit Descriptor Ring Structure Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 144 January 2011 5.6.8.5 STA Table 45. STA Layout 5.6.8.6 IDX Index into the hardware context table to in...
Page 146 - Transmit Descriptor Fetching; Transmit Descriptor Write-Back
Intel ® 82575EB Gigabit Ethernet Controller — Transmit Descriptor Fetching Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 146 January 2011 address = base + (ptr * 16) , where ptr is the value in the hardware head or tail register. Th...
Page 147 - TCP Segmentation
TCP Segmentation — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 147 write-back descriptors. Secondly, to preserve backward compatibility, if the TXDCTL[n].WTHRESH value is 0b...
Page 148 - Assumptions; TCP Segmentation Data Fetch Control; TCP Segmentation Performance
Intel ® 82575EB Gigabit Ethernet Controller — Assumptions Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 148 January 2011 5.8.1 Assumptions The following assumption applies to the TCP Segmentation implementation in the 82575: The RS ...
Page 149 - Packet Format; TCP Segmentation Indication
Packet Format — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 149 • The stack does not need to partition the block to fit the MTU size (saves CPU cycles).• The stack only comp...
Page 151 - IP and TCP/UDP Headers
IP and TCP/UDP Headers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 151 • UDP Header: — The 82575’s DMA function fetches the Ethernet, IP, and TCP/UDP prototype header info...
Page 157 - TCP/IP/UDP Header for the Subsequent Frames
IP/TCP/UDP Header Updating — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 157 5.8.7.1 TCP/IP/UDP Header for the First Frame The hardware makes the following changes to the he...
Page 158 - Offloading
Intel ® 82575EB Gigabit Ethernet Controller — IP/TCP/UDP Transmit Checksum Offloading Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 158 January 2011 — UDP Checksum 5.8.7.3 TCP/IP/UDP Header for the Last Frame Hardware makes the foll...
Page 159 - Offloading in Non-Segmentation Mode; IP Checksum
IP/TCP/UDP Transmit Checksum Offloading in Non-Segmentation Mode — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 159 5.10 IP/TCP/UDP Transmit Checksum Offloading in Non-Segmen...
Page 160 - TCP Checksum
Intel ® 82575EB Gigabit Ethernet Controller — TCP Checksum Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 160 January 2011 As mentioned in Section 5.6.2 , it is not necessary to set a new context for each new packet. In many cases, t...
Page 161 - Tx Completions Head Write-Back
Tx Completions Head Write-Back — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 161 • Round robin arbitration is performed among the LP queues. Note: In order to prevent starva...
Page 162 - Interrupts
Intel ® 82575EB Gigabit Ethernet Controller — Interrupts Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 162 January 2011 Head write-back occurs if TDWBAL#.Head_WB_En is set for this queue and the RS bit is set in the Tx descriptor, f...
Page 163 - Interrupt Acknowledge Auto-mask register
Interrupt Cause Set Register (ICS) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 163 Note: When EICR is used in MSI-X mode, the Rx / Tx related bits in ICR should be masked....
Page 164 - Extended Interrupt Cause Set Register (EICS)
Intel ® 82575EB Gigabit Ethernet Controller — Extended Interrupt Cause Set Register (EICS) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 164 January 2011 5.13.7 Extended Interrupt Cause Set Register (EICS) This registers enables the...
Page 165 - Interrupt Modes Setting Bits; Interrupt Moderation
Interrupt Modes Setting Bits — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 165 5.13.11 Interrupt Modes Setting Bits There are bits in the CTRL_EXT register that define the b...
Page 168 - Clearing Interrupt Causes
Intel ® 82575EB Gigabit Ethernet Controller — Clearing Interrupt Causes Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 168 January 2011 Figure 21. Case A: Heavy Load, Interrupts Moderated Figure 22. Case B: Light Load, Interrupts Imm...
Page 169 - Write to Clear; Dynamic Interrupt Moderation
Write to Clear — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 169 5.15.2 Write to Clear In the case where the software device driver wants to configure itself in MSI-X mode t...
Page 170 - TCP Timer Interrupt; Memory Error Correction and Detection
Intel ® 82575EB Gigabit Ethernet Controller — TCP Timer Interrupt Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 170 January 2011 5.16.1 TCP Timer Interrupt In order to implement TCP timers for I/OAT 2, software needs to take action ...
Page 171 - General Functionality
PCIe* Local Bus Interface — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 173 6.0 PCIe* Local Bus Interface This section describes the software interface and some related hard...
Page 172 - Data Alignment; KB Boundary; Transaction Attributes; Traffic Class and Virtual Channels
Intel ® 82575EB Gigabit Ethernet Controller — Data Alignment Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 174 January 2011 6.1.3 Data Alignment 6.1.3.1 4 KB Boundary Requests must not specify an address/length combination causing m...
Page 173 - Relaxed Ordering; No Snoop and Relaxed Ordering for LAN Traffic; No Snoop Option for Payload
Transaction Attributes — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 175 6.1.4.2 Relaxed Ordering The 82575 takes advantage of the relaxed ordering rules of the PCIe* Specif...
Page 174 - Flow Control; Flow Control Rules; Upstream Flow Control Tracking
Intel ® 82575EB Gigabit Ethernet Controller — Flow Control Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 176 January 2011 Under certain conditions that occur when I/OAT is enabled, software knows that it is safe to transfer a new pa...
Page 175 - Flow Control Update Frequency; Host Interface; Tag IDs
Flow Control Update Frequency — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 177 6.2.3 Flow Control Update Frequency In any case, UpdateFC packets are scheduled immediately a...
Page 179 - Completion Timeout Mechanism
Completion Timeout Mechanism — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 181 IDs are as in data movement engine 1 mode. When in data movement engine 2 mode, messages and M...
Page 180 - Error Events and Error Reporting; Error Events
Intel ® 82575EB Gigabit Ethernet Controller — Error Events and Error Reporting Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 182 January 2011 • Version = 2h - Programmed through PCI configuration. Visible through the Completion_Time...
Page 182 - Error Pollution
Intel ® 82575EB Gigabit Ethernet Controller — Error Pollution Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 184 January 2011 6.4.2 Error Pollution Error pollution can occur if error conditions for a given transaction are not isolate...
Page 183 - Link Layer; Supported DLLPs
Link Layer — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 185 2. Changes in the response to some Uncorrectable Non-Fatal errors detected in non-posted requests to the 82575 c...
Page 184 - Transmit EDB Nullifying; Physical Layer; Link Width
Intel ® 82575EB Gigabit Ethernet Controller — Transmit EDB Nullifying Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 186 January 2011 The following DLLPs are supported by the 82575 as a transmitter. 6.5.3 Transmit EDB Nullifying In c...
Page 185 - Polarity Inversion
Link Width — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 187 The max link width is loaded into the Maximum Link Width field of the PCIe* Capability register (LCAP[11:6]). Th...
Page 186 - Reset; Performance Monitoring; PCI Compatibility
Intel ® 82575EB Gigabit Ethernet Controller — Performance Monitoring Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 188 January 2011 6.6.1.5 Reset The PCIe* Physical layer can supply a core reset to the 82575. The reset can be caused...
Page 187 - Mandatory PCI Configuration Registers
Mandatory PCI Configuration Registers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 189 The LAN0 and LAN1 are shown in PCI functions 0 and PCI functions 1, respectively. The...
Page 193 - PCI Power Management Registers
PCI Power Management Registers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 195 Read and write registers programmed by software indicate the type of system interrupt reques...
Page 195 - Message Signaled Interrupt (MSI) Configuration
PCI Power Management Registers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 197 PMCSR_BSE Bridge Support Extensions: 1 Byte, Offset 46h, (RO) This field is 1 byte at offset...
Page 199 - PCIe* Configuration Registers
PCI Power Management Registers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 201 Table 71. MSI-X PBA Table Offset To request service using a given MSI-X Table entry, a funct...
Page 208 - PCIe* Extended Configuration Space
Intel ® 82575EB Gigabit Ethernet Controller — PCI Power Management Registers Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 210 January 2011 6.6.5.3.1 PCIe* Extended Configuration Space PCIe* Configuration Space is located in a flat ...
Page 209 - Advanced Error Reporting Capability
PCI Power Management Registers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 211 PCIe* Extended Configuration Space is allocated using a linked list of optional or required ...
Page 213 - Power States
Power Management — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 215 7.0 Power Management The 82575 supports the Advanced Configuration and Power Interface (ACPI) Specificatio...
Page 214 - Auxiliary Power; Form Factor Power Limits
Intel ® 82575EB Gigabit Ethernet Controller — Auxiliary Power Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 216 January 2011 Figure 23. Power States and Transitions 7.2 Auxiliary Power If DisableD3Cold equals 0b, the 82575 uses the ...
Page 215 - Power Management Interconnects; PCIe* Link Power Management
Power Management Interconnects — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 217 Note: This auxiliary current limit only applies when the primary 3.3V voltage source is not ...
Page 217 - PHY Power Management; Link Speed Control
Power Management Interconnects — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 219 Figure 24. Link Power Management 7.4.0.2 NC-SI Clock Control The 82575 can be configured to ...
Page 218 - D0a State
Intel ® 82575EB Gigabit Ethernet Controller — Power Management Interconnects Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 220 January 2011 This avoids negotiating through the LPLU procedure a link speed that is not advertised by th...
Page 219 - Link Energy Detect
Power Management Interconnects — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 221 7.4.0.3.3 Non-D0a State The PHY can negotiate to a low speed while in a non-D0a states (Dr, ...
Page 220 - Dr State; Dr Disable Mode
Intel ® 82575EB Gigabit Ethernet Controller — Power States Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 222 January 2011 7.4.0.3.6 SerDes/SGMII Power-Down State Each of the 82575’s SerDes enters a power-down state when none of its ...
Page 221 - Entry to Dr State; D0 Uninitialized State; Entry to D0u State
Power States — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 223 • Pass through manageability is disabled• ACPI PME is disabled for all PCI functions• The 82575 Disable Power ...
Page 222 - D0 Active State; Entry to D0a State; D3 State; Entry to D3 State
Intel ® 82575EB Gigabit Ethernet Controller — Power States Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 224 January 2011 On a transition from D3 to D0u, the 82575 PCI Configuration space is not reset. However, the 82575 requires th...
Page 223 - Master Disable
Power States — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 225 As a response to being programmed into the D3 state, the 82575 brings its PCIe* link into the L1 link state. A...
Page 224 - Power-State Transitions Timing
Intel ® 82575EB Gigabit Ethernet Controller — Power-State Transitions Timing Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 226 January 2011 7.4.2 Power-State Transitions Timing The following sections give detailed timing for the sta...
Page 225 - Transition from D0a to D3 and Back without PE_RST_N
Power-State Transitions Timing — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 227 7.4.2.2 Transition from D0a to D3 and Back without PE_RST_N 13 A first PCIe* configuration a...
Page 226 - Transition from D0a to D3 and Back with PE_RST_N
Intel ® 82575EB Gigabit Ethernet Controller — Power-State Transitions Timing Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 228 January 2011 7.4.2.3 Transition from D0a to D3 and Back with PE_RST_N Notes 1 Writing 11b to the Power St...
Page 227 - D0a to Dr and Back without Transition to D3
Power-State Transitions Timing — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 229 7.4.2.4 D0a to Dr and Back without Transition to D3 7.4.2.5 Timing Requirements The 82575 re...
Page 228 - Timing Guarantees
Intel ® 82575EB Gigabit Ethernet Controller — 82575 and SerDes Power-Down State Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 230 January 2011 7.4.2.6 Timing Guarantees The 82575 guarantees the following start up and power state tra...
Page 229 - Wake Up; Advanced Power Management Wakeup
Wake Up — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 231 The SerDes also enters a power-down state in the following cases: • When the 82575 is configured for PHY operation ...
Page 230 - PCIe Power Management Wakeup
Intel ® 82575EB Gigabit Ethernet Controller — PCIe Power Management Wakeup Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 232 January 2011 • Sets the Magic Packet Received bit in the Wake Up Status Register (WUS).• Sets the packet le...
Page 231 - Directed Exact Packet
Wake-Up Packets — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 233 PE_WAKE_N remains asserted until the operating system either writes a 1b to the PME_Status bit of the PMCSR...
Page 232 - Broadcast
Intel ® 82575EB Gigabit Ethernet Controller — Wake-Up Packets Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 234 January 2011 For multicast packets, the upper bits of the destination address in the incoming packet index a bit vector....
Page 233 - ARP/IPv4 Request Packet
Wake-Up Packets — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 235 Note: Accepting broadcast magic packets for wake up purposes when Broadcast Accept bit of the Receive Contr...
Page 234 - Directed IPv6 Packet; Flexible Filter
Intel ® 82575EB Gigabit Ethernet Controller — Wake-Up Packets Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 236 January 2011 7.5.3.1.7 Directed IPv6 Packet The 82575 supports reception of Directed IPv6 packets for wake up if the IPv...
Page 235 - IPX Diagnostic Responder Request Packet
Wake-Up Packets — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 237 Filter Value Table (FFVT). These contain separate values for each filter. The software must also enable the...
Page 236 - IPv6 Neighbor Discovery Filter; Wake Up Packet Storage
Intel ® 82575EB Gigabit Ethernet Controller — Wake-Up Packets Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 238 January 2011 7.5.3.2.3 IPv6 Neighbor Discovery Filter In Ipv6, a Neighbor Discovery packet is used for address resolutio...
Page 237 - DCA; Implementation Details
DCA — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 239 8.0 DCA This section describes the Direct Cache Access (DCA) functionality for the 82575. Direct Cache Access (DCA) is ...
Page 240 - Interface
Intel ® 82575EB Gigabit Ethernet Controller — Internal MAC/PHY 10/100/1000Base-T Interface Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 242 January 2011 The internal copper PHY features 10/100/1000BASE-T signaling and is capable of...
Page 241 - Duplex Operation for Copper PHY; Full Duplex
Duplex Operation for Copper PHY Operation — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 243 Software can use MDIO accesses to read or write registers in either 1000Base-T or...
Page 242 - Half Duplex; B10B Encoding/Decoding
Intel ® 82575EB Gigabit Ethernet Controller — Half Duplex Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 244 January 2011 9.2.2 Half Duplex In half duplex mode, the 82575 attempts to avoid contention with other traffic on the wire, b...
Page 243 - Code Groups and Ordered Sets
SGMII Encoding in 10/100 Mb/s — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 245 9.2.3.2 Code Groups and Ordered Sets Code group and ordered set definitions are defined in cl...
Page 244 - Auto-Negotiation and Link Setup; SerDes Link Configuration; SerDes Mode Auto-Negotiation
Intel ® 82575EB Gigabit Ethernet Controller — Auto-Negotiation and Link Setup Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 246 January 2011 9.3 Auto-Negotiation and Link Setup The method for configuring the link between two link pa...
Page 245 - PCS Hardware Auto-Negotiation; Forcing Link
SerDes Link Configuration — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 247 A set of registers is provided to facilitate hardware Auto-Negotiation. Note: Hardware Auto-Negot...
Page 246 - Hardware Detection of Non-Auto-Negotiation Partner
Intel ® 82575EB Gigabit Ethernet Controller — SerDes Link Configuration Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 248 January 2011 there is a valid signal being received by the optics or the SerDes. The source of the signal dete...
Page 247 - Copper PHY Link Configuration; MAC Speed Resolution; Forcing MAC Speed
Copper PHY Link Configuration — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 249 9.3.2 Copper PHY Link Configuration When operating with the internal PHY, link configuration ...
Page 248 - Using Internal PHY Direct Link-Speed Indication; MAC Full/Half Duplex Resolution
Intel ® 82575EB Gigabit Ethernet Controller — Copper PHY Link Configuration Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 250 January 2011 There might be circumstances when the software device driver must forcibly set the link speed...
Page 249 - Comments Regarding Forcing Link; Loss of Signal/Link Status Indication
Loss of Signal/Link Status Indication — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 251 • Resetting the PHY• Setting preferred link configuration for advertisement during th...
Page 250 - MAC Control Frames and Reception of Flow Control
Intel ® 82575EB Gigabit Ethernet Controller — Flow Control Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 252 January 2011 Flow control is implemented as a means of reducing the possibility of receive buffer overflows which result in...
Page 252 - Discard PAUSE Frames and Pass MAC Control; Transmission of PAUSE Frames
Intel ® 82575EB Gigabit Ethernet Controller — Discard PAUSE Frames and Pass MAC Control Frames Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 254 January 2011 Resumption of transmission can occur under the following conditions: • Exp...
Page 253 - Software Initiated PAUSE Frame Transmission; Loopback Support
Software Initiated PAUSE Frame Transmission — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 255 Hardware sends a PAUSE frame if it has previously sent one and the FIFO overflo...
Page 254 - MAC Loopback; Setting the 82575 to MAC Loopback Mode; Internal PHY Loopback; Setting the 82575 to Internal PHY Loopback Mode
Intel ® 82575EB Gigabit Ethernet Controller — MAC Loopback Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 256 January 2011 Figure 28. 82575 Loopback Modes 9.4.1 MAC Loopback In MAC loopback, the PHY and SerDes blocks are not function...
Page 255 - Internal SerDes Loopback; Setting Internal SerDes Loopback Mode; External PHY Loopback
Internal SerDes Loopback — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 257 — Clear the Loopback bit (bit 14) — Set the Auto Neg Enable bit (bit 12) — Register values should ...
Page 256 - Setting External PHY Loopback Mode
Intel ® 82575EB Gigabit Ethernet Controller — External PHY Loopback Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 258 January 2011 9.4.4.1 Setting External PHY Loopback Mode The following procedure should be used to put the 82575 in...
Page 258 - Transmitting and Receiving 802.1q; Adding 802.1q Tags on Transmits
Intel ® 82575EB Gigabit Ethernet Controller — Transmitting and Receiving 802.1q Packets Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 260 January 2011 Table 82. 802.1q Tagged Frames 10.2 Transmitting and Receiving 802.1q Packets Sin...
Page 259 - Stripping 802.1q Tags on Receives; q VLAN Packet Filtering
Stripping 802.1q Tags on Receives — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 261 10.2.2 Stripping 802.1q Tags on Receives Software can instruct the 82575 to strip 802.1q ...
Page 260 - Double VLAN Support
Intel ® 82575EB Gigabit Ethernet Controller — Double VLAN Support Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 262 January 2011 Table 84. Packet Reception Decision Table 10.4 Double VLAN Support The 82575 supports a mode where all ...
Page 261 - PHY Functionality and Features; Auto MDIO Register Initialization; General Register Initialization
PHY Functionality and Features — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 263 11.0 PHY Functionality and Features The PHY default configuration is determined by data from...
Page 262 - Determining Link State; False Link
Intel ® 82575EB Gigabit Ethernet Controller — Determining Link State Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 264 January 2011 11.2 Determining Link State The PHY and its link partner determine the type of link established thro...
Page 263 - Forced Operation; Auto Negotiation
Forced Operation — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 265 When the PHY is first powered on, reset, or encounters a link down state, it must determine the line speed...
Page 264 - Parallel Detection; Support for Different Board Layouts
Intel ® 82575EB Gigabit Ethernet Controller — Parallel Detection Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 266 January 2011 11.2.4 Parallel Detection Parallel detection can only be used to establish 10 and 100 links. It occurs w...
Page 265 - Link Criteria; SmartSpeed
Link Criteria — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 267 11.3 Link Criteria Once the link state is determined—via Auto-Negotiation, parallel detection or forced opera...
Page 266 - Using SmartSpeed
Intel ® 82575EB Gigabit Ethernet Controller — Flow Control Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 268 January 2011 lower speed: from 1000 to 100 to 10. Once a link is established, and if it is later broken, the PHY automatica...
Page 267 - Management Data Interface
Management Data Interface — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 269 11.5 Management Data Interface The PHY supports the IEEE 802.3 MII Management Interface also know...
Page 268 - Transmit Functions; Scrambler
Intel ® 82575EB Gigabit Ethernet Controller — Transmit Functions Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 270 January 2011 Figure 30. 1000 Base-T PHY Functions Overview 11.8.1 Transmit Functions This section describes functions...
Page 269 - Transmit FIFO; Transmit Phase-Locked Loop PLL; Spectral Shaper
Transmit FIFO — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 271 2. Each channel (A, B, C, D) gets a unique signature that the receiver uses for identification. The scrambler...
Page 270 - Line Driver
Intel ® 82575EB Gigabit Ethernet Controller — Transmit FIFO Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 272 January 2011 11.8.2.5 Low-Pass Filter To aid with EMI, this filter attenuates signal components more than 180 Mhz. In 1000...
Page 271 - Receive Functions; Hybrid
Receive Functions — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 273 11.8.3 Receive Functions This section describes function blocks that are used when the PHY receives data ...
Page 272 - DPAM5 Decoder; Link Test
Intel ® 82575EB Gigabit Ethernet Controller — 100 Mb/s Operation Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 274 January 2011 The descrambler requires approximately 15 s. to lock, normally accomplished during the training phase....
Page 273 - 0Base-T Link Failure Criteria and Override
10Base-T Link Failure Criteria and Override — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 275 11.10.2 10Base-T Link Failure Criteria and Override Link failure occurs if Link...
Page 275 - Configurable LED Outputs
Configurable LED Outputs — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 277 12.0 Configurable LED Outputs The 82575 implements four output drivers intended for driving extern...
Page 277 - Dual Port Characteristics; Features of Each MAC
Dual Port Characteristics — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 279 13.0 Dual Port Characteristics The 82575 architecture includes two instances both the MAC and PHY...
Page 279 - MAC Configuration Register Space; FLASH Access Contention
MAC Configuration Register Space — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 281 13.1.2 MAC Configuration Register Space All device control/status registers detailed in Se...
Page 280 - Link Mode/Configuration; Overview
Intel ® 82575EB Gigabit Ethernet Controller — Link Mode/Configuration Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 282 January 2011 To avoid this contention, accesses from both LAN devices MUST be synchronized using external softwa...
Page 281 - Multi-Function Advertisement; Legacy Interrupt Use; Power Reporting; Device Disable
Multi-Function Advertisement — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 283 code of this function changes to other values 10A6h and FF00h, respectively. In addition the f...
Page 282 - BIOS Handling of Device Disable
Intel ® 82575EB Gigabit Ethernet Controller — BIOS Handling of Device Disable Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 284 January 2011 While in device disable mode, the PCIe* link is in L3 state. The PHY is in power down mode....
Page 287 - Register Descriptions; Register Conventions
Register Descriptions — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 287 14.0 Register Descriptions This section details the state inside the 82575 that are visible to the pr...
Page 289 - Memory and I/O Address Decoding; Memory-Mapped Access to Internal Registers and
Memory and I/O Address Decoding — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 289 Table 87. Field Attributes 14.1.1 Memory and I/O Address Decoding 14.1.1.1 Memory-Mapped Ac...
Page 290 - Memory-Mapped Access to Expansion ROM; IOADDR
Intel ® 82575EB Gigabit Ethernet Controller — I/O-Mapped Internal Register, Internal Memory, and Flash Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 290 January 2011 14.1.1.4 Memory-Mapped Access to Expansion ROM The external Flash ...
Page 291 - IODATA
I/O-Mapped Internal Register, Internal Memory, and Flash — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 291 14.1.2.2 IODATA The IODATA register must always be written as a DW...
Page 292 - Undefined I/O Offsets; Register Summary
Intel ® 82575EB Gigabit Ethernet Controller — Register Summary Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 292 January 2011 case, the 82575 delays the results through normal bus methods. For example, a split transaction or transac...
Page 298 - Main Register Descriptions
Intel ® 82575EB Gigabit Ethernet Controller — Main Register Descriptions Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 298 January 2011 Note: The PHY registers are accessed through the MDI/O interface. 14.3 Main Register Description...
Page 306 - Extended Device Control Register - CTRL_EXT
Intel ® 82575EB Gigabit Ethernet Controller — Extended Device Control Register - CTRL_EXT (00018h, R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 306 January 2011 14.3.5 Extended Device Control Register - CTRL_EXT (00018h, R/W) ...
Page 311 - PHY Registers
PHY Registers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 311 Note: After a PHY reset, access through the MDIC register should not be attempted for 300 s. 14.3.8 PHY Reg...
Page 316 - Auto-Negotiation Next Page Transmit Register - NPT
Intel ® 82575EB Gigabit Ethernet Controller — PHY Registers Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 316 January 2011 14.3.8.7 Auto-Negotiation Expansion Register - ANE (06d; R) 14.3.8.8 Auto-Negotiation Next Page Transmit Regi...
Page 317 - Auto-Negotiation Next Page Ability Register - LPN
PHY Registers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 317 14.3.8.9 Auto-Negotiation Next Page Ability Register - LPN (08d; R) 14.3.8.10 1000BASE-T/100BASE-T2 Control R...
Page 329 - Flow Control Transmit Timer Value - FCTTV
Flow Control Type - FCT (00030h; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 329 14.3.15 Flow Control Type - FCT (00030h; R/W) This register contains the type field t...
Page 330 - MODE Encodings for LED Outputs
Intel ® 82575EB Gigabit Ethernet Controller — LED Control - LEDCTL (00E00h; RW) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 330 January 2011 14.3.17.1 MODE Encodings for LED Outputs Table 91 lists the MODE encodings used to select...
Page 335 - Manageability EEPROM Control Register -
Manageability EEPROM Control Register - EEMNGCTL (01010h; RO) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 335 14.3.24 Manageability EEPROM Control Register - EEMNGCTL (010...
Page 336 - Manageability Flash Control Register -
Intel ® 82575EB Gigabit Ethernet Controller — Manageability EEPROM Read/Write Data - EEMNGDATA (1014h; RO) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 336 January 2011 14.3.25 Manageability EEPROM Read/Write Data - EEMNGDATA (1014...
Page 337 - Manageability Flash Read Counter - FLMNGCNT
Manageability Flash Read Counter - FLMNGCNT (1020h; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 337 (101Ch; R/W) 14.3.28 Manageability Flash Read Counter - FLMNGCNT (...
Page 338 - Watchdog SW Device Status - WDSWSTS
Intel ® 82575EB Gigabit Ethernet Controller — Watchdog Setup - WDSTP (01040h; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 338 January 2011 Note: • More than one valid bit can be set for write accesses. This results in writing...
Page 344 - Interrupt Acknowledge Auto Mask Register -
Intel ® 82575EB Gigabit Ethernet Controller — Interrupt Acknowledge Auto Mask Register - IAM (000E0h; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 344 January 2011 On interrupt handling, the software device driver should set a...
Page 347 - Extended Interrupt Auto Mask Enable - EIAM
Extended Interrupt Auto Clear - EIAC (0152Ch; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 347 Software blocks interrupts by clearing the corresponding mask bit. This ...
Page 350 - Immediate Interrupt Rx Extended - IMIREXT
Intel ® 82575EB Gigabit Ethernet Controller — Immediate Interrupt Rx Extended - IMIREXT (05AA0h + 4*n [n = 0..7]; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 350 January 2011 14.3.47 Immediate Interrupt Rx Extended - IMIREXT ...
Page 354 - Split and Replication Receive Control - SRRCTL
Intel ® 82575EB Gigabit Ethernet Controller — Split and Replication Receive Control - SRRCTL (0280Ch + 100*n [n=0..3]; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 354 January 2011 14.3.51 Split and Replication Receive Control...
Page 356 - Flow Control Receive Threshold Low - FCRTL
Intel ® 82575EB Gigabit Ethernet Controller — Flow Control Receive Threshold Low - FCRTL (02160h; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 356 January 2011 14.3.53 Flow Control Receive Threshold Low - FCRTL (02160h; R/W) T...
Page 357 - Flow Control Receive Threshold High - FCRTH; Flow Control Refresh Threshold Value - FCRTV
Flow Control Receive Threshold High - FCRTH (02168h; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 357 14.3.54 Flow Control Receive Threshold High - FCRTH (02168h; R/W)...
Page 358 - Receive Descriptor Base Address Low - RDBAL; Receive Descriptor Base Address High - RDBAH
Intel ® 82575EB Gigabit Ethernet Controller — Receive Descriptor Base Address High - RDBAH (02804h + 100*n [n=0..3]; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 358 January 2011 14.3.55.1 Receive Descriptor Base Address Low -...
Page 362 - Receive Long Packet Maximum Length - RLPML
Intel ® 82575EB Gigabit Ethernet Controller — Receive Long Packet Maximum Length - RLPML (05004; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 362 January 2011 14.3.62 Receive Long Packet Maximum Length - RLPML (05004; R/W) 14....
Page 366 - Transmit Descriptor Base Address Low - TDBAL
Intel ® 82575EB Gigabit Ethernet Controller — Transmit Descriptor Base Address Low - TDBAL (03800h + 100*n [n=0..3]; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 366 January 2011 14.3.68 Transmit Descriptor Base Address Low - ...
Page 368 - Transmit Descriptor Control - TXDCTL (03828h
Intel ® 82575EB Gigabit Ethernet Controller — Transmit Descriptor Control - TXDCTL (03828h + 100*n [n=0..3]; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 368 January 2011 • Queue1 - TDT1 (03918h)• Queue2 - TDT2 (03A18h)• Queue...
Page 369 - Tx Descriptor Completion Write-Back Address
Tx Descriptor Completion Write-Back Address Low - TDWBAL (03838h + 100*n [n=0..3]; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 369 14.3.74 Tx Descriptor Completion Wr...
Page 376 - Link Partner Ability Next Page - PCS_LPABNP; DCA Registers
Intel ® 82575EB Gigabit Ethernet Controller — Link Partner Ability Next Page - PCS_LPABNP (04224h; RO) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 376 January 2011 14.3.82 Link Partner Ability Next Page - PCS_LPABNP (04224h; RO) 1...
Page 378 - Filter Registers
Intel ® 82575EB Gigabit Ethernet Controller — Tx DCA Control Registers - TXCTL (03814h + 100h *n [n=0..3]; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 378 January 2011 14.4.2 Tx DCA Control Registers - TXCTL (03814h + 100h *n...
Page 379 - Multicast Table Arra
Multicast Table Array - MTA (05200h + 4*n [n..127]; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 379 14.5.1 Multicast Table Array - MTA (05200h + 4*n [n..127]; R/W) Th...
Page 382 - Multiple Receive Queues Command Register -
Intel ® 82575EB Gigabit Ethernet Controller — Multiple Receive Queues Command Register - MRQC (05818h; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 382 January 2011 14.5.5 Multiple Receive Queues Command Register - MRQC (05818...
Page 385 - Wakeup Registers
VLAN Filter Queue Array 0 - VFQA0 (0B100h + 4*n [n=0…127]; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 385 14.5.9 VLAN Filter Queue Array 0 - VFQA0 (0B100h + 4*n [n=0...
Page 386 - Wakeup Filter Control Register - WUFC
Intel ® 82575EB Gigabit Ethernet Controller — Wakeup Filter Control Register - WUFC (05808h; R/ W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 386 January 2011 14.6.2 Wakeup Filter Control Register - WUFC (05808h; R/W) This regist...
Page 391 - Manageability Registers; Management VLAN TAG Value - MAVTV (5010h
Manageability Registers — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 391 All reserved fields read as 0's and ignore writes. Note: Before writing to the flexible filter leng...
Page 394 - Management Control to Host Register - MANC2H
Intel ® 82575EB Gigabit Ethernet Controller — Management Control to Host Register - MANC2H (5860h; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 394 January 2011 14.7.5 Management Control to Host Register - MANC2H (5860h; R/W) ...
Page 395 - Manageability IP Address Filter - MIPAF
Manageability IP Address Filter - MIPAF (0x58B0-0x58EC; RW) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 395 14.7.7 Manageability IP Address Filter - MIPAF (0x58B0-0x58EC; ...
Page 398 - Manageability MAC Address Low - MMAL (5910h; Manageability MAC Address High - MMAH; Flexible TCO Filter Table Registers - FTFT
Intel ® 82575EB Gigabit Ethernet Controller — Manageability MAC Address Low - MMAL (5910h + 8*n[n=0..3]; RW) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 398 January 2011 14.7.8 Manageability MAC Address Low - MMAL (5910h + 8*n[n=0...
Page 408 - Function Active and Power State to MNG -
Intel ® 82575EB Gigabit Ethernet Controller — PCIe* Counter #2 - GSCN_2 (05B28h; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 408 January 2011 14.8.9 PCIe* Counter #2 - GSCN_2 (05B28h; R/W) 14.8.10 PCIe* Counter #3 - GSCN_3 (0...
Page 413 - Using the Software-Firmware Synchronization
Software-Firmware Synchronization - SW_FW_SYNC (05B5Ch; R/WS) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 413 Notes: 1. This register should be written only by the managea...
Page 416 - Statistics Registers
Intel ® 82575EB Gigabit Ethernet Controller — DCA Control - DCA_CTRL (05B74h; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 416 January 2011 14.8.25 DCA Control - DCA_CTRL (05B74h; R/W) Note: The DCA tag disabled value in data ...
Page 420 - FC Received Unsupported Count - FCRUC
Intel ® 82575EB Gigabit Ethernet Controller — XON Transmitted Count - XONTXC (0404Ch; RC) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 420 January 2011 14.9.15 XON Transmitted Count - XONTXC (0404Ch; RC) This register counts the nu...
Page 423 - Broadcast Packets Received Count - BPRC
Broadcast Packets Received Count - BPRC (04078h; RC) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 423 14.9.26 Broadcast Packets Received Count - BPRC (04078h; RC) This regi...
Page 424 - Good Octets Transmitted Count - GOTCL
Intel ® 82575EB Gigabit Ethernet Controller — Good Octets Received Count - GORCL (04088h; RC)/GORCH (0408Ch; RC) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 424 January 2011 14.9.29 Good Octets Received Count - GORCL (04088h; RC)/...
Page 426 - Management Packets Received Count - MNGPRC
Intel ® 82575EB Gigabit Ethernet Controller — Management Packets Received Count - MNGPRC (040B4h; RC) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 426 January 2011 Packets over 1518/1522/1526 bytes are oversized if LPE is 0b. If LP...
Page 429 - Packets Transmitted (1024 Bytes or Greater)
Packets Transmitted (128-255 Bytes) Count - PTC255 (040E0h; RC) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 429 14.9.45 Packets Transmitted (128-255 Bytes) Count - PTC255 ...
Page 430 - Multicast Packets Transmitted Count - MPTC
Intel ® 82575EB Gigabit Ethernet Controller — Multicast Packets Transmitted Count - MPTC (040F0h; RC) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 430 January 2011 Due to changes in the standard for maximum frame size for VLAN tagg...
Page 431 - Receive Descriptor Minimum Threshold Count -
Interrupt Assertion Count - IAC (04100h; RC) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 431 14.9.52 Interrupt Assertion Count - IAC (04100h; RC) This counter counts the t...
Page 432 - SerDes/SGMII Code Violation Packet Count -; Diagnostics Registers; Receive Data FIFO Head Register - RDFH
Intel ® 82575EB Gigabit Ethernet Controller — SerDes/SGMII Code Violation Packet Count - SCVPC (04228h; R/WS) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 432 January 2011 14.9.57 SerDes/SGMII Code Violation Packet Count - SCVPC (0...
Page 433 - Receive Data FIFO Head Saved Register -
Receive Data FIFO Head Saved Register - RDFHS (02420h; RO) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 433 14.10.3 Receive Data FIFO Head Saved Register - RDFHS (02420h; R...
Page 434 - PB Descriptor Read Pointers - PBDESCRP
Intel ® 82575EB Gigabit Ethernet Controller — PB Descriptor Read Pointers - PBDESCRP (02454h; RO) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 434 January 2011 14.10.6 PB Descriptor Read Pointers - PBDESCRP (02454h; RO) 14.10.7 Pac...
Page 435 - Transmit Data FIFO Tail Register - TDFT
Transmit Data FIFO Tail Register - TDFT (03418h; R/WS) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 435 14.10.9 Transmit Data FIFO Tail Register - TDFT (03418h; R/WS) This ...
Page 436 - Transmit Data FIFO Packet Count - TDFPC
Intel ® 82575EB Gigabit Ethernet Controller — Transmit Data FIFO Packet Count - TDFPC (03430h; RO) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 436 January 2011 14.10.12 Transmit Data FIFO Packet Count - TDFPC (03430h; RO) This reg...
Page 437 - Tx Descriptor Handler ECC Error Inject - TDHEEI
Tx Descriptor Handler ECC Error Inject - TDHEEI (035F8h; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 437 14.10.14 Tx Descriptor Handler ECC Error Inject - TDHEEI (035...
Page 438 - Packet Buffer Memory Page NPBMPN Register
Intel ® 82575EB Gigabit Ethernet Controller — Packet Buffer Memory - PBM (10000h - 10FFCh; R/ W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 438 January 2011 14.10.16 Packet Buffer Memory - PBM (10000h - 10FFCh; R/W) All PBM (FIFO...
Page 439 - Tx Descriptor Handler Memory Page Number -
Tx Descriptor Handler Memory Page Number - TDHMP (035FCh; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 439 Note: The queue depth field must be updated before the recei...
Page 440 - Rx Descriptor Handler ECC Status - RDHESTS
Intel ® 82575EB Gigabit Ethernet Controller — Packet Buffer ECC Status - PBECCSTS (0245Ch; R/ W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 440 January 2011 14.10.20 Packet Buffer ECC Status - PBECCSTS (0245Ch; R/W) 14.10.21 Rx D...
Page 441 - Tx Descriptor Handler ECC Status - TDHESTS; Packet Generator Registers; Packet Generator Destination Address Low -
Tx Descriptor Handler ECC Status - TDHESTS (0246Ch; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 441 14.10.22 Tx Descriptor Handler ECC Status - TDHESTS (0246Ch; R/W) ...
Page 442 - Packet Generator Source Address Low - PGSAL
Intel ® 82575EB Gigabit Ethernet Controller — Packet Generator Source Address Low - PGSAL (04288h; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 442 January 2011 14.11.3 Packet Generator Source Address Low - PGSAL (04288h; R/W)...
Page 443 - Packet Generator Packet Length - PGPL
Packet Generator Packet Length - PGPL (04294h; R/W) — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 443 14.11.6 Packet Generator Packet Length - PGPL (04294h; R/W) The actual ...
Page 444 - Packet Generator StaPGSTS Bit Description
Intel ® 82575EB Gigabit Ethernet Controller — Packet Generator StaPGSTS Bit Description Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 444 January 2011 14.11.8 Packet Generator StaPGSTS Bit Description 14.11.9 Packet Generator ContPG...
Page 446 - MSI-X Table Entry Lower Address - MSIXTADD
Intel ® 82575EB Gigabit Ethernet Controller — MSI-X Table Entry Lower Address - MSIXTADD (00000h - 00090h; R/W) Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 446 January 2011 14.12.1 MSI-X Table Entry Lower Address - MSIXTADD (00000...
Page 449 - Diagnostics and Testability; Diagnostics; FIFO Pointer Accessibility
Diagnostics and Testability — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 449 15.0 Diagnostics and Testability 15.1 Diagnostics To assist in test and debug of device-driver ...
Page 450 - Testability; EXTEST Instruction
Intel ® 82575EB Gigabit Ethernet Controller — Testability Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Software Developer’s Manual and EEPROM Guide Revision: 2.1 450 January 2011 • MAC Loopback while operating with the internal PHY.• MAC Loopback, by setting the LBM bits in RCTL register t...
Page 451 - BYPASS Instruction
BYPASS Instruction — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 451 15.2.4 BYPASS Instruction This instruction is the only instruction defined by the standard that causes o...
Page 455 - RMON
RMON — Intel ® 82575EB Gigabit Ethernet Controller 324632-003 Intel ® 82575EB Gigabit Ethernet Controller Revision: 2.1 Software Developer’s Manual and EEPROM Guide January 2011 455 16.3 RMON The 82575 supports the part of the RMON Ethernet statistics group as defined by IETF RFC 2819. The following...
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