Analog Devices AD9883A - Manuals

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Manual

Manual Analog Devices AD9883A

Summary

Page 2 - Analog Interface

REV. 0 – 2 – AD9883A–SPECIFICATIONS Test AD9883AKST-110 AD9883AKST-140 Parameter Temp Level Min Typ Max Min Typ Max Unit RESOLUTION 8 8 Bits DC ACCURACY Differential Nonlinearity 25 ° C I ± 0.5 +1.25/–1.0 ± 0.5 +1.35/–1.0 LSB Full VI +1.35/–1.0 +1.45/–1.0 LSB Integral Nonlinearity 25 ° C I ± 0.5 ± 1...

Page 4 - CAUTION; ABSOLUTE MAXIMUM RATINGS

REV. 0 AD9883A – 4 – CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readilyaccumulate on the human body and test equipment and can discharge without detection. Althoughthe AD9883A features proprietary ESD protection circuitry, permanent damage may occ...

Page 5 - PIN CONFIGURATION; Table I. Complete Pinout List

REV. 0 – 5 – AD9883A PIN CONFIGURATION GND GREEN <7> GREEN <6> GREEN <5> GREEN <4> GREEN <3> GREEN <2> GREEN <1> GREEN <0> GND V DD BLUE <7> BLUE <6> BLUE <5> BLUE <4> BLUE <3> BLUE <2> BLUE <1> BLUE <0> ...

Page 7 - not; POWER SUPPLY; Digital Inputs

REV. 0 AD9883A – 7 – PIN FUNCTION DESCRIPTIONS (continued) Pin Name Function CLAMP External Clamp Input This logic input may be used to define the time during which the input signal is clamped to ground. It should beexercised when the reference dc level is known to be present on the analog input cha...

Page 8 - At that point the signal should be resistively terminated (75; Figure 1. Analog Input Interface Circuit; Serial Control Port; as; RGB Clamping; F capacitor, (even if midscale clamping is

REV. 0 AD9883A – 8 – At that point the signal should be resistively terminated (75 Ω to the signal ground return) and capacitively coupled to theAD9883A inputs through 47 nF capacitors. These capacitorsform part of the dc restoration circuit. In an ideal world of perfectly matched impedances, the be...

Page 9 - Figure 2. Gain and Offset Control; Gain and Offset Control; Figure 3. Typical Clamp Configuration; Clock Generation; Figure 4. Pixel Sampling Times; Figure 5. Pixel Clock Jitter vs. Frequency

REV. 0 AD9883A – 9 – GAIN 1.0 0.0 00h FFh INPUT RANGE – Volts 0.5 OFFSET = 00h OFFSET = 3Fh OFFSET = 7Fh OFFSET = 00h OFFSET = 7Fh OFFSET = 3Fh Figure 2. Gain and Offset Control Gain and Offset Control The AD9883A can accommodate input signals with inputsranging from 0.5 V to 1.0 V full scale. The f...

Page 10 - Figure 6. PLL Loop Filter Detail; Table II. VCO Frequency Ranges; Table III. Charge Pump Current/Control Bits; NOTES

REV. 0 AD9883A – 1 0 – The PLL characteristics are determined by the loop filter design,by the PLL Charge Pump Current and by the VCO range setting.The loop filter design is illustrated in Figure 6. Recommendedsettings of VCO range and charge pump current for VESAstandard display modes are listed in...

Page 11 - Figure 7. Output Timing; Hsync Timing

REV. 0 AD9883A – 1 1 – Table V. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats Refresh Horizontal Standard Resolution Rate Frequency Pixel Rate VCORNGE Current VGA 640 × 480 60 Hz 31.5 kHz 25.175 MHz 00 101 72 Hz 37.7 kHz 31.500 MHz 00 110 75 Hz 37.5 kHz 31.500 M...

Page 13 - Vsync will be used only if Bit 1 is set to Logic 1.

REV. 0 AD9883A – 1 3 – 2-Wire Serial Register Map The AD9883A is initialized and controlled by a set of registers, which determine the operating modes. An external controller isemployed to write and read the Control Registers through the 2-line serial interface port. Table VI. Control Register Map W...

Page 14 - PWRDN

REV. 0 AD9883A – 1 4 – Table VI. Control Register Map (continued) Write and Hex Read or Default Register Address Read Only Bits Value Name Function 0FH R/ W 7:1 0 ******* Bit 7 – Clamp Function. Chooses between HSYNC for Clampsignal or another external signal to be used for clamping.(Logic 0 = HSYNC...

Page 15 - NOTE; TWO-WIRE SERIAL CONTROL REGISTER DETAIL; VCORNGE

REV. 0 AD9883A – 1 5 – Table VI. Control Register Map (continued) Write and Hex Read or Default Register Address Read Only Bits Value Name Function 15H R/ W 7:0 Test Register Bits [7:2] Reserved for future use.Bit 1 – 4:2:2 Output Formatting Mode.Bit 0 – Must be set to 0 for proper operation. 16H R/...

Page 16 - decreases; Override Bit; falling

REV. 0 AD9883A – 1 6 – 04 7–3 Clock Phase Adjust A 5-bit value that adjusts the sampling phase in 32 stepsacross one pixel time. Each step represents an 11.25 ° shift in sampling phase. The power-up default value is 16. CLAMP TIMING05 7–0 Clamp Placement An 8-bit register that sets the position of t...

Page 21 - Serial Interface Read/Write Examples; Figure 11. Serial Interface—Typical Byte Transfer

REV. 0 AD9883A – 2 1 – Data is read from the control registers of the AD9883A in a similarmanner. Reading requires two data transfer operations: The base address must be written with the R/ W bit of the slave address byte LOW to set up a sequential read operation. Reading (the R/ W bit of the slave ...

Page 23 - Figure 13. Current Loop; PLL

REV. 0 AD9883A – 2 3 – It is also recommended to use a single ground plane for the entireboard. Experience has repeatedly shown that the noise perfor-mance is the same or better with a single ground plane. Usingmultiple ground planes can be detrimental because each separateground plane is smaller, a...

Page 24 - OUTLINE DIMENSIONS

REV. 0 – 2 4 – C02561–1–10/01(0) PRINTED IN U.S.A. AD9883A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 80-Lead LQFP (ST-80) 61 60 1 80 20 41 21 40 TOP VIEW (PINS DOWN) PIN 1 0.630 (16.00) BSC SQ 0.551 (14.00) BSC SQ SEATING PLANE 0.063 (1.60) MAX 0.004 (0.10) MAX COPLANARITY 0.006 (0.15)...