Analog Devices ADSP-2192 - Manual

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Page 6 – Figure 1 on page 1
Page 8 – Card Bus interface; Target/Slave Interface; and; Bus Master Interface
Page 9 – PCI Interr upts; Table 5 on page 9; PCI Control Register.; Table 5. PCI Interrupt Register
Page 17 – USB DSP Register Definitions
Page 18 – USB DSP Memor y Buffer Base Addr Register; Page
Page 21 – ST 1 = Endpoint is stalled; USB Endpoint Stall Policy Register
Page 25 – DSP Code Download
Page 26 – Example Initialization Process; XXX
Page 27 – ADSP-2192 USB Data Pipe Operations
Page 30 – FIFO Control Registers; Table 25. AC’97 Slot Select Values
Page 35 – Signal
Page 42 – RECOMMENDED OPERATING CONDITIONS; ELECTRICAL CHARACTERISTICS
Page 43 – TIMING SPECIFICATIONS; ABSOLUTE MAXIMUM RATINGS; ESD SENSITIVITY
Page 44 – Figure 12. Sub-ISA Interface Read Cycle Timing Diagram
Page 45 – Figure 13. Sub-ISA Interface Write Cycle Timing Diagram
Page 46 – Total power dissipation for the ADSP-2192 is TBD.; TEST CONDITIONS; PD = Power Dissipation in W; Rating Description
Page 50 – ORDERING GUIDE; Part Number

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Preliminary Technical Data

DSP

Microcomputer

This information applies to a product under development. Its characteristics
and specifications are subject to change without notice. Analog Devices
assumes no obligation regarding future manufacturing unless otherwise
agreed to in writing.

One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700

World Wide Web Site: http://www.analog.com

Fax:781/326-8703

©Analog Devices,Inc., 2000

REV. PrA

ADSP-2192

ADSP-2192 DUAL-CORE DSP FEATURES
320 MIP Dual ADSP-219x DSP in a 144-lead LQFP

package with PCI, USB, Sub-ISA, and CardBus
Interfaces

3.3V/5V PCI 2.2 Compliant 33MHz / 32-bit Interface with

Bus Mastering over four DMA Channels with
Scatter-Gather Support

Integrated USB 1.1 Compliant Interface
AC ‘97 serial interface supports external modem,

handset, and audio codecs

Dual 160 MIPS ADSP-219x DSPs with 140K Words of

Memory and 4K x 16-bit Shared Data Memory

DSP P0 Memory Includes: 64K x 16-bit Data Memory,

16K x 24-bit Program Memory, and Boot ROM

DSP P1 Memory Includes: 32K x 16-bit Data Memory,

16K x 24-bit Program Memory, and Boot ROM

ADSP-219X DSP CORE FEATURES
6.25 ns Instruction Cycle Time (Internal), for up to 160

MIPS Sustained Performance

ADSP-218x Family Code Compatible with the Same

Easy to Use Algebraic Syntax

Single-cycle Instruction Execution
Dual Purpose Program Memory for Both Instruction and

Data Storage

Fully Transparent Instruction Cache Allows Dual

Operand Fetches in Every Instruction Cycle

Unified Memory Space Permits Flexible Address

Generation, Using Two Independent DAG Units

Independent ALU, Multiplier/Accumulator, and Barrel

Shifter Computational Units with Dual 40-bit
Accumulators

Figure 1. ADSP-2192 Dual-Core DSP Block Diagram

INTERRUPT CONTRO LLER/

TIMER/FLA GS

CACHE

64 X 24-BIT

PM ADDRESS BUS

DM ADDRESS BUS

PM DATA BUS

DM DATA BUS

ADSP-219X

DSP CORE

DATA

REGISTER

FILE

MULT

BARREL
SHIFTER

ALU

INPUT

REGISTERS

RESULT

REGISTERS

16 X 16-BIT

CORE

INTERFACE

BUS

CONNECT

(PX)

PROGRAM

SEQUENCER

DAG1

4X4 X16

DAG2

4X4X16

INTERRUPT CONTRO LLER/

TIMER/FLAGS

CACHE

64 X 24-BIT

PM ADDRESS BUS

DM ADDRESS BUS

PM DATA BUS

DM DATA BUS

2 4

1 6

ADSP-219X

DSP CORE

DATA

REGISTER

FILE

MULT

BARREL

SHIFTER

ALU

INPUT

REGISTERS

RESULT

REGISTERS

16 X 16-BIT

CORE

INTERFACE

2 4

BUS

CONNECT

(PX)

PROGRAM

SEQUENCER

DAG1

4X4X16

DAG2

4X4X16

P R O C E S S O R P 0

P R O C E S S O R P 1

SHARED

MEMORY

ⴛ

16 DM

ADDR

DATA

MEMORY

16K

ⴛ

24 PM

64K

ⴛ

16 DM

BOOT ROM

MEMORY

16K

ⴛ

24 PM

32K

ⴛ

16 DM

BOOT ROM

ADDR

DATA

ADDR

DATA

P0 DMA

CONTROLLE R

FIFOS

SHARED DSP

I/O MAPPED

REGISTERS

P1 DMA

CONTROLLE R

FIFOS

ADDR

DATA

HOST PORT

PCI 2.2

USB 1.1

SERIAL PORT

AC'97

COMPLIANT

GP I/O PINS

(& OPTIONAL

SERIAL

EEPROM)

JTAG

EMULATION

PORT

ADDR

DATA

ADDR

DATA

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Summary

Page 6 - Figure 1 on page 1

PR EL IM IN AR Y TE CH NI CA L DA TA PR EL IM IN AR Y TE CH NI CA L DA TA For current information contact Analog Devices at (781) 461-3881 ADSP-2192 October 2000 This information applies to a product under development. Its characteristics and specifications are subject to change with-out notice. Ana...

Page 8 - Card Bus interface; Target/Slave Interface; and; Bus Master Interface

Page 9 - PCI Interr upts; Table 5 on page 9; PCI Control Register.; Table 5. PCI Interrupt Register

PR EL IM IN AR Y TE CH NI CA L DA TA PR EL IM IN AR Y TE CH NI CA L DA TA This information applies to a product under development. Its characteristics and specifications are subject to change with-out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed...